PEF 20954 HT V1.1 Infineon Technologies, PEF 20954 HT V1.1 Datasheet

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PEF 20954 HT V1.1

Manufacturer Part Number
PEF 20954 HT V1.1
Description
IC ECHO CANCELLER DGTL TQFP144
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20954 HT V1.1

Function
Smart Integrated Digital Echo Canceller (SIDEC)
Interface
PCM, Serial, UCC
Number Of Circuits
1
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
350mA
Power (watts)
900mW
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
144-LFQFP
Includes
Double Talk Detection
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
PEF20954HTV1.1
SP000007505
D a t a S he e t , R ev . 2 , J u l y 20 0 4
SIDEC
S m a r t I n t e g r a t e d D i g i t a l E c h o C a n c e l l e r
P E F / P E B 2 0 9 5 4 H T , V e r s i o n 1 . 1
P E F / P E B 2 0 9 5 4 E , V e r s i o n 1 . 1
W i r e l i n e C o m m u n i c a t i o n s
N e v e r
s t o p
t h i n k i n g .

Related parts for PEF 20954 HT V1.1

PEF 20954 HT V1.1 Summary of contents

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SIDEC ...

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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...

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SIDEC Revision History: Previous Version: Page Subjects (major changes since last revision) Changes from previous version DS3, 2003-06-01 to DS4, 2003-09-01 Page 141 timing t_smon_delay document rearranged Additional configuration hints in the Page 51 and following pages 2004-07-28 Data Sheet, ...

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Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 4.3.4.1 Coefficient damping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 6.6.8.1 Intel Mode (IM0='0 ...

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List of Figures Figure 1 Logic Symbol of the SIDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Figures Figure 43 Read Timing in Demultiplexed Intel Mode (IM0='0', IM1='1 149 Figure 44 Write Timing in Demultiplexed Intel Mode (IM0='0', IM1='1 149 Figure ...

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List of Tables Table 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Tables Table 43 Serial Interface (Controlling and Monitoring) Timing (preliminary 140 Table 44 UCC Interface Signal Timing and Frame Alignment (preliminary 145 Table 45 Preliminary Internal Read and Write Signal Timing . . ...

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Introduction The Smart Integrated Digital Echo Canceller (SIDEC) suppresses echoes in telecommunication networks which might disturb any kind of terrestrial or wireless communication. It incorporates leading edge CMOS technology as well as INFINEON’s' many years' experience in Telecommunication ICs. ...

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SIDEC Smart Integrated Digital Echo Canceller Version 1.1 1.1 Key Features • 2.048 MHz PCM input and output interfaces with selectable - and A-Law coding according to ITU G.711 • Rapid convergence of patented algorithm at the beginning or during ...

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Integrated Universal Control and Communication Interface (UCCI) for signaling highways with direct hardware control for: – disable cancelling – configurable disabling functions – communication between board controllers • Support of Channel Associated Signaling (CAS) BR transparency (robbed bits) in ...

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Ordering Information Table 1 Ordering Information Product Package PEB 20954 HT P-TQFP 144 PEF 20954 HT P-TQFP 144-8 (- P-LFBGA-160-2 PEB 20954 E P-LFBGA-160-2 PEF 20954E Data Sheet Q-Number Q67003 H9363 ...

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Logic Symbol General Pins PORES MODE1 MODE0 Synchronization CLK32SEL CLK32 CTRL32 SCLKI SCLKO SYNCI SYNCO SDECI SDECO RFCLKF RFCLKN RFCLKEX CLK16 CTRL16 RFSPF RFSPN CLK4O SO128 Speech RO128 Highway Interface Figure 1 Logic Symbol of ...

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Typical Applications The SIDEC can be used for various applications. Figure 2 to Figure 5 display typical examples. SDH or PDH FALC Network 56 PEB 2256 SDH: Synchronous Digital Hierarchy PDH: Plesiochronous Digital Hierarchy Asynchronous Transfer Mode ATM: Figure ...

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PSTN Figure 3 SIDEC in a Voice over IP Gateway An emerging market in the telecom industry is “Voice Over IP”. Due to the long delay echo cancellation is required. The delay is introduced through packetizing and voice compression. The ...

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POTS HV- SLIC HV- POTS SLIC HV- SLIC HV- POTS SLIC POTS Echo HV- SLIC HV- SLIC POTS POTS PBX: Private Branch eXchange SLICOFI: Signal Processing with integrated Subscriber Line Interface Circuit Codec Filter Figure 4 SIDEC in ...

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POTS MSC POTS Echo POTS E1/T1 SIDEC POTS TRAU: Transcoder Rate Adaptor Unit MSC: Mobile Switching Center Figure 5 SIDEC in a Wireless System Due to voice compression and error correction the one way transmission time for wireless voice signals ...

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Pin Description 2.1 Pin Diagram NC 109 NC 110 CLK32SEL 111 MODE1 112 MODE0 113 PORES 114 VDD 115 VSS 116 CLK4O 117 SYNCO 118 SCLKO 119 SDECO 120 VDD 121 122 CTRL32 123 VDD 124 VSS 125 CLK32 ...

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CTRL16 RFSPF_N RFCLKF 13 MODE1 CLK32SEL NC RFSPN_N 12 PORES_N MODE0 VSS VDD 11 SYNCO CLK4O VDD VSS 10 SDECO SCLKO VSS VDD 9 CTRL32 NC VDD VSS 8 CLK32 NC VDD VDD 7 ...

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Pin Definitions and Functions for the P-TQFP-144-8 package Table 2 General Pins Pin No. Symbol 114 PORES 112 MODE1 113 MODE0 112 MODE1 113 MODE0 Table 3 Synchronization Pin No. Symbol 111 CLK32SEL 126 CLK32 123 CTRL32 130 SCLKI ...

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Table 3 Synchronization (cont’d) Pin No. Symbol 131 SYNCI 118 SYNCO 120 SDECO 129 SDECI 101 RFCLKF 100 RFCLKN Data Sheet I/O, PU/PD Function I, PU System Synchronization input pulse. Defines the frame alignment of PCM and UCCI signals in ...

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Table 3 Synchronization (cont’d) Pin No. Symbol 99 RFCLKEX 96 CLK16 106 CTRL16 103 RFSPF 102 RFSPN Table 4 Microprocessor Interface Pin No. Symbol 78 IM0 77 IM1 71 CS0 70 CS1 46-43 A0..A6 40-38 58-55 AD0..AD7 52-49 Data Sheet ...

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Table 4 Microprocessor Interface (cont’d) Pin No. Symbol 67 ALE 69 RD/DS 68 WR/RW 64 INT 61 RDY Table 5 Microcontroller Port Extension Pin No. Symbol 27 UPIO0 28 UPIO1 29 UPIO2 30 UPIO3 Data Sheet I/O, PU/PD Function I, ...

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Table 6 Processor Watchdog Circuit Pin No. Symbol 63 UPRES 62 UPRES 33 DISWD 34 UPRESI Table 7 Speech Highways Pin No. Symbol Data Sheet I/O, PU/PD Function O P-Reset. High pulse ...

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Table 7 Speech Highways Pin No. Symbol 88 SO128 87 RO128 Table 8 UCC Interface Pin No. Symbol 132 UCCI Data Sheet I/O, PU/PD Function I/O, PU Auxiliary 2.048 Mbit/s Send speech highway output in 128 ms mode. Input in ...

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Table 8 UCC Interface Pin No. Symbol 135 UCCO 136 TUCCO Table 9 Speech Highway Control Signals for CAS in T1 Systems Pin No. Symbol 82 TSIGM 81 TMFBI 93 TMFBO Table 10 Channelwise Serial Interface Pin No. Symbol 12 ...

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Table 10 Channelwise Serial Interface (cont’d) Pin No. Symbol 10 FREEZE 9 CONVDIS 8 ENCC 7 FLEXSCTR 24 DISMON 23 NLPDISMON 22 FREEZEMON O 21 HRESMON 18 FLEXMON1 Data Sheet I/O, PU/PD Function I, PD Serial 256 kbit/s signal to ...

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Table 10 Channelwise Serial Interface (cont’d) Pin No. Symbol 17 FLEXMON2 16 CONVDISMON O 15 CCMON Table 11 Test Interface for Boundary Scan according to IEEE 1149.1 Pin No. Symbol 1 TDI 144 TDO 2 TMS 3 TCK 4 TRST ...

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Table 12 Test Interface (cont’d) Pin No. Symbol 139 KSCEN 141 TEST Note: The Test interface will be used by the manufacturer. For normal operation, this pins should be connected to the recommended fixed value in the table. Table 13 ...

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Pin Definitions and Functions for the P-LFBGA-160-2 Package Table 15 General Pins Ball No. Symbol A12 PORES A13 MODE1 B12 MODE0 A13 MODE1 B12 MODE0 Table 16 Synchronization Ball No. Symbol B13 CLK32SEL A8 CLK32 A9 CTRL32 B7 SCLKI ...

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Table 16 Synchronization (cont’d) Ball No. Symbol A6 SYNCI A11 SYNCO A10 SDECO A7 SDECI D14 RFCLKF E13 RFCLKN Data Sheet I/O, PU/PD Function I, PU System Synchronization input pulse. Defines the frame alignment of PCM and UCCI signals in ...

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Table 16 Synchronization (cont’d) Ball No. Symbol E14 RFCLKEX F13 CLK16 B14 CTRL16 C14 RFSPF D13 RFSPN Table 17 Microprocessor Interface Ball No. Symbol M14 IM0 N14 IM1 P14 CS0 P13 CS1 N5,P4, A0..A6 N4,P3, N3,P2N 2 P9,N8,P AD0..AD7 8,P7,N7 ...

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Table 17 Microprocessor Interface Ball No. Symbol N11 ALE N12 RD/DS P12 WR/RW P11 INT N9 RDY Table 18 Microcontroller Port Extension Ball No. Symbol L1 UPIO0 L2 UPIO1 M1 UPIO2 M2 UPIO3 Data Sheet I/O, PU/PD Function I, PU ...

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Table 19 Processor Watchdog Circuit Ball No. Symbol N10 UPRES P10 UPRES N1 DISWD P1 UPRESI Table 20 Speech Highways Ball No. Symbol J13 SI K14 RI G13 SO G14 RO Data Sheet I/O, PU/PD Function O P-Reset. High pulse ...

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Table 20 Speech Highways Ball No. Symbol H14 SO128 H13 RO128 Table 21 UCC Interface Ball No. Symbol B6 UCCI Data Sheet I/O, PU/PD Function I/O, PU Auxiliary 2.048 Mbit/s Send speech highway output in 128 ms mode. Input in ...

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Table 21 UCC Interface Ball No. Symbol A5 UCCO B5 TUCCO Table 22 Speech Highway Control Signals for CAS in T1 Systems Pin No. Symbol K13 TSIGM L14 TMFBI F14 TMFBO Table 23 Channelwise Serial Interface Pin No. Symbol F1 ...

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Table 23 Channelwise Serial Interface (cont’d) Pin No. Symbol E1 FREEZE E2 CONVDIS D1 ENCC D2 FLEXSCTR K2 DISMON K1 NLPDISMON J2 FREEZEMON O J1 HRESMON H2 FLEXMON1 Data Sheet I/O, PU/PD Function I, PD Serial 256 kbit/s signal to ...

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Table 23 Channelwise Serial Interface (cont’d) Pin No. Symbol H1 FLEXMON2 G1 CONVDISMON O G2 CCMON Table 24 Test Interface for Boundary Scan according to IEEE 1149.1 Ball No. Symbol B2 TDI A1 TDO B1 TMS C2 TCK C1 TRST ...

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Table 25 Test Interface (cont’d) Pin No. Symbol A4 KSCEN A2 TEST Note: The Test interface will be used by the manufacturer. For normal operation, this pins should be connected to the recommended fixed value in the table. Table 26 ...

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Table 27 Unused Pins Pin No. Symbol A14,B3,B4,B NC 8,B9,C13,L1 3,M13,N13,J 14 Data Sheet I/O, PU/PD Function Common ground rail 42 PEB 20954 PEF 20954 Pin Description Rev. 2, 2004-07-28 ...

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Functional Description 3.1 Functional Block Diagram and Description Send In PCM Input Send Path Interface Adaptive Echo Near End Estimation Unit with echo path UCCI Receive Out PCM Output Receive Path Interface Figure 8 Block Diagram The following paragraphs ...

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Section Figure necessary. The H-Register reset signal is also provided by the Speech Control. 3.1.2 Disabling Logic Upon request of the Speech Control and depending on external inputs the Disabling Logic disables the Non Linear Processor and/or the ...

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Offset adjustment is implemented at the output of the canceller. The attenuation of 0 dB, 2 programmable by a register. The use of this feature requires that the cancelling function for the corresponding timeslot is ...

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A/ -Law conversion can be operated directly by the hardware without intervention of the microprocessor. This feature reduces the work load of the processor dramatically. 3.1.9 Watchdog Timer A Watchdog timer is ...

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Description of Functional Features 3.2.1 Channelwise and Global A- and -Law Conversion The SIDEC allows channel individual conversion. of the different options for the requirements of the application two settings can be configured: Either global ...

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CHCTRL0-31.CONVDIS 0 possible conversion channel individual configuration via CHCTRL[7:5] 1 CONFLAW.CHIND 0 1 CHCTRL0-31.CONVDIS global 0 configuration via possible CONFLAW[2:0] conversion Figure 9 Explanation of Options for A- and -Law Conversion 3.2.2 Bypass and Disabling Functions Figure 10 depicts ...

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Send Path '0' Frame log RSLOOP Alignm. '1' 64 Clear Frame Alignm. '0' RBYPASS '1' Figure 10 Bypass and Disabling Functions of the SIDEC 3.2.3 UCC Interface The UCC Interface uses a clock frequency of 2048 kHz. The UCC ...

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SCLKI SYNCI 125 s frame 3 frame 4 UCCI UCCO frame 3 frame 4 SCLKI SYNCI frame 4, channel 31 UCCI frame 4, channel 31 UCCO TUCCO SCLKI SYNCI frame 3, channel 31 UCCI Bit 0 SMLP* frame 3, channel ...

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Operational Description 4.1 Pin Connection Diagram for SIDEC Figure 12 illustrates an example for the pin connection of the SIDEC to an E1/T1 IC and to an interworking element IC. The SIDEC is used to cancel the echo on ...

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Synchronization and Clock Modes The SIDEC can be connected in different synchronization and clock modes. These modes can be used for several applications. Basically there are two clock modes, slave and master clock mode (not to be mixed up ...

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VCO SCLKI 8.192MHz SDECI n.c. Figure 14 Master Clock Mode with External 8.192 MHz Clock In the master clock mode with 8.192 MHz clock clock is supplied by the VCO. The SIDEC provides a controlling voltage for the VCO in ...

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SCLKI SDECI Figure 15 Slave Clock Mode with External 8.192 MHz and 32.768 MHz In the slave clock mode the 8.192 MHz and the 32.768 MHz clock have to be synchronous and phase aligned (e.g. SCLKI has been derived from ...

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VCXO RFCLKF RFCLKN RFCLKEX 2 MHz Figure 16 Reference Clock Mode with 2.048 MHz In this mode a 2.048 MHz system clock is provided at either the RFCLKF, RFCLKN or the RFCLKEX pin. The VCXO and VCO supply the operating ...

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SCLKI SI RO SDECI SCLKI SI Figure 17 128 ms Delay Mode The pin connection of a 128 ms master and slave SIDEC is shown in and RI is supplied to both SIDECs. The RO and SO is provided by ...

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SDECI V DD SCLKI SI RO SDECI SCLKI SI RO Figure 18 Multiple SIDEC In multiple SIDEC mode the output SDECO of the clock master SIDEC is used to synchronize clock slave SIDECs to the system clock. In this application ...

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SCLKI SYNCI (SYNCO) channel 26 RI Bit 2 Bit 1 Bit 0 SI Bit 0 Bit 7 channel 26 RO Bit 2 Bit 1 Bit 0 channel 2 SO Bit 3 Bit 2 SCLKI SYNCI (SYNCO) sampling ...

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RIALIGN, SIALIGN an SOALIGN. For finer adjustments, the valid bit phase of the PCM signals at the first detection of an active SYNCI with the falling edge of SCLKI can be configured by writing to the register PHALIGN. The ...

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Timing of SYNCI and SYNCO SYNCI is clocked in with the falling edge and SYNCO is clocked out with the rising edge of SCLKI, SYNCI and SYNCO are active low (CONFCC.SSCLKEDGE = '0' and CONFCC.SYNCACT = '0') SCLKI SYNCI ...

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Clock Timing within External VCO Capture Range SCLKI Lock-in at 0° CLK32 internal 8Mhz clock CTRL32 Lock-in at 90° CLK32 internal 8Mhz clock CTRL32 Lock-in at 180° CLK32 internal 8Mhz clock CTRL32 Figure 23 Clock Timing within External VCO ...

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Serial Interface (Controlling and Monitoring) Timing CLK32 SCLKO SDECO 6 serial control inputs serial monitor channel 30 outputs CLK32 SCLKO SDECO serial control inputs serial monitor outputs Figure 24 Serial Interface (Controlling and Monitoring) Timing Data Sheet sampling of ...

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UCC Interface Signal Timing and Frame Alignment SCLKI SYNCI (SYNCO) UCCI ...

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UCCMFR. For finer adjustments, the valid bit phase of the UCC signals at the first detection of an active SYNCI with the falling edge of SCLKI can be configured by writing to the two MSBs of register PHALIGN. The ...

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Special Cases for Multiframe Alignment Case 1: SYNCI at channel 31, bit 0, phase 3 SCLKI SYNCI (SYNCO) UCCI/UCCO Phase 1 Case 2: SYNCI at channel 0, bit 7, phase 0 SCLKI SYNCI (SYNCO) UCCI/UCCO Phase 1 Timing Characteristics SCLKI ...

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Speech Highway Control Signals for CAS in T1 Systems Frame 1 SI TMFBI Transmit Multiframe Begin; indication bit 7 channel 0 SYNCI System Synchronisation Input Pulse Using FALC in channel translation mode TSIGM marks robbed ...

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Microprocessor Interface The SIDEC Microprocessor Interface supports both, Intel and Motorola mode. In each mode the address can be provided either through the multiplexed address/data or a parallel address bus. In multiplexed mode the address is always sampled with ...

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Stability / divergence protection 4.3.4.1 Coefficient damping A configurable damping feature of main and auxiliary coefficients increases the algorithmical stability even further, thus preventing possible divergence even in difficult situation. 4.3.4.2 Auxiliary coefficient supervision In order to prevent misadaptation ...

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In ITU comfort noise mode SIDEC inserts a white noise with a constant amplitude and sign generated by a PN-generator. In the SIDEC unique subjective mode, SIDEC simply limits the outgoing SO signal to an amplitude defined by the adaptive ...

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Operational functions configuration This sections shows you the correlation of the different SIDEC configuration registers settings with the SIDEC operational functions and the effect of the settings on these functions. For further explanation or the exact values please refer ...

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Table 29 Filter coefficient adaptation speed adjustment (cont’d) Register Addr. Value ATMAT 77H TURBO Up Modification of the AFSTC has some dramatic effect on stability and convergence speed, be careful with those settings. Modification of the turbo threshold is not ...

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Table 31 Auxiliary coefficient supervision (cont’d) Register Addr. Value ACSEFF ECT ATMAT 77H TURBO AACSC modifications mainly prevent misadaptation and divergence on periodical signals. The effect is not very strong but noticeable. Be careful not to unnecessarily activate the feature, ...

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Table 32 Sinusoidal (non-voice) signal protection (cont’d) Register Addr. Value VDDIFF AVDCI 75H VDCI CONFSCU 12H ADAPTFAST 1 ADAPTSLOW VDFCTRL defines the effects on the detection of a non-voice event. For stability reasons the adaptive algorithm should be frozen (VDFCTRL. ...

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Table 33 Overcompensation protection Register Addr. Value CONFSCU4 15H OCINC OCDEC SIADD OCAMR ES OCHRE S SIDEC detects an overcompensation if the level of the supposedly echocancelled output signal SO is higher than the SI input signal level by an ...

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Table 34 Background noise measurement Register Addr. Value CONFSCU7 18H NOISEINC Up BNINC BNDEC CONFSCU8 19H BNMAXSL Up BNMAXRL Up The final resulting inserted comfort noise level can be configured mainly by modifying the value CONFSCU7.NOISEINC. Please keep in mind ...

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CONFSCU8. BNMAXRL behaves the same way for the RI signal and may be lowered in order to reduce the effect ...

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Register Description 5.1 Detailed Register Description In the following section the meaning and addresses of the registers of the SIDEC are described, The addresses and reset values are given in Hex-Code indicated by a subsequent capital H. A number ...

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Addr Short Name . 10H UCCALIGN 11H PHALIGN 12H CONFSCU1 13H CONFSCU2 14H CONFSCU3 15H CONFSCU4 16H CONFSCU5 17H CONFSCU6 18H CONFSCU7 19H CONFSCU8 1AH CONFSCU9 1BH CONFSCU10 1CH CONFPSD 1DH CONFSS7 1EH MONSIL 1FH MONSOL 20H MONRIL 21H MONOFSI ...

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Addr Short Name . 29H MONSI 2AH MONSO 2BH MONRI 2CH MONSTAT1 2DH MONSTAT2 2EH MONSTAT3 2FH CTRLTSMON 30H CONFPCM 31H CONFTS16 32H CONFIDLE 33H IDLEMASK 34H IDLEPATTERN 35H ATE 36H SFATSES 37H TESTTIMER 38H CTRLTEST 39H TSGSPP 3AH TSGRPP ...

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Addr Short Name . 3FH CONFLAW 40H CHCTRL0 41H CHCTRL1 42H CHCTRL2 43H CHCTRL3 44H CHCTRL4 45H CHCTRL5 46H CHCTRL6 47H CHCTRL7 48H CHCTRL8 49H CHCTRL9 4AH CHCTRL10 4BH CHCTRL11 4CH CHCTRL12 4DH CHCTRL13 4EH CHCTRL14 4FH CHCTRL15 50H CHCTRL16 ...

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Addr Short Name . 5CH CHCTRL28 5DH CHCTRL29 5EH CHCTRL30 5FH CHCTRL31 60H CONFUCC 61H UCCMFR 62H UCCFRS 63H WRUCC 64H DORAM 65H IMASKFRS 66H IMASKFRN 67H DIRAM 68H UCCOLD 69H UCCNEW 6AH UCCSTAT 6BH SCMASK 6CH CONFFLEX SCTR 6DH ...

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Addr Short Name . 74H AVDHG 75H AVDCI 76H VDFCTRL 77H ATMAT 78H AACSC 79H ACONF 7AH AFCMC 7BH AFCD1 7CH AFCD2 7DH AFCD3 Data Sheet Full name AFI Voice Detection, Hysteresis and Gap AFI Voice Detection Count Init Voice ...

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Read-Write-Register NOTEBOOK[7:0] (Addr.: 00H): Notebook, write protected, Reset value = 00H NOTE NOTE NOTE BOOK[7] BOOK[6] BOOK[5] NOTEBOOK[7:0] Read/Write register for testing of the P interface, content without effect, write protected UPIO[7:0] (Addr.: 05H): P-I/O-Pin extension, Reset value = ...

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RESULT is valid, if the RAMBIST was activated before CUFAIL '1': RAMBIST of central unit failed, i.e. a RAM error was detected '0': RAMBIST of central unit succesful: no error in RAM AFI3FAIL '1': RAMBIST of adaptive filter ...

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WP[7:0] (Addr.: 01H) Write Protection, Reset Value 'protected'= NOT 95H WP[7] WP[6] WP[5] WP[7:0] Write access to the write protected configuration registers is released by writing the value 95H to this register. The write protection is activated by writing any ...

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WDG2[7:0] (Addr.: 03H) Watchdog 2 WDG2[7] WDG2[6] WDG2[5] WDG2[4] WDG2[3] WDG2[2] WDG2[1] WDG2[0] WDG2[7:0] For watchdog test: Must be written with the defined value 99H as the second of the three watchdog registers within 2 seconds WDG3[7:0] (Addr.: 04H) Watchdog ...

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Attenuation of send path output is disabled for all channels SOATTMOD '1': Attenuation of send path output is 2 enabled '0': Attenuation of send path output enabled ROATTEN '1': Attenuation of ...

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CHIND = '0' and CONVDIS = '0' '0': -Law PCM encoding at far end side (RI and SO) if CHIND = '0' and CONVDIS = '0' *Note: In the case of no A-/ -Law conversion (same law at near ...

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Possible PCM Law conversion is enabled if Bit ENPCTRL = '1', Law conversion on/off depends on other hardware sources (serial control signals, UCC) if ENPCTRL = '0'. FREEZE '1': The H-register of the corresponding channel are ...

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SCMASK[5:0] (Addr.: 6BH): Serial Control Interface Mask, write protected, Reset value = 3FH - - MASK This register is for masking of external pins of the Serial Interface. The effect of this register depends also on the value of CHCTRL0..31.ENPCTRL. ...

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No reset of the attenuation meters unit by FLEXSCTR FSHRESET '1': serial control signal at pin FLEXSCTR resets the H-Register '0': No reset of the H-Register by FLEXSCTR FSCONVDIS '1': serial control signal at pin FLEXSCTR disables the PCM-Law ...

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The bits CONFFLEXMON1[3:0] and CONFFLEXMON2[3:0] configure the serial control signals FLEXMON1 and FLEXMON2, respectively. CONFFLEXMON1[3:0] / CONFFLEXMON2[3:0] Configuration of the flexible monitor output signal at pin FLEXMON1/ FLEXMON2 "0000": "0001": "0010": "0011": "0100": "0101": "0110": "0111": "1000": "1001": "1010": "1011": ...

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CONFIDLE[5:0] (Addr.: 32H): Configuration of IDLE Detection, write protected, Reset value = 1DH - - ENIDLE For idle detection the Receive In or Send In input pattern is compared either with itself or with a maskable configurable pattern of ...

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IDLEMASK [7:0] '1': The corresponding bit is ignored for pattern comparison '0': normal operation (bit comparison enabled) IDLEPATTERN[7:0] (Addr.: 34H): Idlepattern, write protected, Reset value = 55H IDLE IDLE IDLE PAT PAT PAT TERN[7] TERN[6] TERN[5] The reset value corresponds ...

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RLISTEN This bit is only active in Reflect Mode which can be configured via bit CONFUCC.RSWCTRL or SMLP bit of UCC Interface. '1': UCCI input data will be transferred to IRAM and interrupt will be generated '0': Normal operation: No ...

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Note: In 128 ms mode the DIS-Bit and the FX-Bit are only evaluated in the 16 processed channels. UCCMFR[4:0] (Addr.: 61H): UCC Multiframe Alignment, write protected, Reset value = ...

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UCCO and the activation of TUCCO for all frames in 128 ms mode if the number does not correspond to one of the 16 processed channels.* UCCFRS[4:0] Denotes the frame number of ...

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IMASKFRN[7:0] (Addr.: 66H): Interrupt Mask for channel individual UCC frames (FRN), Reset value = 00H IMASK IMASK IMASK FRN[7] FRN[6] FRN[5] IMASKFRN[7:0] Each activated (set to '1') mask bit prevents the generation of an UCC interrupt at a change of ...

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TESTTIMER.UPTEST. If the channel that is background tested by the software suddenly becomes enabled by external sources before the test is terminated an interrupt is generated that informs the software to abort ...

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SGMOD1 operation mode1 for signal generator (see SPTP [6:0] Send path test pattern amplitude, log, A-/µ-Law encoded TSGRPP[7:0] (Addr.: 3AH): Test signal generator for receive path pattern, Reset value = 55H SG RP MOD0 TP[6] TP[5] SGMOD0 operation mode 0 ...

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The timer can be used by the processor, if the processor wants to do different operations inbetween. The timer is counting downward. The timing decrement is 1 ms. The accuracy of the timer is +0 ... 1 ms. The maximum ...

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BYPTHL[4:0] Transhybrid loss as of which the canceling unit is bypassed "00000": "00001": "00010": "00011": "00100": "10010": "11111": READD[1:0] Safety distance for SO > residual echo + READD comparison "00" DHHLEC '1':Enables detection of a change in end ...

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CONFSCU4[7:0] (Addr.: 15H): Configuration of speech control unit 4, write protected, Reset value = A7H OC OC INC[1] INC[0] DEC[1] Overcompensation: OCINC[1:0] Increment period for overcompensation evaluation "00" OCDEC[1:0] Decrement period for overcompensation evaluation "00" SIADD[1:0] ...

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CONFSCU6[7:0] (Addr.: 17H): Configuration of speech control unit 6, write protected, Reset value = 2AH REL REL REL ADD[2] ADD[1] ADD[0] RELADD[2:0] Safety increment for the residual echo limiter threshold "000" "100" "101" "110": ...

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CONFSCU8[7:0] (Addr.: 19H), Configuration of speech control unit 8, write protected, Reset value = EEH BNMAX BNMAX BNMAX SL[3] SL[2] SL[1] BNMAXSL[3:0] Maximum send path level for background noise measurement "0000": "0001": "0010": "0011": "0100": ... "1110": "1111": BNMAXRL[3:0] Maximum ...

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Coefficient (H-Register) reset: DISHRES '0': no reset via 2100 Hz Disabler without phase shift '1': reset via 2100 Hz Disabler even without phase shift PSHRES '0': no reset via 2100 Hz Disabler even with phase shift '1': reset via 2100 ...

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VDFCTRL[7:0] (Addr.: 76H): Voice Detection Freeze Control, write protected, Reset value = B4H VDF VDF VDF RELEN REL[2] REL[1] VDFRELEN '0': No freeze of H-Register on no voice detection when combined loss (ERL+ERLE) > VDFREL '1':Freeze of H-Register on no ...

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DBPMAX[2:0] Maximum interruption time that results in response: "000" "010" "100" "110" DBPMIN[1:0] and DBPMAX[2:0] determine the evaluation window. CONFSS7[7:0] (Addr.: 1DH): Configuration of SS7 continuity ...

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CONFCC[6:0] (Addr.: 0BH) Configuration of Clock Control unit, write protected, Reset value = 00H - INV SYNC CTRL32 ACT INVCTRL32 '1': Inverts the control voltage signal for the 32MHz VCO at pin CTRL32 (see '0': no inversion of the control ...

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FSLIPIV[4:0] Determines the safety interval around the SYNCO pulse, which represents the minimum allowed distance between SYNCO and RFSPN or RFSPF steps. If the distance between RFSPN/F and SYNCO becomes smaller than FSLIPIV[4: SYNCO ...

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UCCALIGN[7:0] (Addr.: 10H): UCC frame alignment,write protected, Reset value = 00H UCC UCC UCC ALIGN[7] ALIGN[6] ALIGN[5] UCCALIGN[7:0] Determines the valid frame bit of the UCC frame (starting with bit 7 channel 0) at the first falling SCLKI edge, with ...

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STFALL[2:0] Saw-tooth falling clock frequency The clock for the increasing a decreasing saw tooth offset voltage is: "000": 4 kHz "010": 1 kHz "100": 250 Hz "110": 62 STRISE[2:0] and STFALL[2:0] are set to "000", the clock will ...

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SIDEC ASICs has to be used in which a single SIDEC chip processes only every other four channels: Master: Slave: If the 128 ms mode is not selected (pins MODE0 and ...

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AVDHG[7:0] (Addr.: 74H): AFI Voice Detection, Hysteresis and Gap, write protected, Reset value = 74H VDSO VDSO VDSO DELAY DELAY DELAY [3] ...

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AVDCI[7:0] (Addr.: 75H): AFI Voice Detection Count Init, write protected, Reset value = 85H VDCI VDCI VDCI [7] [6] VDCI[7:0] Voice Detection Counter Init value: A counter is used to count the number of values within the VDINTERVAL which fulfill ...

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ACSEFFECT ACSEFFECT specifies the effect of slow-down mode. If set to '1', coefficient update is limited to increasing/decreasing by at most 1. If set to '0', coefficient increment/decrement takes place in the normal way of operation, but turbo mode is ...

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It is configured in the range from -42 dBm0 (VDAT[3:0] = "0001" dBm0 (VDAT[3:0] = "1111") in steps of 3 dBm0. With VDAT set to the default value "0000", no lower limit ...

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Read Register CLKSTAT[5:0] (Addr.: 09H): Clock-Status - - CLKEX RFCLKEX '1': no valid 2 MHz clock available at pin RFCLKEX RFCLKN '1': no valid 2 MHz clock available at pin RFCLKN RFCLKF '1': no valid 2 MHz clock available ...

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UCCPOLL '1': UCC status TSMPOLL '1': Timeslot monitor status SFATSES[2:0] (Addr.: 36H): Super frame alarm and requested timeslot en/disable status - - TSENVALID '1': TSEN value for the requested TS in register ATE is valid '0': TSEN value not valid ...

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H-Register not reset ERL '1': echo return loss > value of BYPTHL[4:0] '0': echo return loss not > value of BYPTHL[4:0] FCM '1': fast convergence mode '0': normal convergence mode NOSPEECH '1': no speech detected '0': speech detected DIRAM[7:0] ...

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NOSYNC '1': UCC unit is not synchronized to SYNCI pulse, i.e. the SYNCI pulse period is not an integer multiple of 32 UCC frames (4ms). '0': UCC unit is synchronized to SYNCI pulse, i.e. a SYNC ...

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Table 37 AFI Coefficients to Absolute Linear Value Conversion ...

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The content of this register is PCM encoded MONSIL[7:0] (Addr.: 1EH): Monitor send input level MON MON MON SIL[7] SIL[6] SIL[5] The content of this register is encoded logarithmically. The maximum value of 191 corresponds to 3 dBm0. A decrease ...

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MONRIL[7:0] (Addr.: 20H): Monitor of receive input level MON MON MON RIL[7] RIL[6] RIL[5] The content of this register is encoded logarithmically. For conversion to dBm0 see Table 38 . MONOFSI[5:0] (Addr.: 21H): Monitor offset in send path input - ...

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MONERL[7:0] (Addr.: 25H): Monitor Echo return loss MON MON MON ERL[7] ERL[6] ERL[5] The content of this register is encoded logarithmically. For conversion to dB see Table 38 . MONCL[7:0] (Addr.: 26H): Monitor combined loss without NLP MON MON MON ...

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MNS '1': "no-voice" detected MDISNOSP '1': 2100Hz detected but without speech protection MDIS '1': 2100Hz detected with speech protection MDISPS '1': 2100Hz with phase shift and speech protection detected MHRES '1': H-Register reset MFREEZE '1': H-Register frozen MNLP '1': NLP ...

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MSCCONVDIS '1': serial control signal CONVDIS active MFLEXSCTR '1': serial control signal FLEXSCTR active Data Sheet Register Description 127 PEB 20954 PEF 20954 Rev. 2, 2004-07-28 ...

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Electrical Characteristics 6.1 Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature IC supply voltage Voltage on any functional pin (not V not ) with respect to ground SS 1) ESD robustness HBM: 1 100 pF ...

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DC Characteristics Parameter Input low voltage Input high voltage Output low voltage Output high voltage Avg. power supply current Input leakage current Output leakage current 1) Permanent exposure to negative input voltages may result in minor degradation of lifetime ...

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AC Characteristics Parameter Input low voltage Input high voltage Output low voltage Output high voltage 1) Permanent exposure to negative input voltages may result in minor degradation of lifetime 2) Apply to the following O or I/O pins: UPIO0, ...

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Capacitances Parameter Clock input capacitance Clock output capacitance Input capacitance Output capacitance Data Sheet Symbol Limit Values min. max XIN C 10 XOUT OUT 131 PEB 20954 PEF 20954 Electrical Characteristics Unit ...

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Timing Diagrams Note: All timing parameters are no subject to production tests. These parameters are verified by design/characterization only. 6.6.1 Clock Timing CLK32 1 SDECI SCLKO if CLK32SEL='1' CLK16 6 SCLKO if CLK32SEL='0' SCLKI 7 CLK4O Figure 30 Clock ...

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Table 39 Clock Timing Characteristics (preliminary) (cont’d) No. Name 6 t_sclko_delay_clk16 SCLKO output delay 7 t_clk4o_delay Table 40 Periods of Clock Signals No. Parameter CLK32 CLK16 SCLKI CLK4O 6.6.2 PCM Signal Timing and Frame Alignment The SIDEC requires the MSB ...

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SCLKI SYNCI (SYNCO) channel 26 RI Bit 2 Bit 1 Bit 0 SI Bit 0 Bit 7 channel 26 RO Bit 2 Bit 1 Bit 0 channel 2 SO Bit 3 Bit 2 SCLKI SYNCI (SYNCO) sampling ...

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RIALIGN, SIALIGN an SOALIGN. For finer adjustments, the valid bit phase of the PCM signals at the first detection of an active SYNCI with the falling edge of SCLKI can be configured by writing to the register PHALIGN. The ...

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Table 41 PCM Signal Timing and Frame Characteristics (preliminary) No. 1 t_pcm_setup 2 t_pcm_hold 3 t_pcm_delay 4 t_pcm_ri2ro_delay 5 t_pcm_si2so_delay delay for bybass t_pcm_ri2so_delay 7 t_pcm_si2ro_delay Data Sheet Parameter min. PCM input (RI,SI) 15 input setup time ...

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Timing of SYNCI and SYNCO SYNCI is clocked in with the falling edge and SYNCO is clocked out with the rising edge of SCLKI, SYNCI and SYNCO are active low (CONFCC.SSCLKEDGE = '0' and CONFCC.SYNCACT = '0') SCLKI SYNCI ...

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Table 42 Characteristics of Timing of SYNCI and SYNCO (preliminary) No. Name 1 t_synci_setup 2 t_synci_hold 3 t_synco_delay Data Sheet Parameter min. SYNCI setup time 10 before active sampling edge of SCLKI SYNCI hold time after 10 active sampling edge ...

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Clock Timing within External VCO Capture Range SCLKI Lock-in at 0° CLK32 internal 8Mhz clock CTRL32 Lock-in at 90° CLK32 internal 8Mhz clock CTRL32 Lock-in at 180° CLK32 internal 8Mhz clock CTRL32 Figure 35 Clock Timing within External VCO ...

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Serial Interface (Controlling and Monitoring) Timing CLK32 SCLKO SDECO 6 serial control inputs serial monitor channel 30 outputs CLK32 SCLKO SDECO serial control inputs serial monitor outputs Figure 36 Serial Interface (Controlling and Monitoring) Timing Table 43 Serial Interface ...

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Table 43 Serial Interface (Controlling and Monitoring) Timing (preliminary) No. Name 4 t_smon_delay 5 Data Sheet Parameter min. Serial monitor signal 0 output delay after CLK32Y SDECO duration 16 * CLK32 period 141 PEB 20954 PEF 20954 Electrical Characteristics Limit ...

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UCC Interface Signal Timing and Frame Alignment SCLKI SYNCI (SYNCO) UCCI ...

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UCCMFR. For finer adjustments, the valid bit phase of the UCC signals at the first detection of an active SYNCI with the falling edge of SCLKI can be configured by writing to the two MSBs of register PHALIGN. The ...

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Special Cases for Multiframe Alignment Case 1: SYNCI at channel 31, bit 0, phase 3 SCLKI SYNCI (SYNCO) UCCI/UCCO Phase 1 Bit 0, channel 31, frame 3 Case 2: SYNCI at channel 0, bit 7, phase 0 SCLKI SYNCI (SYNCO) ...

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Table 44 UCC Interface Signal Timing and Frame Alignment (preliminary) No. Name 1 t_ucci_setup 2 t_ucci_hold 3 t_ucco_delay 4 t_tucco_delay 5 t_ucc_reflect_delay Propagation delay Data Sheet Parameter min. UCCI input setup time 15 before sampling with SCLKIZ UCCI input hold ...

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Speech Highway Control Signals for CAS in T1 Systems Frame 1 SI TMFBI Transmit Multiframe Begin; indication bit 7 channel 0 SYNCI System Synchronisation Input Pulse Using FALC in channel translation mode TSIGM marks robbed ...

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Microprocessor Interface Internal Read Internal Read Condition: SIEMENS/Intel Mode (IM0 = '0'):(CS0 = '0' or CS1 = '0') and RD/DS = '0' Motorola Mode (IM0 = '1'): Internal Write Internal Read Condition: SIEMENS/Intel Mode (IM0 = '0'):(CS0 = '0' ...

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Intel Mode (IM0='0') a) Multiplexed Mode (IM1='0') ALE 1 AD[7: RDY Figure 41 Read Timing in Multiplexed Intel Mode (IM0='0', IM1='0') ALE 1 AD[7: RDY Figure 42 Write Timing in Multiplexed Intel Mode (IM0='0', IM1='0') ...

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Demultiplexed Mode (IM1='1') 16a Figure 43 Read Timing in Demultiplexed Intel Mode (IM0='0', IM1='1') A[5: AD[7:0] RDY Figure 44 Write Timing in Demultiplexed Intel Mode (IM0='0', IM1='1') Data Sheet 17a 17b 5a 4a 16b ...

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Motorola Mode (IM0='1') a) Multiplexed Mode (IM1='0') ALE 1 AD[7: RDY Figure 45 Read Timing in Multiplexed Motorola Mode (IM0='1', IM1='0') 1 Figure 46 Write Timing in Multiplexed Motorola Mode (IM0='1', IM1='0') Data Sheet 2 22a ...

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Demultiplexed Mode (IM1='1') A[5: AD[7:0] RW RDY Figure 47 Read Timing in Demultiplexed Motorola Mode (IM0='1', IM1='1') A[5: AD[7:0] RW RDY Figure 48 Write Timing in Demultiplexed Motorola Mode (IM0='1', IM1='1') Data Sheet 33a 33b ...

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Table 46 Prliminary Microprocessor Interface Timing Values No. Parameter 1 Address setup before ALE falling edge 2 Address hold after ALE falling edge 3a ALE falling edge before CS active if RD asserted 3b ALE falling edge before RD active ...

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Table 46 Prliminary Microprocessor Interface Timing Values (cont’d) No. Parameter 12a Write data setup before CS rising edge if WR asserted 12b Write data setup before WR rising edge if CS asserted 13a Write data hold after CS rising edge ...

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Table 46 Prliminary Microprocessor Interface Timing Values (cont’d) No. Parameter 20b ALE falling edge before DS active if CS asserted and RW = '1’ 21a RW setup before CS active if DS asserted 21b RW setup before DS active if ...

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Table 46 Prliminary Microprocessor Interface Timing Values (cont’d) No. Parameter 29b Write data setup before DS rising edge if CS asserted and RW = '0' 30a Write data hold after CS rising edge if DS asserted and RW = '0' ...

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JTAG Timing TCK TMS TDI TDO Figure 49 JTAG Boundary Scan Timing Table 47 JTAG Boundary Scan Timing No. Name 1 t_tck_period 2 t_tck_high 3 t_tck_low 4 t_tms_setup 5 t_tms_hold 6 t_tdi_setup 7 t_tdi_hold 8 t_tck_tdo_fall Data Sheet 1 ...

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Package Outlines TQFP-144 (144pin Thin Plastic Quad Flatpack Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet 157 PEB 20954 PEF 20954 Package Outlines ...

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P-LFBGA-160-2 (Plastic Metric Quad Flat Package) You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. SMD = Surface Mounted Device Data Sheet 158 PEB 20954 PEF 20954 Package Outlines GPM05249 ...

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Glossary acoustic echo Acoustic echoes consist of reflected signals caused by acoustic environments, e.g. hands-free phones which are connected with a 2-wire circuit to a hybrid. An echo path is introduced by the acoustic path from earphone to microphone. ...

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Network Elements Near-end Hybrid Network Elements Figure 50 Location of levels and loss of an echo canceller echo path The transmission path between R to describe the signal path of the echo. echo path capacity The maximum echo path ...

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The attenuation of the echo signal as it passes through the send path of an echo canceller. This definition specifically excludes any non-linear processing on the output of the canceller to provide for further ...

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NOTE 2 – An example of a NLP is an analogue center clipper in which all signal levels below a defined threshold are forced to some minimum value. non-linear processing loss (A Additional attenuation of residual echo level by a ...

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L is related to L by: RET Rin RET RIN ECHO If non-linear processing is not present, note that L Data Sheet + A ) CANC NLP RES 163 PEB 20954 PEF ...

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... Published by Infineon Technologies AG ...

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