SLXT973QC Cortina Systems Inc, SLXT973QC Datasheet - Page 10

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SLXT973QC

Manufacturer Part Number
SLXT973QC
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of SLXT973QC

Lead Free Status / Rohs Status
Not Compliant

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LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
Cortina Systems
Added
Added
Changed PECL to LVPECL in first paragraph, second sentence under
Modified table note 2 in
Modified table note 2 in
all pins except SD, MII...”.
Added
In
Changed "Peak differential output voltage (single ended)" to "Peak-to-peak differential output voltage".
Changed "VOP" to "V
Modified
Figure 1 “LXT973 Block
Added note to diagram.
Under
Removed Table 10: 4B/5B Coding.
Section 3.10.1, “Monitoring
Under
Removed Table 16: 4B/5B Coding.
Section 12.0, “Register Definitions”
Removed “multiple 11-bit registers, with” from first sentence.
Table 20 “PHY Identification Register 2 (Address
Changed default for Register bits 3.9:4 from “001110” to “100001”.
Table 29 “Absolute Maximum Ratings”
Added three table notes.
Table 31 “Digital Input/Output
Table 32 “Digital Input/Output Characteristics - MII Pins”
Removed “Driver Output Impedance.”
Table 34 “LED Pin Characteristics”
Added MAX value to Output High Current.
Table 35 “100BASE-TX Transceiver Characteristics”
Added Typ values.
Table 36 “10BASE-T Transceiver Characteristics”
Added/replaced Typ values.
Removed “Receiver Input Impedance.”
Table 37 “100BASE-FX Transceiver Characteristics”
Added Typ values
Table 38 “10BASE-T Link Integrity Timing Characteristics”
Added Typ value for Link Pulse Width
Added
Modified
Table 46 “100BASE-TX Transceiver
Section 3.8.4, “PMA
Section 8.1, “Displaying Symbol
Figure 15 “Recommended LXT973-to-5 VFiber Transceiver Interface
Figure 16 “ON Semiconductor* Triple PECL-to-LVPECL Logic
Table 42 “Digital Input/Output Characteristics - SD
Table 39 “Twisted-Pair
Table 63 “Product Ordering
Table 40 on page 77
®
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
diffp-p
Table 41 “Digital Input/Output Characteristics2”
Table 29 “Port Configuration Register (Address 16)”
Diagram”:
", and removed footnote #2 (and all references).
Sublayer”:
Auto-Negotiation”: Removed paragraphs 3 and 4, and Figure 11.
Characteristics2”Modified table note 2.
Pins”.
through
Information”.
Table 49 on page
Characteristics”:
Modified Power Supply: added V
Errors”:
Revision Date: 20 January 2004
3)”:
Revision Date: June 2002
Revision Number: 003
Revision Number: 002
85.
Pins”.
Translator”.
Section 9.0, “Fiber
– (changed “applies to all pins except MII...” to “applies to
CC
A, V
(changed ”hardware pins” to “FIBER_TPn”.
Circuitry”.
CC
, VCCPECL, VCCIO information.
Interface”.
Revision History
Page 10

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