SLXT973QC Cortina Systems Inc, SLXT973QC Datasheet - Page 44

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SLXT973QC

Manufacturer Part Number
SLXT973QC
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of SLXT973QC

Lead Free Status / Rohs Status
Not Compliant

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LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
4.1.5
Cortina Systems
The Fiber Interface
The fiber interface consists of an LVPECL transmit and receive pair to an external fiber-
optic transceiver. Both 3.3 V fiber-optic transceivers and 5 V fiber-optic transceivers can
be used with the LXT973 Transceiver. See the 100BASE-FX Fiber Optic Transceivers-
Connecting a PECL/LVPECL Interface Application Note (document number 250781) for
detailed information on fiber interface designs and recommendations for Cortina PHYs.
The following should occur in 3.3 V fiber transceiver applications as shown in
Refer to the fiber transceiver manufacturers’ recommendations for termination circuitry.
Figure 14, Recommended LXT973 Transceiver Transceiver-to-3.3 V Fiber Transceiver
Interface Circuitry, on page 48
3.3 V fiber transceiver interface.
The following occurs in 5 V fiber transceiver applications as shown in
Recommended LXT973 Transceiver-to-5 V Fiber Transceiver Interface Circuitry, on
page
Refer to the fiber transceiver manufacturers’ recommendations for termination circuitry.
Figure 15
interface, while
®
• The transmit pair should be AC-coupled with 2.5 V supplies and re-biased to
• The transmit pair should contain a balance offset in the pull-up resistors to prevent
• The receive pair should be DC-coupled with an emitter current path for the fiber
• The signal detect pin should be DC-coupled with an emitter current path for the fiber
• The transmit pair should be AC-coupled and re-biased to 5 V PECL input levels
• The transmit pair should contain a balance offset in the pull-up resistors to prevent
• The receive pair should be AC-coupled with an emitter current path for the fiber
• The signal detect pin on a 5 V fiber transceiver interface should use the logic
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
3.3 VLVPECL levels
PHY-to-fiber transceiver crosstalk amplification in power-down, loopback, and reset
states (see fiber interface application note)
transceiver
transceiver
PHY-to-fiber transceiver crosstalk amplification in power-down, loopback, and reset
states (see fiber interface application note)
transceiver and re-biased to 1.2 V
translator circuitry as shown in
LVPECL Logic Translator, on page
49:
shows a typical example of an LXT973 Transceiver-to-5 V fiber transceiver
Figure 16
shows the interface circuitry for the logic translator.
shows a typical example of an LXT973 Transceiver-to-
Figure 16, ON Semiconductor* Triple PECL-to-
50.
4.1 Design Recommendations
Figure 15,
Figure
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14:

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