SC16C554DBIA68,529 NXP Semiconductors, SC16C554DBIA68,529 Datasheet
SC16C554DBIA68,529
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SC16C554DBIA68-S
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SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Rev. 4 — 8 June 2010 1. General description The SC16C554B/554DB is a 4-channel Universal Asynchronous Receiver and Transmitter (QUART) used for serial data ...
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... NXP Semiconductors Automatic hardware flow control (RTS/CTS) Software selectable baud rate generator Four selectable Receive FIFO interrupt trigger levels Standard modem interface Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break) Transmit, Receive, Line Status, and Data Set interrupts independently controlled ...
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... NXP Semiconductors 4. Block diagram SC16C554B/554DB DATA BUS IOR AND IOW CONTROL RESET LOGIC REGISTER SELECT CSA to CSD LOGIC 16/68 INTA to INTD TXRDY RXRDY INTERRUPT CONTROL LOGIC INTSEL Fig 1. Block diagram of SC16C554B/554DB (16 mode) SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs ...
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... NXP Semiconductors SC16C554B/554DB DATA BUS AND R/W CONTROL RESET LOGIC REGISTER SELECT CS LOGIC 16/68 IRQ INTERRUPT TXRDY CONTROL RXRDY LOGIC Fig 2. Block diagram of SC16C554B/554DB (68 mode) SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs TRANSMIT ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 5.1.1 PLCC68 Fig 3. SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs DSRA 10 11 CTSA 12 DTRA RTSA 14 INTA 15 16 CSA 17 TXA SC16C554DBIA68 IOW 18 TXB 19 CSB 20 21 INTB 22 RTSB GND ...
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... NXP Semiconductors Fig 4. SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 10 DSRA 11 CTSA DTRA RTSA 14 15 IRQ 16 CS TXA 17 SC16C554DBIA68 R/W 18 TXB n.c. RTSB 22 GND 23 DTRB 24 25 CTSB 26 DSRB Pin configuration for PLCC68 (68 mode) All information provided in this document is subject to legal disclaimers. Rev. 4 — ...
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... NXP Semiconductors 5.1.2 LQFP64 Fig 5. SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs DSRA 1 CTSA 2 3 DTRA RTSA 5 INTA 6 CSA 7 SC16C554BIB64 8 TXA SC16C554DBIB64 9 IOW SC16C554BIBM TXB 10 CSB 11 INTB 12 13 RTSB 14 GND DTRB 15 CTSB 16 Pin configuration for LQFP64 All information provided in this document is subject to legal disclaimers. Rev. 4 — ...
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... NXP Semiconductors 5.1.3 LQFP80 INTSEL Fig 6. SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs n.c. 1 CDD 2 RID 3 4 RXD n. GND 16 RXA 17 RIA 18 19 CDA 20 n.c. Pin configuration for LQFP80 All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 5.1.4 HVQFN48 Fig 7. Fig 8. SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs terminal 1 index area CTSA RTSA INTA 4 CSA 5 TXA 6 SC16C554BIBS 7 IOW 8 TXB CSB 9 INTB 10 RTSB 11 12 CTSB Transparent top view Pin configuration for HVQFN (16 mode) ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin PLCC68 LQFP64 LQFP80 HVQFN48 16/ CDA 9 64 CDB 27 18 CDC 43 31 CDD CSA 16 7 CSB 20 11 CSC 50 38 CSD 54 42 SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin PLCC68 LQFP64 LQFP80 HVQFN48 CTSA 11 2 CTSB 25 16 CTSC 45 33 CTSD DSRA 10 1 DSRB 26 17 DSRC 44 32 DSRD 60 48 DTRA 12 3 DTRB 24 15 DTRC 46 34 DTRD 58 46 GND 6, 23, 14, 28, 40, 57 45, 61 INTA ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin PLCC68 LQFP64 LQFP80 HVQFN48 INTSEL 65 - IOR 52 40 IOW 18 9 IRQ 15 - n.c. 21, 49, - 52, 54, 55, 65 SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Type Description Interrupt Select (active HIGH, with internal pull-down) ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin PLCC68 LQFP64 LQFP80 HVQFN48 RESET 37 27 (RESET) RIA 8 63 RIB 28 19 RIC 42 30 RID 62 50 RTSA 14 5 RTSB 22 13 RTSC 48 36 RTSD RXA 7 62 RXB 29 20 RXC 41 29 RXD 63 51 RXRDY 38 - SC16C554B_554DB Product data sheet ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin PLCC68 LQFP64 LQFP80 HVQFN48 TXA 17 8 TXB 19 10 TXC 51 39 TXD 53 41 TXRDY 13, 30, 4, 21, CC 47, 64 35, 52 XTAL1 35 25 XTAL2 36 26 [1] HVQFN48 package die supply ground is connected to both GND pins and exposed center pad. GND pins must be connected to supply ground for proper device operation ...
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... NXP Semiconductors 6. Functional description The SC16C554B/554DB provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character ...
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... NXP Semiconductors 6.1 Interface options Two user interface modes are selectable for the PLCC68 package. These interface modes are designated as the ‘16 mode’ and the ‘68 mode’. This nomenclature corresponds to the early 16C454/554 and 68C454/554 package interfaces respectively. 6.1.1 The 16 mode interface ...
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... NXP Semiconductors 6.2 Internal registers The SC16C554B/554DB provides 12 internal registers for monitoring and control. These registers are shown in (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO Control Register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user accessible Scratchpad Register (SPR) ...
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... NXP Semiconductors 6.4 Autoflow control (see Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has space for the data ...
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... NXP Semiconductors Remark: Auto-CTS is not supported in channel D of the HVQFN48 package, therefore MCR[5] of channel D should not be written. 6.4.3 Enabling autoflow control and auto-CTS Autoflow control is enabled by setting MCR[5] and MCR[1]. Table 7. MCR[ 6.4.4 Auto-CTS and auto-RTS functional timing Start bits CTS (1) When CTS is LOW, the transmitter keeps sending serial data out ...
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... NXP Semiconductors RX byte 14 RTS IOR (1) RTS is de-asserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the sixteenth byte. (2) RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing, or there is more than one byte of space available ...
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... NXP Semiconductors A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel control. The programmable Baud Rate Generator is capable of accepting an input clock MHz (for 3.3 V and 5 V operation), as required for supporting a 5 Mbit/s data rate. The SC16C554B/554DB can be configured for internal or external clock operation ...
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... NXP Semiconductors 6.7 DMA operation The SC16C554B/554DB FIFO trigger level provides additional flexibility to the user for block mode operation. LSR[6:5] provide an indication when the transmitter is empty or has an empty location(s). The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA mode is de-activated (DMA Mode 0), the SC16C554B/554DB activates the interrupt output pin for each data transmit or receive operation ...
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... NXP Semiconductors SC16C554B/554DB DATA BUS IOR AND IOW CONTROL RESET LOGIC REGISTER SELECT CSA to CSD LOGIC INTA to INTD INTERRUPT TXRDY CONTROL RXRDY LOGIC Fig 14. Internal Loopback mode diagram (16 mode) SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs ...
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... NXP Semiconductors SC16C554B/554DB (HVQFN48 DATA BUS IOR AND IOW CONTROL RESET LOGIC REGISTER SELECT CSA to CSD LOGIC INTERRUPT INTA to INTD CONTROL LOGIC Fig 15. Internal Loopback mode diagram (16 mode) for HVQFN48 package SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs ...
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... NXP Semiconductors SC16C554B/554DB DATA BUS R/W AND RESET CONTROL LOGIC REGISTER SELECT CS LOGIC 16/68 IRQ INTERRUPT TXRDY CONTROL RXRDY LOGIC Fig 16. Internal Loopback mode diagram (68 mode) SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs ...
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... NXP Semiconductors SC16C554B/554DB (HVQFN48 DATA BUS R/W AND RESET CONTROL LOGIC REGISTER SELECT CS LOGIC 16/68 INTERRUPT IRQ CONTROL LOGIC Fig 17. Internal Loopback mode diagram (68 mode) for HVQFN48 package SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs ...
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... NXP Semiconductors 7. Register descriptions Table 9 The assigned bit functions are more fully defined in Table 9. SC16C554B/554DB internal registers Register Default [2] General Register set RHR THR IER FCR ISR LCR MCR LSR MSR SPR FF [5] Special Register set DLL DLM XX [1] The value shown represents the register’s initialized hexadecimal value not applicable. ...
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... NXP Semiconductors 7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR) The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the THR, providing that the THR or TSR is empty ...
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... NXP Semiconductors 7.2.1 IER versus Receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: • The receive data available interrupts are issued to the external CPU when the FIFO has reached the programmed trigger level ...
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... NXP Semiconductors 7.3.2 FIFO mode Table 11. Bit 7:6 5 SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs FIFO Control Register bits description Symbol Description FCR[7:6] RCVR trigger. These bits are used to set the trigger level for the receive FIFO interrupt ...
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... NXP Semiconductors Table 12. FCR[ 7.4 Interrupt Status Register (ISR) The SC16C554B/554DB provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... NXP Semiconductors 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 15. Bit 1:0 SC16C554B_554DB Product data sheet ...
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... NXP Semiconductors Table 16. LCR[ Table 17. LCR[ Table 18. LCR[ SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs LCR[5] parity selection LCR[4] LCR[3] Parity selection parity 0 1 odd parity 1 1 even parity 0 1 forced parity ‘1’ ...
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... NXP Semiconductors 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 19. Bit 7 SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Modem Control Register bits description Symbol ...
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... NXP Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C554B/554DB and the CPU. Table 20. Bit SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Line Status Register bits description ...
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... NXP Semiconductors 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C554B/554DB is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state ...
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... NXP Semiconductors 7.9 Scratchpad Register (SPR) The SC16C554B/554DB provides a temporary data register to store 8 bits of user information. 7.10 SC16C554B/554DB external reset conditions Table 22. Register IER ISR LCR MCR LSR MSR FCR Table 23. Output TXA, TXB, TXC, TXD RTSA, RTSB, RTSC, RTSD DTRA, DTRB, DTRC, DTRD ...
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... NXP Semiconductors 9. Static characteristics Table 25. Static characteristics − ° ° +85 C; tolerance of V amb Symbol Parameter V clock LOW-level input IL(clk) voltage V clock HIGH-level input IH(clk) voltage V LOW-level input voltage IL V HIGH-level input voltage IH V LOW-level output voltage OL V HIGH-level output voltage ...
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... NXP Semiconductors 10. Dynamic characteristics Table 26. Dynamic characteristics − ° ° +85 C; tolerance of V amb Symbol Parameter t pulse width HIGH WH t pulse width LOW WL f oscillator/clock frequency XTAL t address set-up time 6s t address hold time 6h t IOR delay from chip select 7d t IOR strobe width ...
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... NXP Semiconductors Table 26. Dynamic characteristics − ° ° +85 C; tolerance of V amb Symbol Parameter t delay from IOW to 27d set TXRDY t delay from start to reset 28d TXRDY t address set-up time 30s t chip select strobe width 30w t address hold time 30h t read cycle delay ...
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... NXP Semiconductors 30s CS t 32s R Fig 19. General write timing in 68 mode IOW Fig 20. General write timing in 16 mode SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs t t 30w 30h t 32h t t 33h 33s t 6h ...
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... NXP Semiconductors IOR Fig 21. General read timing in 16 mode IOW RTSA, RTSB, RTSC, RTSD DTRA, DTRB, DTRC, DTRD CDA, CDB, CDC, CDD CTSA, CTSB, CTSC, CTSD DSRA, DSRB, DSRC, DSRD INTA, INTB, INTC, INTD IOR RIA, RIB, RIC, RID Fig 22. Modem input/output timing ...
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... NXP Semiconductors external clock 1 -------------- - f = XTAL clk Fig 23. External clock timing RX INT IOR Fig 24. Receive timing SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs w(clk) start bit data bits ( data bits 6 data bits 7 data bits 16 baud rate clock All information provided in this document is subject to legal disclaimers ...
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... NXP Semiconductors RX RXRDY IOR Fig 25. Receive ready timing in non-FIFO mode RX RXRDY IOR Fig 26. Receive ready timing in FIFO mode SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs start bit data bits ( start bit data bits ( ...
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... NXP Semiconductors TX INT active IOW Fig 27. Transmit timing TX IOW active byte #1 t 27d TXRDY Fig 28. Transmit ready timing in non-FIFO mode SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs start bit data bits ( data bits ...
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... NXP Semiconductors TX IOW active byte #16 TXRDY Fig 29. Transmit ready timing in FIFO mode (DMA mode ‘1’) SC16C554B_554DB Product data sheet 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs start bit data bits ( data bits 6 data bits 7 data bits ...
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... NXP Semiconductors 11. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors LQFP80: plastic low profile quad flat package; 80 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.16 1.5 mm 1.6 0.25 0.04 1.3 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT315-1 136E15 Fig 31 ...
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... NXP Semiconductors LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT414-1 136E06 Fig 32 ...
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... NXP Semiconductors HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 0.85 mm terminal 1 index area terminal 1 48 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max 0.05 0. 0.2 0.00 0.15 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included ...
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... NXP Semiconductors PLCC68: plastic leaded chip carrier; 68 leads pin 1 index β DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. 4.57 0.53 mm 0.51 0.25 3.3 4.19 0.33 0.180 0.021 inches 0.02 0.01 0.13 0.165 0.013 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 35. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 13. Abbreviations Table 29. Acronym CMOS CPU DMA FIFO I/O ISDN LSB MSB PCB QUART TTL UART SC16C554B_554DB Product data sheet ...
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... Release date SC16C554B_554DB v.4 20100608 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 2 “Features and tolerant on input pins only”; added • ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.1.1 PLCC68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.1.2 LQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1.3 LQFP80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.4 HVQFN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Functional description . . . . . . . . . . . . . . . . . . 15 6.1 Interface options . . . . . . . . . . . . . . . . . . . . . . . 16 6.1.1 The 16 mode interface . . . . . . . . . . . . . . . . . . 16 6 ...