SC28L92A1B,557 NXP Semiconductors, SC28L92A1B,557 Datasheet
SC28L92A1B,557
Specifications of SC28L92A1B,557
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SC28L92A1B
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SC28L92A1B,557 Summary of contents
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... The bit 3 of the MR0A register allows the device to operate byte FIFO mode if strict compliance with the SC26C92 FIFO structure is required. The NXP Semiconductors SC28L92 Dual Universal Asynchronous Receiver/Transmitter (DUART single-chip CMOS-LSI communications device that provides two full-duplex asynchronous receiver/transmitter channels in a single package. It interfaces directly with microprocessors and may be used in a polled or interrupt driven system with modem and DMA interface ...
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... NXP Semiconductors 2. Features I Member of IMPACT family +85 C and 68xxx or 80xxx bus interface for all devices I Dual full-duplex independent asynchronous receiver/transmitters I 16 character FIFOs for each receiver and transmitter I Pin programming selects 68xxx or 80xxx bus interface I Programmable data format N 5 data to 8 data bits plus parity ...
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... NXP Semiconductors I On-chip crystal oscillator I Power-down mode I Receiver time-out mode I Single 3 power supply I Powers up to emulate SC26C92 3. Ordering information Table 1. Ordering information Type number Package Name SC28L92A1A PLCC44 SC28L92A1B QFP44 SC28L92A1BS HVQFN48 SC28L92_7 Product data sheet 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter 10 % ...
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... NXP Semiconductors 4. Block diagram SC28L92 (80xxx mode RDN WRN CEN RESET I/M open or connect to V for 80xxx CC INTRN X1/CLK X2 The data pins TxD and RxD are considered idle at the logic 1 (HIGH) level when inactive, or active when at the logic 0 (LOW) level. Comments about these levels when RS232 is referenced often refer to Mark and Space levels. Mark usually means inactive and Space means active ...
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... NXP Semiconductors SC28L92 (68xxx mode R/WN IACKN CEN RESETN I/M ground for 68xxx mode INTRN DACKN X1/CLK X2 The data pins TxD and RxD are considered idle at the logic 1 (HIGH) level when inactive, or active when at the logic 0 (LOW) level. Comments about these levels when RS232 is referenced often refer to Mark and Space levels. Mark usually means inactive and Space means active ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 3. Pin configuration for PLCC44; 80xxx mode Fig 4. Pin configuration for PLCC44; 68xxx mode SC28L92_7 Product data sheet 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter A3 7 IP0 8 9 WRN RDN 10 RxDB 11 SC28L92A1A I/M 12 (80xxx mode) ...
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... NXP Semiconductors Fig 5. Pin configuration for QFP44; 80xxx mode Fig 6. Pin configuration for QFP44; 68xxx mode SC28L92_7 Product data sheet 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter A3 1 IP0 2 3 WRN RDN 4 RxDB 5 SC28L92A1B 6 TxDB (80xxx mode) OP1 7 OP3 8 OP5 ...
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... NXP Semiconductors Fig 7. Pin configuration for HVQFN48; 80xxx mode Fig 8. Pin configuration for HVQFN48; 68xxx mode SC28L92_7 Product data sheet 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter terminal 1 index area A3 1 IP0 2 3 WRN RDN 4 RxDB 5 6 n.c. SC28L92A1BS 7 I/M ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description for 80xxx bus interface (Intel) Symbol Pin PLCC44 QFP44 HVQFN48 I CEN WRN RDN RESET INTRN X1/CLK RxDA RxDB SC28L92_7 Product data sheet 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter Type Description I Bus configuration: When HIGH or not connected configures the bus interface to the conditions shown in this table ...
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... NXP Semiconductors Table 2. Pin description for 80xxx bus interface (Intel) Symbol Pin PLCC44 QFP44 HVQFN48 TxDA TxDB OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 IP0 IP1 IP2 IP3 IP4 IP5 IP6 38 SC28L92_7 Product data sheet 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter … ...
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... NXP Semiconductors Table 2. Pin description for 80xxx bus interface (Intel) Symbol Pin PLCC44 QFP44 HVQFN48 GND 22 16 n. 13, 24, 25, 36, 37, 43 [1] HVQFN48 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region ...
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... NXP Semiconductors Table 3. Pin description for 68xxx bus interface (Motorola) Symbol Pin PLCC44 QFP44 HVQFN48 INTRN X1/CLK RxDA RxDB TxDA TxDB OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 IP0 IP1 IP2 SC28L92_7 Product data sheet 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter … ...
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... NXP Semiconductors Table 3. Pin description for 68xxx bus interface (Motorola) Symbol Pin PLCC44 QFP44 HVQFN48 IP3 IP4 IP5 38 GND 22 16 n. 13, 24, 25, 36, 37, 43 [1] HVQFN48 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply ground for proper device operation ...
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... NXP Semiconductors receivers, and counter/timer. When OP3 to OP7 are programmed as interrupts, their output buffers are changed to the open-drain active LOW configuration. The OP pins may be used for DMA and modem control as well (see 6.1.4 FIFO configuration Each receiver and transmitter has a 16 byte FIFO. These FIFOs may be configured to operate at a fi ...
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... NXP Semiconductors 6.2.2 Baud rate generator The baud rate generator operates from the oscillator or external clock input at the X1 input and is capable of generating 28 commonly used data communications baud rates ranging from 50 kBd to 38.4 kBd. Programming bit 0 of MR0 to a logic 1 gives additional baud rates of 57 ...
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... NXP Semiconductors counter/timer input clock n = -------------------------------------------------------------------------- 2 16 Often this division will result in a non-integer number; 26.3 for example. One may only program integer numbers to a digital divider. Therefore 26 (0x1A) would be chosen. If 26.7 were the result of the division, then 27 (0x1B) would be chosen. This gives a baud rate error of 0 ...
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... NXP Semiconductors Counter/Timer upper register. These commands have slight differences depending on the mode of operation. Please see the detail of the commands in registers”. 6.2.7 Time-out mode caution When operating in the special time-out mode possible to generate what appears false interrupt, i.e., an interrupt without a cause. This may result when a time-out interrupt occurs and then, before the interrupt is serviced, another character is received, i ...
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... NXP Semiconductors 6.2.10 Output port The output ports are controlled from six places: the OPCR, OPR, MR, Command, SOPR and ROPR registers. The OPCR register controls the source of the data for the output ports OP2 through OP7. The data source for output ports OP0 and OP1 is controlled by the MR and CR registers ...
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... NXP Semiconductors If CTS option is enabled (MR2[4] = 1), the CTS input at IP0 or IP1 must be LOW in order for the character to be transmitted. The transmitter will check the state of the CTS input at the beginning of each character transmitted found to be HIGH, the transmitter will delay the transmission of any following characters until the CTS has returned to the LOW state ...
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... NXP Semiconductors 6.3.4 Receiver FIFO The Rx FIFO consists of a First-In-First-Out (FIFO) stack with a capacity characters. Data is loaded from the receive shift register into the topmost empty position of the FIFO. The RxRDY bit in the status register is set whenever one or more characters are available to be read, and a FFULL status bit is set if all stack positions are filled with data ...
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... NXP Semiconductors A receiver reset will discard the present shift register date, reset the receiver ready bit (RxRDY), clear the status of the byte at the top of the FIFO and realign the FIFO read/write pointers. 6.3.7 Watchdog A watchdog timer is associated with each receiver. Its interrupt is enabled by MR0[7]. The purpose of this timer is to alert the control processor that characters are in the Rx FIFO which have not been read ...
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... NXP Semiconductors 6.3.9 Time-out mode caution When operating in the special time-out mode possible to generate what appears false interrupt, i.e., an interrupt without a cause. This may result when a time-out interrupt occurs and then, before the interrupt is serviced, another character is received, i.e., the data stream has started again. (The interrupt latency is longer than the pause in the data stream ...
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... NXP Semiconductors For example, changing the number of bits per character while the transmitter is active may cause the transmission of an incorrect character. In general, the contents of the MR, the CSR, and the OPCR should only be changed while the receiver(s) and transmitter(s) are not enabled, and certain changes to the ACR should only be made while the C/T is stopped ...
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... NXP Semiconductors Table 5. Register name Command Register Receiver FIFO Transmitter FIFO Table 6. Register name Input Port Change Register Auxiliary Control Register Interrupt Status Register Interrupt Mask Register Counter/Timer Upper value Counter/Timer Lower value Counter/Timer Preset Upper Counter/Timer Preset Lower Input Port Register Output Confi ...
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... NXP Semiconductors Table 11 Command Register 7 6 channel command code Table 12 channel Status Register 7 6 received framing error break Table 13. IMR - Interrupt Mask Register (enables interrupts change input change break port B Table 14. ISR - Interrupt Status Register 7 6 input port change break change B Table 15 ...
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... NXP Semiconductors Table 21. ROPR - Reset Output Port bits Register (ROPR reset OP7 reset OP6 Table 22. OPCR - Output Port Configuration Register OP1 and OP0 are the RTSN output and are controlled by the MR register 7 6 configure configure OP7 OP6 7.3 Register descriptions 7 ...
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... NXP Semiconductors Table 24. Bit Table 25. RxINT[2:1] (bits MR0[6] and MR1[6]) FIFOSIZE = 0 (8 bytes FIFOSIZE = 1 (16 bytes [1] Interrupt fill level must be set when the transmit and receive FIFOs are empty, otherwise the new level takes effect only after a read or a write to the FIFO. ...
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... NXP Semiconductors 7.3.1.2 Mode Register 1 channel A (MR1A) Table 27. MR1A - Mode Register 1 channel A (address 0x0) bit allocation MR1A is accessed when the channel A MR pointer points to MR1. The pointer is set to MR1 by RESET set pointer command applied via CR command 1. After reading or writing MR1A, the pointer will point to MR2A ...
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... NXP Semiconductors Table 28. Bit 2 1:0 7.3.1.3 Mode Register 2 channel A (MR2A) Table 29. MR2A - Mode Register 2 channel A (address 0x0) bit allocation MR2A is accessed when the channel A MR pointer points to MR2, which occurs after any access to MR1A. Accesses to MR2A do not change the pointer channel mode Table 30 ...
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... NXP Semiconductors Table 30. Bit SC28L92_7 Product data sheet 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter MR2A - Mode Register 2 channel A (address 0x0) bit description Symbol Description - Channel A transmitter Request To Send (RTS) control RTS control 1 = RTS control This bit controls the deactivation of the RTSAN output (OP0) by the transmitter ...
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... NXP Semiconductors Table 31. Mode Normal Automatic echo Local loopback Remote loopback Table 32. MR2A[3:0] (hexadecimal SC28L92_7 Product data sheet 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter DUART mode description Description The transmitter and receiver operating independently. Places the channel in the automatic echo mode, which automatically retransmits the received data ...
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... NXP Semiconductors Table 32. MR2A[3:0] (hexadecimal [1] Add 0.5 to values shown for channel is programmed for 5 bit per character 7.3.1.4 Mode Register 0 channel B (MR0B) MR0B (address 0x8) is accessed when the channel B MR pointer points to MR1. The pointer is set to MR0 by RESET set pointer command applied via CRB. After reading or writing MR0B, the pointer will point to MR1B. The bit defi ...
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... NXP Semiconductors 7.3.2 Clock select registers Table 33. 7 7.3.2.1 Clock Select Register channel A (CSRA) Table 34. Bit Table 35. Baud rate (based on a 3.6864 MHz crystal clock) See Table 36 for bit rate characteristics. CSR[7:4] MR0[ (Normal mode) CSR[3:0] ACR[ 0000 50 0001 110 0010 134 ...
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... NXP Semiconductors Table 36. Crystal or clock = 3.6864 MHz. Normal rate (baud 110 134.5 150 200 300 600 1050 1200 1800 2000 2400 4800 7200 9600 19200 38400 [1] Duty cycle of 16 clock 7.3.2.2 Clock Select Register channel B (CSRB) Table 37. Bit SC28L92_7 Product data sheet 3 ...
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... NXP Semiconductors 7.3.3 Command registers Table 38. 7 7.3.3.1 Command Register channel A (CRA) CRA is a register used to supply commands to channel A. Multiple commands can be specifi single write to CRA as long as the commands are non-conflicting, e.g., the enable transmitter and reset transmitter commands cannot be specifi single command word ...
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... NXP Semiconductors Table 40. Command 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 7.3.3.2 Command Register channel B (CRB) CRB is a register used to supply commands to channel B. Multiple commands can be specifi single write to CRB as long as the commands are non-conflicting, e.g., the enable transmitter and reset transmitter commands cannot be specifi ...
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... NXP Semiconductors 7.3.4 Status registers 7.3.4.1 Status Register channel A (SRA) Table 41. 7 received [1] break [1] These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits [7:5] from the top of the FIFO together with bits [4:0]. These bits are cleared by a reset error status command ...
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... NXP Semiconductors Table 42. Bit Symbol TxEMTA 2 TxRDYA 1 FFULLA 0 RxRDYA SC28L92_7 Product data sheet 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter SRA - Status register channel A (address 0x1) bit description Description Channel A overrun error yes This bit, when set, indicates that one or more characters in the received data stream have been lost ...
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... NXP Semiconductors 7.3.4.2 Status Register channel B (SRB) Table 43. 7 received [1] break [1] These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits [7:5] from the top of the FIFO together with bits [4:0]. These bits are cleared by a reset error status command ...
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... NXP Semiconductors Table 45. Bit 3 and 2 1 and 0 SC28L92_7 Product data sheet 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter OPCR - Output configuration control register (address 0xD) bit description Symbol Description - OP3 output select 00 = The complement of OPR[ The counter/timer output, in which case OP3 acts as an open-drain output ...
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... NXP Semiconductors 7.3.6 Set Output Port bits Register (SOPR) Ones in the byte written to this register will cause the corresponding bit positions in the OPR to set to 1. Zeros have no effect. This allows software to set individual bits without keeping a copy of the OPR bit configuration. ...
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... NXP Semiconductors 7.3.7 Reset Output Port bits Register (ROPR) Ones in the byte written to the ROPR will cause the corresponding bit positions in the OPR to set to 0. Zeros have no effect. This allows software to reset individual bits without keeping a copy of the OPR bit configuration. ...
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... NXP Semiconductors 7.3.8 Output Port Register (OPR) Table 50. The output pins (OP pins) drive the complement of the data in this register as controlled by SOPR and ROPR. 7 OP7 Table 51. Bit SC28L92_7 Product data sheet 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter OPR - Output port register (no address) bit allocation ...
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... NXP Semiconductors 7.3.9 Auxiliary Control Register (ACR) Table 52. ACR - Auxiliary control register (address 0x4) bit allocation 7 6 BRG set counter/timer mode and clock source select select Table 53. Bit Table 54. ACR[6:4] 000 001 010 011 100 101 110 111 [1] The timer mode generates a square wave. ...
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... NXP Semiconductors 7.3.10 Input Port Change Register (IPCR) Table 55. 7 delta IP3 Table 56. Bit 7.3.11 Interrupt Status Register (ISR) This register provides the status of all potential interrupt sources. The contents of this register are masked by the Interrupt Mask Register (IMR bit in the ISR is a logic 1 and the corresponding bit in the IMR is also a logic 1, the INTRN output will be asserted (LOW) ...
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... NXP Semiconductors Table 58. Bit Symbol RxRDYB 4 TxRDYB RxRDYA 0 TxRDYA SC28L92_7 Product data sheet 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter ISR - Interrupt status register (address 0x5) bit description Description Channel B change in break not active 1 = active This bit, when set, indicates that the channel B receiver has detected the beginning or the end of a received break ...
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... NXP Semiconductors 7.3.12 Interrupt Mask Register (IMR) The programming of this register selects which bits in the ISR causes an interrupt output bit in the ISR is a logic 1 and the corresponding bit in the IMR is also a logic 1 the INTRN output will be asserted. If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no effect on the INTRN output ...
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... NXP Semiconductors 7.3.13 Interrupt Vector Register (IVR; 68xxx mode) or General Purpose register (GP; 80xxx mode) This register stores the Interrupt Vector initialized to 0x0F on hardware reset and is usually changed from this value during initialization of the SC28L92. The contents of this register will be placed on the data bus when IACKN is asserted LOW or a read of address 0xC is performed ...
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... NXP Semiconductors The counter ready status bit (ISR[3]) is set once each cycle of the square wave. The bit is reset by a stop counter command (read with 1111). The command however, does not stop the C/T. The generated square wave is output on OP3 programmed to be the C/T output. In the counter mode, the value C/T loaded into CTPU and CTPL by the CPU is counted down to 0 ...
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... NXP Semiconductors MR2[4] is the bit that allows the transmitter to be controlled by the CTS pin (IP0 or IP1). When this bit is set to one AND the CTS input is driven HIGH, the transmitter will stop sending data at the end of the present character being serialized usually the RTS output of the receiver that will be connected to the transmitter’ ...
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... NXP Semiconductors 9. Static characteristics Table 65. Static characteristics operation +85 C; unless otherwise specified. CC amb Symbol Parameter V input LOW voltage IL V input HIGH voltage IH V output LOW voltage OL V output HIGH voltage OH I Power-down mode input current I(1XPD) on pin X1/CLK I operating input LOW current on ...
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... NXP Semiconductors ( amb ( 5 amb Bus cycle times: 80xxx mode for V DD RWD 68xxx mode cycle of the X1 clock for = 70 ns for V CSC DAT Fig 9. Port timing as a function of capacitive loading at typical conditions SC28L92_7 Product data sheet 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter ...
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... NXP Semiconductors Table 66. Static characteristics, 3.3 V operation +85 C; unless otherwise specified. CC amb Symbol Parameter V input LOW voltage IL V input HIGH voltage IH V output LOW voltage OL V output HIGH voltage OH I Power-down mode input I(1XPD) current on pin X1/CLK I operating input LOW current ...
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... NXP Semiconductors 10. Dynamic characteristics Table 67. Dynamic characteristics operation +85 C, unless otherwise specified. CC amb Symbol Parameter Reset timing (see Figure 10) t reset pulse width RES [2] Bus timing (see Figure 11 set-up time to RDN, WRN LOW hold time from RDN, WRN LOW ...
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... NXP Semiconductors Table 67. Dynamic characteristics operation +85 C, unless otherwise specified. CC amb Symbol Parameter Clock timing (see Figure 17) t X1/CLK HIGH or LOW time CLK f X1/CLK frequency CLK t C/T clock (IP2) HIGH or LOW time (C/T CTC external clock input) f C/T clock (IP2) frequency ...
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... NXP Semiconductors [7] Minimum DACKN time is (( DCR cycles, the 80xxx bus timing may be used while in the 68xxx mode not necessary to wait for DACKN to insure the proper operation of the SC26C92. In all cases the data will be written to the SC28L92 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle ...
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... NXP Semiconductors Table 68. Dynamic characteristics, 3.3 V operation +85 C, unless otherwise specified. CC amb Symbol Parameter Clock timing (see Figure 17) t X1/CLK HIGH or LOW time CLK f X1/CLK frequency CLK t C/T clock (IP2) HIGH or LOW time (C/T CTC external clock input) f C/T clock (IP2) frequency ...
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... NXP Semiconductors [7] Minimum DACKN time is (( DCR cycles, the 80xxx bus timing may be used while in the 68xxx mode not necessary to wait for DACKN to insure the proper operation of the SC26C92. In all cases the data will be written to the SC28L92 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle ...
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... NXP Semiconductors Fig 12. Bus timing, read cycle (68xxx mode) Fig 13. Bus timing, write cycle (68xxx mode) SC28L92_7 Product data sheet 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter t CSC X1/CLK R/ CEN not valid t DA DACKN DACKN LOW requires two rising edges of X1 clock after CEN is LOW. ...
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... NXP Semiconductors Fig 14. Interrupt cycle timing (68xxx mode) a. Input pins. b. Output pins. Fig 15. Port timing SC28L92_7 Product data sheet 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter t CSC X1/CLK INTRN IACKN DACKN DACKN LOW requires two rising edges of X1 clock after CEN is LOW. ...
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... NXP Semiconductors (1) IRQN or OP3 to OP7 when used as interrupt outputs. Fig 16. Interrupt timing (80xxx mode) SC28L92_7 Product data sheet 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter WRN (1) interrupt output RDN (1) interrupt output The test for open-drain outputs is intended to guarantee switching of the output transistor. ...
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... NXP Semiconductors t CLK t CTC X1/CLK C/T clock RxC TxC 3 pF parasitic capacitance 3 pF parasitic capacitance for C = 13.5 pF. For the oscillator feedback loop, the capacitors C1 and C2 are in series and C2 should be chosen according to the crystal manufacturer’s specification. C1 and C2 values will include any parasitic capacitance of the wiring and X1, X2 pins. ...
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... NXP Semiconductors D1 TxD transmitter enabled TxRDY (SR2) WRN D1 D8 (1) CTSN (IP0) (2) RTSN (OP0) OPR( (1) Timing shown for MR2[ (2) Timing shown for MR2[ Fig 20. Transmitter timing D1 RxD receiver enabled RxRDY (SR) FFULL (CR) RxRDY/ FFULL (2) (OP5) RDN status data OVERRUN (SR) (1) RTS (OP0) OPR[ (1) Timing shown for MR1[ ...
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... NXP Semiconductors master station: TxD ADD#1 transmitter enabled TxRDY (SR) WRN MR1[4: ADD#1 MR1[ MR1[ peripheral station: bit 9 RxD 0 receiver enabled RxRDY (SR) RDN/WRN MR1[4: Fig 22. Wake-up mode timing 12. Test information Fig 23. Test conditions on outputs SC28L92_7 Product data sheet 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter ...
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... NXP Semiconductors 13. Package outline PLCC44: plastic leaded chip carrier; 44 leads pin 1 index DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. 4.57 0.53 mm 0.51 0.25 3.05 4.19 0.33 0.180 0.021 inches 0.02 0.01 0.12 0.165 0.013 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 1. pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.25 1.85 mm 2.1 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT307-2 Fig 25 ...
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... NXP Semiconductors HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 0.85 mm terminal 1 index area terminal 1 48 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max 0.05 0. 0.2 0.00 0.15 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included ...
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... NXP Semiconductors 14. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 27. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 15. Abbreviations Table 71. Acronym DMA UART FIFO CPU COS BRG MIDI C/T SC28L92_7 Product data sheet 3 ...
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... Release date SC28L92_7 20071219 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • added HVQFN48 package option • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Functional description . . . . . . . . . . . . . . . . . . 13 6.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1.1 Data bus buffer . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1.2 Operation control . . . . . . . . . . . . . . . . . . . . . . 13 6.1.3 Interrupt control . . . . . . . . . . . . . . . . . . . . . . . 13 6.1.4 FIFO configuration . . . . . . . . . . . . . . . . . . . . . 14 6 ...