ISD5116SY Nuvoton Technology Corporation of America, ISD5116SY Datasheet
ISD5116SY
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ISD5100 SERIES SINGLE-CHIP MINUTES DURATION VOICE RECORD/PLAYBACK DEVICES WITH DIGITAL STORAGE CAPABILITY ISD5100 SERIES Publication Release Date: Oct 31, 2008 - 1 - Revision 1.42 ...
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GENERAL DESCRIPTION ................................................................................................................4 2. FEATURES ........................................................................................................................................5 3. BLOCK DIAGRAM .............................................................................................................................6 4. PIN CONFIGURATION......................................................................................................................7 5. PIN DESCRIPTION ...........................................................................................................................8 6. FUNCTIONAL DESCRIPTION ..........................................................................................................9 6.1. Overview ....................................................................................................................................9 6.1.1 Speech/Voice Quality .........................................................................................................9 6.1.2 Duration ..............................................................................................................................9 6.1.3 Flash Technology ...............................................................................................................9 6.1.4 Microcontroller Interface .....................................................................................................9 ...
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Digital Mode .............................................................................................................................36 6.5.1 Erasing Digital Data ..........................................................................................................36 6.5.2 Writing Digital Data ...........................................................................................................36 6.5.3 Reading Digital Data.........................................................................................................37 6.5.4 Example Command Sequences .......................................................................................37 6.6. Pin Details ................................................................................................................................48 6.6.1 Digital I/O Pins ..................................................................................................................48 6.6.2 Analog I/O Pins .................................................................................................................50 6.6.3 Power and ...
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GENERAL DESCRIPTION The ISD5100 ChipCorder Series provide high quality, fully integrated, single-chip Record/Playback solutions for 1- to 16-minute messaging applications that are ideal for use in cellular phones, automotive communications, GPS/navigation systems and other portable products. The ISD5100 ...
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FEATURES Fully-Integrated Solution • Single-chip voice record/playback solution • Dual storage of digital and analog data • Durations Device ISD5102 Duration minutes Low Power Consumption • Supply Voltage Commercial Temperature = +2.7V to +3.3V Industrial Temperature ...
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BLOCK DIAGRAM ISD5100-Series Block Diagram 6dB MICROPHONE MIC+ MIC IN AGC MIC - 1 (AGPD) AGCCAP AUX IN FILTO ANA IN 1 (INS0) AUX IN AUX IN ARRAY AMP 1 (AXPD) ( AXG0 ) 2 AXG1 XCLK ANA IN ...
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PIN CONFIGURATION SCL SDA SSD ISD5116 V 6 SSD ISD5108 7 NC ISD5104 8 MIC+ ISD5102 9 V SSA 10 MIC- 11 ANA OUT+ 12 ANA OUT- 13 ACAP 14 SP- ...
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PIN DESCRIPTION Pin Name SOIC/PDIP TSOP SCL SDA 5,6 12,13 SSD NC 7,21,22 1,14,28 MIC 9,15,23 2,15,22 SSA MIC ANA OUT ...
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FUNCTIONAL DESCRIPTION 6.1. O VERVIEW 6.1.1 Speech/Voice Quality The ISD5100 ChipCorder Series can be configured via software to operate at 4.0, 5.3, 6.4 or 8.0 kHz sampling frequency to select appropriate voice quality. Increasing the duration decreases the sampling ...
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These are the RAC timing pin and the INT pin for interrupts to the controller. Communications with all the internal registers of any operations are through the serial bus, as well as digital memory Read and Write operations. 6.1.5 ...
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Mic inputs are fed to AUX OUT and transmitted to the phone line, while message from other party is input from the AUX IN, then fed through to the speaker for listening. The ISD5100 device has the ...
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Digital data is sent and received serially over the I and stored in one of two alternating (commutating) 64-bit shift registers. When an input register is full, it becomes the register that is parallel written into the array. The prior ...
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ISD5100 Series I C Operation Definitions There are many control functions used to operate the ISD5100-Series. Among them are: 6.3.1.1. Read Status Command: The Read Status command is a read ...
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Note that the processor could have sent an I after the Status Word data transfer and aborted the transfer of the Address bytes. A graphical representation of this operation is found below. See the caption box above for more explanation. ...
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Load Command Byte Register (Single Byte Load): A single byte may be written to the Command Byte Register in order to power up the device, start or stop Analog Record (if no address information is needed ...
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I C Control Registers The ISD5100 Series are controlled by loading commands to, or, reading from, the internal command, configuration and address registers. The Command byte sent is used to start and stop recording, write or read digital ...
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Register Bits The register load may be used to modify a command sequence (such as load an address) or used with the null command sequence to load a configuration or test register. Not all registers are accessible to the user. ...
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OPCODE COMMAND BYTE TABLE OPCODE COMMAND BIT NUMBER POWER UP POWER DOWN STOP (DO NOTHING) STAY ON STOP (DO NOTHING) STAY OFF LOAD CFG0 LOAD CFG1 RECORD ANALOG RECORD ANALOG @ ADDR PLAY ANALOG PLAY ANALOG @ ADDR MSG CUE ...
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Data Bytes 2 In the I C write mode, the device can accept data sent after the command byte register load option is selected, the next two bytes are loaded into the selected register. The format of ...
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Configuration Register Bytes The configuration register bytes are defined, in detail, in the drawings of drawings display how each bit enables or disables a function of the audio paths in the ISD5100- Series. The tables below give a general ...
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Configuration Register 1 (CFG1) Configuration Register 1 (CFG1) D15 D14 D13 D12 D11 D10 D9 D15 D14 D13 D12 D11 D10 D9 D15 D14 D13 D12 D11 D10 D9 D15 D14 D13 D12 D11 D10 D9 VLS1 VLS0 VOL2 VOL1 ...
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Record Mode The command sequence for an Analog Record would be a four byte sequence consisting of the Slave Address (80h), the Command Byte (91h) for Record Analog @ Address, and the two address bytes. See “Load Command Byte Register ...
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To select this mode, the following control bits must be configured in the ISD5100 Series configuration registers. To set up the transmit path: 1. Select the FTHRU path through the ANA OUT MUX—Bits AOS0, AOS1 and AOS2 control the state ...
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Don’t Care bits — The following stages are not used in Feed Through Mode. Their bits may be set to either level. In this example, we will set all the following bits to a ZERO. (a). Bit INS0, bit ...
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Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 controls the state of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the SUM1 SUMMING amplifier path. 4. ...
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Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 controls the state of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the SUM1 SUMMING amplifier path. 5. ...
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Select the SUM2 SUMMING amplifier path through the VOLUME MUX — Bits VLS0 and VLS1 control the state VOLUME MUX. These bits are bits D14 and D15, respectively of CFG1. They should be set to the state where D14 ...
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A M NALOG ODE 6.4.1 Aux In and Ana In Description The AUX additional audio input to the ISD5100-Series, such as from the microphone circuit in a mobile phone “car kit.” This input has a nominal ...
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ISD5100 Series Analog Structure (left half) Description INP INPU RCE MUX AGC AMP AMP (INS0) S UM1 MUX AMP INSO Source 2 (S1S1,S1S0) ...
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ISD5100 Series Aanalog Structure (right half) Description FILTER MUX MUX SUM1 ARR AY FLS0 SOURCE 0 SUM1 1 ARRAY FLPD CONDITION 0 Power Up 1 Power Down ANA IN AMP XCL K FLD1 FLD0 SAMPLE ...
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Volume Control Description VOL AMP MUX S UM2 S UM1 INP 2 (VLS1,VLS0) VLS1 VLS0 SOURCE 0 0 ANA IN AMP 0 1 SUM2 1 0 SUM1 1 1 INP AIG1 AIG0 AIPD AXG1 AXG0 AXPD ...
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Speaker and Aux Out Description OU T PUT MUX VOL ANA IN AMP FIL UM2 2 (OPS1 OPS1 AIG1 AIG0 AIPD AXG1 AXG0 ...
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Ana Out Description * FT HRU * INP * VOL * FIL TO * SUM1 * SUM2 3 (AOS 2,AOS1,AOS 0) *DIFFERENTIAL PATH AIG1 AIG0 AIPD AXG1 AXG0 AXPD 6.4.7 Analog Inputs Microphone ...
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MIC C– ACA P * Diffe re ntial Path VLS 1 VLS0 VOL 2 VOL 1 VOL0 S1S 1 S1S0 ANA IN (Analog Input) The ANA IN pin is ...
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Gain from ANA IN to SP+/- 2. Gain from ANA IN to ARRAY IN 3. 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB below clipping 4. Speaker Out ...
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D M IGITAL ODE 6.5.1 Erasing Digital Data The Digital Erase command can only erase an entire page at a time. This means that the D1 command only needs to include the 11-bit page address; the 5-bit for block ...
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Reading Digital Data The Digital Read command utilizes the combined I the chip using the write data direction. Then the data direction is reversed by sending a repeated start condition, and the slave address with R/W set to 1. ...
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SendByte(row/256) - high address byte WaitACK WaitSCLHigh SendByte(row%256) - low address byte WaitACK WaitSCLHigh I2CStop repeat until the number of RAC pulses are one less than the number of rows to delete { wait RAC low WAIT RAC high } ...
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WaitACK WaitSCLHigh SendByte(0x40) - Exit Digital Mode Command WaitACK WaitSCLHigh I2Cstop Notes 1. Erase operations must be addressed on a Row boundary. The 5 LSB bits of the Low Address Byte will be ignored bus is ...
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S SLAVE ADDRESS S SLAVE ADDRESS W A Command Byte "N" RAC cycles Last erased row Note Note S SLAVE ADDRESS W A CON A Erase starts on falling edge of Slave acknowledge D1 A DATA A DATA A High ...
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SUGGESTED FLOW FOR DIGITAL ERASE IN ISD5100-Series ENTER DIGITAL 80,C0 MODE SEND ERASE 80,D1,nn,nn COMMAND COMMANDS 80 = PowerUp or Stop C0 = Enter Digital Mode D1 = Erase Digital Page Exit Digital Mode SEND STOP 80,C0 COMMAND ...
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Write Digital Data Write ===== I2CStart SendByte(0x80) - Write, Slave address zero WaitACK WaitSCLHigh SendByte(0xc0) - Enter Digital Mode Command WaitACK WaitSCLHigh I2CStop I2CStart SendByte(0x80) - Write, Slave address zero WaitACK WaitSCLHigh SendByte(0xc9) - Write Digital Data Command WaitACK ...
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I2CStart SendByte(0x80) - Write, Slave address zero WaitACK WaitSCLHigh SendByte(0x40) - Exit Digital Mode Command WaitACK WaitSCLHigh I2CStop S SLAVE ADDRESS S SLAVE ADDRESS S SLAVE ADDRESS W A CON W A C9h A DATA Command Byte High Addr. Byte ...
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Read Digital Data Read ===== I2CStart SendByte(0x80) - Write, Slave address zero WaitACK WaitSCLHigh SendByte(0xc0) - Enter Digital Mode WaitACK WaitSCLHigh I2CStop I2CStart SendByte(0x80) - Write, Slave address zero WaitACK WaitSCLHigh SendByte(0xe1) - Read Digital Data Command WaitACK WaitSCLHigh ...
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I2CStop() I2CStart SendByte(0x80) - Write, Slave address zero WaitACK WaitSCLHigh SendByte(0x40) - Exit Digital Mode WaitACK WaitSCLHigh I2CStop S SLAVE ADDRESS W S SLAVE ADDRESS Command Byte S SLAVE ADDRESS S SLAVE ADDRESS W A CON A E1h A ...
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ETAILS 6.6.1 Digital I/O Pins SCL (Serial Clock Line) The Serial Clock Line is a bi-directional clock line open-drain line requiring a pull-up resistor to Vcc driven by the "master" chips ...
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RAC Waveform During Digital Erase @ 8kHz Operation INT (Interrupt) INT is an open drain output pin. The ISD5100 Series interrupt pin goes LOW and stays LOW when an Overflow (OVF) or End of Message (EOM) marker is detected. Each ...
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A0, A1 (Address Pins) These two pins are normally strapped for the desired address that the ISD5100 Series will have on the serial interface. If there are four of these devices on the bus, then each must ...
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ACAP (AGC Capacitor) This pin provides the capacitor connection for setting the parameters of the microphone AGC circuit. It should have a 4.7 µF capacitor connected to ground. It cannot be left floating. This is because the capacitor is also ...
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ANA IN (Analog Input) The ANA IN pin is the analog input from the telephone chip set. It can be switched (by the I interface) to the speaker output, the array input or to various other paths. This pin is ...
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AUX IN (Auxiliary Input) The AUX additional audio input to the ISD5100-Series, such as from the microphone circuit in a mobile phone “car kit.” This input has a nominal 694 mV p-p level at its minimum gain ...
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Power and Ground Pins (Voltage Inputs) CCA CCD To minimize noise, the analog and digital circuits in the ISD5100 Series devices use separate power busses. These +3 V busses lead to separate pins. Tie the V ...
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PCB Layout Examples For SOIC package : PC board traces and the three chip capacitors are on the bottom side of the board. Note Note 3 (Digital G round) Note 1: V traces should ...
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ISD5100 SERIES Publication Release Date: Oct 31, 2008 - 56 - Revision 1.42 ...
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TIMING DIAGRAMS 2 7 IMING IAGRAM START SDA SCL SU-DAT t HIGH t LOW t SCLK - 57 - ISD5100 SERIES STOP SU-STO Publication Release Date: Oct ...
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PARAMETER SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data set-up time ...
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LAYBACK AND TOP YCLE t START SDA PLAY AT ADDR SCL DATA CLOCK PULSES ANA IN ANA OUT ISD5100 SERIES t STOP STOP STOP Publication Release Date: Oct 31, 2008 - 59 - Revision 1.42 ...
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XAMPLE OF OWER OMMAND FIRST BITS - 60 - ISD5100 SERIES Publication Release Date: Oct 31, 2008 Revision 1.42 ...
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ABSOLUTE MAXIMUM RATINGS ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS) Junction temperature Storage temperature range Voltage Applied to any pins Voltage applied to any pin (Input current limited to +/-20 mA) Lead temperature (soldering – 10 seconds ...
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OPERATING CONDITIONS (PACKAGED PARTS) Conditions Commercial operating temperature [2] Supply voltage ( [3] Ground voltage ( Voltage Applied to any pins Conditions Industrial operating temperature [2] Supply voltage ( [3] Ground voltage (V ) ...
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ELECTRICAL CHARACTERISTICS 9. ENERAL ARAMETERS Symbol Parameters V Input Low Voltage IL V Input High Voltage IH V SCL, SDA Output OL Voltage V Input low voltage IL2V interface V Input high voltage for 2V IH2V interface ...
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T P IMING ARAMETERS Symbol Parameters F Sampling Frequency S F Filter Knee CF 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) T Record Duration REC 8.0 kHz (sample rate) 6.4 ...
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T RAC Clock Low Time RACL 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) T RAC Clock Period in RACM Message Cueing Mode 8.0 kHz (sample rate) 6.4 ...
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A P NALOG ARAMETERS (14) MICROPHONE INPUT Symbol Parameters V MIC +/- Input Voltage MIC+/- V MIC +/- input MIC (0TLP) transmission (0TLP) A Gain from MIC +/- input to MIC ANA OUT A MIC +/- Gain Tracking MIC ...
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AUX IN Symbol Parameters V AUX IN Input Voltage AUX IN V AUX IN (0TLP) AUX IN (0TLP) Voltage A Gain from AUX IN to ANA AUX IN (ANA OUT) OUT A AUX IN Gain Accuracy AUX IN (GA) ...
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F Frequency Response (300- R 3400 Hz) P Power Output (Low Gain OUTLG Setting) SINAD SINAD ANA IN to SP+/- (14) ANA OUT Symbol Parameters SINAD SINAD, MIC IN to ANA OUT SINAD SINAD, AUX IN to ANA OUT (0 ...
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C T ANA OUT to AUX OUT R ANA OUT/AUX Cross Talk OUT (14) AUX OUT Symbol Parameters V AUX OUT – Maximum AUX OUT Output Swing R Minimum Load Impedance L C Maximum Load Capacitance L V AUX OUT ...
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Conditions 1. Typical values 25°C and Vcc = 3.0V All min/max limits are guaranteed by Nuvoton via electrical testing or characterization. Not all specifications are 100 percent tested. 3. Low-frequency cut off depends upon the value ...
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SDA SCL Start and stop conditions Both data and clock lines remain HIGH when the interface bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the start condition (S). A ...
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MICRO- CONTROLLER SDA SCL Example Acknowledge The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge ...
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ROTOCOL Since the I2C protocol allows multiple devices on the bus, each device must have an address. This address is known as a “Slave Address”. A Slave Address consists of 7 bits, followed by a ...
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Master Reads from Slave immediately after first byte (Read Mode) acknowledgement from slave S SLAVE ADDRESS R A From Master Start Bit R/W From From Master Master Another common operation in the ISD5100 Series is the reading of digital data ...
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TYPICAL APPLICATION CIRCUIT The following typical application example on ISD5100 series is for references only. They make no representation or warranty that such applications shall be suitable for the use specified. It’s customer’s obligation to verify the design in ...
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PACKAGE SPECIFICATION 11.1. 28-L 8 13.4 EAD X IQC e b θ LASTIC HIN MALL UTLINE Dimension in Inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. ...
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EAD Plastic Thin Small Outline Package (TSOP) Type ...
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EAD Plastic Small Outline Integrated Circuit (SOIC) Dimensions INCHES Min A 0.701 B 0.097 C 0.292 ...
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EAD IL Plastic Dual Inline Package (PDIP) (P) Dimensions INCHES Min Nom A 1.445 1.450 B1 0.150 B2 0.065 0.070 C1 0.600 C2 0.530 0.540 D D1 0.015 E 0.125 F 0.015 0.018 G 0.055 0.060 H ...
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ISD5116 D IE ISD5116 Device Die Dimensions X: 4125 µm Y: 8030 µm [3] Die Thickness 292.1 µm ± 12.7 µm Pad Opening Single pad µm Double pad: 180 x 90 µm V SSA MIC + ...
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ISD5116 Pad Coordinates (with respect to die center in µm) Pad Pad Name V Analog Ground SSA RAC Row Address Clock Interrupt INT XCLK External Clock Input V Digital Supply Voltage CCD V Digital Supply Voltage CCD SCL Serial Clock ...
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ISD5108 D IE ISD5108 Device Die Dimensions (include scribe line) X: 4230 µm Y: 6090 µm Die Thickness [3] 292.1 µm ± 12.7 µm Pad Opening Single pad µm Double pad: 180 x 90 µm V ...
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ISD5108 Pad Coordinates (with respect to die center in µm) Pad Pad Name V Analog Ground SSA RAC Row Address Clock Interrupt INT XCLK External Clock Input V Digital Supply Voltage CCD V Digital Supply Voltage CCD SCL Serial Clock ...
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ISD5104 D IE ISD5104 Device Die Dimensions (include scribe line) X: 4230 µm Y: 5046 µm [3] Die Thickness 292.1 µm ± 12.7 µm Pad Opening Single pad µm Double pad: 180 x 90 µm V ...
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ISD5104 Pad Coordinates (with respect to die center in µm) Pad Pad Name V Analog Ground SSA RAC Row Address Clock Interrupt INT XCLK External Clock Input V Digital Supply Voltage CCD V Digital Supply Voltage CCD SCL Serial Clock ...
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ISD5102 D IE ISD5102 Device Die Dimensions (include scribe line) X: 4230 µm Y: 5046 µm Die Thickness [3] 292.1 µm ± 12.7 µm Pad Opening Single pad µm Double pad: 180 x 90 µm V ...
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ISD5102 Pad Coordinates (with respect to die center in µm) Pad Pad Name V Analog Ground SSA RAC Row Address Clock Interrupt INT XCLK External Clock Input V Digital Supply Voltage CCD V Digital Supply Voltage CCD SCL Serial Clock ...
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... I I ISD5104EY I5104EY ISD5108EY ISD5104EYI I5104EY ISD5108EY ISD5100 SERIES ISD5108 ISD5116 Order # Part # Order # I5108X ISD5116X I5116X N/A ISD5116PY I5116PY I5108SY ISD5116SY I5116SY I5108SY ISD5116SYI I5116SY I I I5108EY ISD5116EY I5116EY I5108EY ISD5116EYI I5116EY I I Publication Release Date: Oct 31, 2008 Revision 1.42 ...
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VERSION HISTORY VERSION DATE 0.1 Mar 2003 New data sheet for the ISD5100-Series 0.2 Oct 2003 Add I5102 and I5104 products Utilize TAD application in Functional Details Reserve Load Address feature for factory uses Simplify Playback mode AnaIn: add ...
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Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other ...