TDA8932BTW/N2,118 NXP Semiconductors, TDA8932BTW/N2,118 Datasheet - Page 10

• Manufacturer Part Number: TDA8932BTW/N2,118
• Description: IC AMP AUDIO CLASS D 32HTSSOP
• Manufacturer: NXP Semiconductors
• Type: Class Dr

Specifications of TDA8932BTW/N2,118

• Output Type: 1-Channel (Mono) or 2-Channel (Stereo)
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Max Output Power X Channels @ Load: 55W x 1 @ 8 Ohm; 26.5W x 2 @ 4 Ohm
• Voltage - Supply: 10 V ~ 36 V, ±5 V ~ 18 V
• Features: Depop, Differential Inputs, Mute, Short-Circuit and Thermal Protection
• Mounting Type: Surface Mount
• Product: Class-D
• Output Power: 55 W
• Available Set Gain: 36 dB
• Common Mode Rejection Ratio (min): 75 dB
• Thd Plus Noise: 0.007 %
• Operating Supply Voltage: 22 V
• Supply Current: 0.145 mA
• Maximum Power Dissipation: 5000 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Audio Load Resistance: 8 Ohms
• Dual Supply Voltage: +/- 11 V
• Input Signal Type: Differential
• Minimum Operating Temperature: - 40 C
• Output Signal Type: Differential, Single
• Supply Type: Single or Dual
• Supply Voltage (max): 36 V
• Supply Voltage (min): 10 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935283479118

NXP Semiconductors
UJA1079_2
Product data sheet
6.1.5 Sleep mode
6.1.6 Overtemp mode
6.2.1 Introduction
6.2 SPI
Sleep mode is selected from Standby mode or Normal mode by setting bits MC in the
Mode_Control register
no pending interrupts (INTN = HIGH) or wake-up events and at least one wake-up source
is enabled (LIN or WAKE). Any attempt to enter Sleep mode while one of these conditions
has not been satisfied will result in a short reset (3.6 ms minimum pulse width;
see
In Sleep mode, V1 is off and the LIN transceiver will be switched off (Off mode;
STBCL = 0; see
wake-up detection active - see
LOW.
A LIN or local wake-up event will cause the SBC to switch from Sleep mode to Standby
mode, generating a (short or long; see
control bits (MC) will be changed to 00 and V1 will be enabled.
The SBC will enter Overtemp mode from Normal mode or Standby mode when the chip
temperature exceeds the overtemperature protection activation threshold, T
In Overtemp mode, the voltage regulator is switched off and the bus system is in a
high-resistive state. When the SBC enters Overtemp mode, the RSTN pin is driven LOW
and the limp home control bit, LHC, is set so that the LIMP pin is driven LOW.
The chip temperature must drop a hysteresis level below the overtemperature shutdown
threshold before the SBC can exit Overtemp mode. After leaving Overtemp mode the
SBC enters Standby mode and a system reset is generated (reset pulse width of t
long or short; see
The Serial Peripheral Interface (SPI) provides the communication link with the
microcontroller, supporting multi-slave operations. The SPI is configured for full duplex
data transfer, so status information is returned when new control data is shifted in. The
interface also offers a read-only access option, allowing registers to be read back by the
application without changing the register content.
The SPI uses four interface signals for synchronization and data transfer:
Bit sampling is performed on the falling clock edge and data is shifted on the rising clock
edge (see
•
•
•
•
SCSN: SPI chip select; active LOW
SCK: SPI clock; default level is LOW due to low-power concept
SDI: SPI data input
SDO: SPI data output; floating when pin SCSN is HIGH
Section 6.5.1
Figure
All information provided in this document is subject to legal disclaimers.
Table
4).
and
Section 6.5.1
Table
6) or in a low-power state (Lowpower mode; STBCL = 1) with bus
(Table
Rev. 02 — 27 May 2010
11).
5) to 01. The SBC will enter Sleep mode providing there are
Section
and
Table
Section
6.7.1). The watchdog is off and the reset pin is
11).
6.5.1) system reset. The value of the mode
LIN core system basis chip
UJA1079
© NXP B.V. 2010. All rights reserved.
th(act)otp
w(rst)
.
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