UPD3728DZ Renesas Electronics Corporation., UPD3728DZ Datasheet

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UPD3728DZ

Manufacturer Part Number
UPD3728DZ
Description
Manufacturer
Renesas Electronics Corporation.
Datasheet

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Part Number:
UPD3728DZ
Manufacturer:
NEC
Quantity:
6 219
Document No. S15417EJ2V0DS00 (2nd edition)
Date Published October 2002 NS CP (K)
Printed in Japan
DESCRIPTION
changes optical images to electrical signal and has the function of color separation.
transfer register, which transfers the photo signal electrons of 7300 pixels separately in odd and even pixels.
Therefore, it is suitable for 600 dpi/A3 high-speed color digital copiers and so on.
FEATURES
• Valid photocell
• Photocell pitch
• Line spacing
• Color filter
• Resolution
• Drive clock level : CMOS output under 5 V operation
• Data rate
• Output type
• Power supply
• On-chip circuits : Reset feed-through level clamp circuits
ORDERING INFORMATION
The µ PD3728DZ is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which
The µ PD3728DZ has 3 rows of 7300 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge
Part Number
µ PD3728DZ
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
7300 PIXELS × × × × 3 COLOR CCD LINEAR IMAGE SENSOR
: 7300 pixels × 3
: 10 µ m
: 40 µ m (4 lines) Red line - Green line, Green line - Blue line
: Primary colors (red, green and blue), pigment filter (with light resistance 10
: 24 dot/mm A3 (297 × 420 mm) size (shorter side)
: 40 MHz MAX. (20 MHz/1 output)
: 2 outputs in phase/color
: +12 V
Voltage amplifiers
CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600))
The mark
shows major revised points.
DATA SHEET
Package
MOS INTEGRATED CIRCUIT
µ µ µ µ PD3728DZ
7
lx•hour)
2001

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UPD3728DZ Summary of contents

Page 1

PIXELS × × × × 3 COLOR CCD LINEAR IMAGE SENSOR DESCRIPTION The µ PD3728DZ is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the ...

Page 2

BLOCK DIAGRAM φ φ CLB GND V 2 OUT 32 (Blue, even) GND OUT 34 (Blue, odd) GND OUT 36 (Green, odd OUT 1 (Green, even) GND 2 ...

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PIN CONFIGURATION (Top View) CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600)) • µ PD3728DZ Output signal 4 (Green, even) Ground Output signal 6 (Red, even) Ground Output signal 5 (Red, odd) Ground Output drain voltage Reset ...

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ABSOLUTE MAXIMUM RATINGS (T Parameter Output drain voltage Shift register clock voltage Reset gate clock voltage Reset feed-through level clamp clock voltage Transfer gate clock voltage Note Operating ambient temperature Storage temperature Note Use at the condition without dew condensation. ...

Page 5

ELECTRICAL CHARACTERISTICS = +25° MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 V φ light source: 3200 K halogen lamp +C-500S ...

Page 6

C, V INPUT PIN CAPACITANCE (T A Parameter Shift register clock pin capacitance 1 Shift register clock pin capacitance 2 Last stage shift register clock pin capacitance Reset gate clock pin ...

Page 7

TIMING CHART 1 (Bit clamp mode, for each color) φ φ TG1 to TG3 φ φ 10) φ φ 20) φ 1L φ RB φ CLB Note OUT ...

Page 8

TIMING CHART 2 (Bit clamp mode, for each color) φ φ 10) φ φ 20) φ 1L φ RB φ CLB OUT OUT Symbol t1, t2 t1’, t2’ t5, ...

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TIMING CHART 3 (Bit clamp, for each color) φ φ TG1 to TG3 φ φ 10) φ φ 20) φ 1L φ RB φ CLB Symbol t11 t12 t13, t14 t15, t16 Notes 1. Input the ...

Page 10

φ φ φ φ 1, φ φ φ φ 2 and φ φ φ φ 10, φ φ φ φ 20 cross points φ 1 φ 2 φ 10 φ 20 φ φ φ φ 1L, φ φ φ φ ...

Page 11

TIMING CHART 4 (Line clamp mode, for each color) φ φ TG1- TG3 φ φ 10) φ φ 20) φ 1L φ RB φ CLB Note OUT OUT ...

Page 12

TIMING CHART 5 (Line clamp mode, for each color) φ φ 10) 10% 90% φ φ 20) φ 1L 10% φ RB "H" φ CLB OUT OUT Symbol t1, t2 t1’, ...

Page 13

TIMING CHART 6 (Line clamp mode, for each color) φ φ TG1 to TG3 φ φ 10) φ φ 20) 90% φ 1L φ RB φ CLB Symbol t12 t13, t14 t15, t16 t17, t18 t19 ...

Page 14

DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : V sat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage ...

Page 15

Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : ...

Page 16

Register imbalance : RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. This is calculated by the following formula. n ...

Page 17

STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC 0.5 0.25 0 Operating Ambient Temperature T TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter 100 ...

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APPLICATION CIRCUIT EXAMPLE + µ µ 10 F/ Ω φ Ω 2 Ω 2 Ω φ Ω Caution Connect the No connection pins (NC) to GND. 18 µ PD3728DZ ...

Page 19

Remarks 1. Pin 9 ( φ 10) and pin 28 ( φ 20) should be open to decrease the influence of input clock noise to output signal waveform, in case of operating at low or middle speed range; data rate ...

Page 20

PACKAGE DRAWING CCD LINEAR IMAGE SENSOR 36-PIN CERAMIC DIP (15.24 mm (600)) 94.00±0.7 46.00±0.5 1.00±0.08 1 35.00±0.6 The 1st valid pixel index mark 24.13±0.2 20.32±0.13 48.26±0.4 20 3.00±0.08 11.00±0.15 1.00 (6.00) 2.8±0.08 1.27 2.54 0.46±0.05 20.32±0.13 1.00±0.2 4.00±0.2 Name Dimensions ...

Page 21

RECOMMENDED SOLDERING CONDITIONS When soldering this product highly recommended to observe the conditions as shown below. If other soldering processes are used the soldering is performed under different conditions, please make sure to consult with our ...

Page 22

NOTES ON HANDLING THE PACKAGES 1 MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when ...

Page 23

NOTES ON HANDLING THE PACKAGES 3 OPERATE AND STORAGE ENVIRONMENTS Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So ...

Page 24

Data Sheet S15417EJ2V0DS µ µ µ µ PD3728DZ ...

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Data Sheet S15417EJ2V0DS µ µ µ µ PD3728DZ 25 ...

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Data Sheet S15417EJ2V0DS µ µ µ µ PD3728DZ ...

Page 27

NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...

Page 28

The information in this document is current as of October, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date ...

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