MAX191BCNG Maxim Integrated Products, MAX191BCNG Datasheet
MAX191BCNG
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MAX191BCNG Summary of contents
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... Built-In Track/Hold Internal Reference with Adjustment Capability Low Power: 3mA Operating Mode 100ksps Tested Sampling Rate Serial and 8-Bit Parallel µP Interface supply current to 24-Pin Narrow DIP and Wide SO Packages DD PART MAX191ACNG MAX191BCNG MAX191ACWG MAX191BCWG TM serial- MAX191BC/D MAX191AENG MAX191BENG MAX191AEWG MAX191BEWG ...
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Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down ABSOLUTE MAXIMUM RATINGS V to DGND............................................................-0. AGND ............................................................-7V to +0. ..............................................................................12V DD SS AGND, VREF, REFADJ to DGND................-0. ...
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Internal Reference and Power-Down ELECTRICAL CHARACTERISTICS (continued ±5 -5V ±5 mode, reference compensation mode—external, synchronous operation, Figure 6, T PARAMETER SYMBOL ANALOG INPUT Input Voltage Range (Note 7) Input ...
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Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down ELECTRICAL CHARACTERISTICS (continued ±5 -5V ±5 CLK mode, reference compensation mode—external, synchronous operation, Figure 6, T PARAMETER SYMBOL LOGIC OUTPUTS Output ...
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Internal Reference and Power-Down TIMING CHARACTERISTICS (Figures 6–10) (continued) (V =5V ±5 -5V ±5 PARAMETER SYMBOL Hold Time Setup Time ...
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Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down __________________________________________Typical Operating Characteristics CLOCK FREQUENCY vs. TIMING CAPACITOR 10 SEE FIGURE +25˚ 0.1 0.01 0 TIMING CAPACITOR (nF) POSITIVE SUPPLY CURRENT vs. TEMPERATURE 3.5 ...
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Internal Reference and Power-Down PIN NAME Power-Down Input. A logic low at PD deactivates the ADC—only the bandgap reference is active. A logic PD 1 high selects normal operation, internal-reference compensation mode. An open-circuit condition selects normal operation, external-reference ...
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Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down DGND a. High and High Figure 1. Load Circuits for Access Time DN 10pF 3k DGND ...
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Internal Reference and Power-Down AIN + TRACK C HOLD HOLD 32pF SWITCH PACKAGE 10pF 5pF HOLD AIN - 12-BIT DAC Figure 4. Equivalent Input Circuit various interface modes. The time required for the T/H to acquire ...
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Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down CLK BUSY t 2 CS, RD, and CLK Synchronous Operation Figure 6. between 45% and 55%. Clock and Control Synchronization For best ...
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Internal Reference and Power-Down HBEN CONV 2 BUSY t 3 OLD DATA DATA D7– HOLD* TRACK *INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = ...
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Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down HBEN t 8 CLK BUSY t 3 OLD DATA DATA D7– HOLD* TRACK *INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = ...
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Internal Reference and Power-Down Table 1. Data-Bus Output, PIN NAME D7/DOUT HBEN = 0, PAR = 1, D7 PARALLEL MODE HBEN = 1, PAR = 1, Low PARALLEL MODE HBEN = X, PAR = 0, DOUT SERIAL MODE, RD ...
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Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down 23 SCLK DOUT RD MAX191 SCLK OUT HBEN SSTRB LOGIC INPUT CS SCLK SCLK OUT DOUT SSTRB NOTE: USE SSTRB TO GATE PARALLEL DATA TRANSFER FROM SHIFT REGISTER, ...
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Internal Reference and Power-Down ing edge of the first clock cycle after conversion end (when BUSY goes high). As mentioned previously, two more read operations (after BUSY goes high) are needed to access the conversion results. The only dif- ...
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Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down f (MAX) = (1/ SCLK where t (M) is the minimum data-setup time re- su quired at the serial data input to the µP. For example, Motorola’s ...
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Internal Reference and Power-Down SCLK CS HIGH-Z DOUT MSB a. CPOL = 0, CPHA = 0 SCLK CS HIGH-Z DOUT MSB D10 b. CPOL = 1, CPHA = 1 Figure 15. QSPI Serial-Interface Timing SCLK CLKR CS HIGH-Z SSTRB ...
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Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down Following the data transfer, the DSP receive shift regis- ter (RSR) contains a 16-bit word consisting of the 12 data bits, MSB first, followed by four trailing 0s. Applications Information Power-On ...
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Internal Reference and Power-Down VREF Figure 18b. Low Average-Power Mode Operation (Internal Compensation) which can be achieved using power-down between conversions. External Compensation Figure 19a shows the connection for ...
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Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down OPEN CIRCUIT (FLOAT VREF 2ms 200ms 12 Figure 19b. Low Average-Power Mode Operation (External Compensation) between FFE (hex) and FFF (hex). Because interaction occurs between adjustments, offset ...
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Internal Reference and Power-Down R7 10k MAX480 10k R1 10k R2 100 VREF R3 R5 10k 10k R6 10k R4 49.9 VREF R9* 20k R10* 0.1 F* 49.9 * CONNECT AIN- TO AGND WHEN USING DUAL ...
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Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down 0.01µF and 10µF bypass capacitors. Minimize capaci- tor lead lengths for best supply-noise rejection. If the +5V power supply is very noisy, a 10Ω resistor can be connected as a lowpass ...
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Internal Reference and Power-Down TTL/CMOS IC OUTPUTS 1 MAX250 SHDN 4 3 TTL/CMOS INPUTS GND 8 7 Figure 24. Isolated Data-Acquisition Circuit ______________________________________________________________________________________ Low-Power, ...
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Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down ___________________Chip Topography VREF REFADJ AGND BIP 0.142" (3.6065mm) SUBSTRATE CONNECTED ________________________________________________________Package Information 24 ______________________________________________________________________________________ HBEN CS RD 0.198" (5.0292mm) D7/DOUT D6/SCLK OUT ...