PLDC20G10-35PC Cypress Semiconductor Corporation., PLDC20G10-35PC Datasheet

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PLDC20G10-35PC

Manufacturer Part Number
PLDC20G10-35PC
Description
CMOS Generic 24-Pin Reprogrammable Logic Device
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Cypress Semiconductor Corporation
Document #: 38-03010 Rev. *A
Features
Note:
1. The CG7C323 is the PLDC20G10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The
• Fast
• Low power
• Commercial and military temperature range
• User-programmable output cells
• Generic architecture to replace standard logic
• Eight product terms and one OE product term per output
— Commercial: t
— Military: t
— I
— I
— Selectable for registered or combinatorial operation
— Output polarity control
— Output enable source selectable from pin 13 or
functions including: 20L10, 20L8, 20R8, 20R6, 20R4,
12L10, 14L8, 16L6, 18L4, 20L2, and 20V8
difference is in the location of the “no connect” or NC pins.
product term
Logic Block Diagram
CC
CC
Pin Configurations
I/OE
V
13
12
SS
max.: 70 mA, commercial
max.: 100 mA, military
NC
I
I
I
I
I
I
PD
5
6
7
8
9
10
11
OUTPUT
I/O
14
11
I
12131415161718
= 20 ns, t
4 3 2
CELL
PLDC20G10B
9
8
PLDC20G10
PD
Top View
LCC
1
= 15 ns, t
282726
OUTPUT
I/O
15
10
CO
I
CELL
8
8
25
24
23
22
21
20
19
= 15 ns, t
CO
NC
I/O
I/O
I/O
I/O
I/O
I/O
4
5
2
3
6
7
= 10 ns, t
OUTPUT
I/O
16
9
I
CELL
8
7
S
= 15 ns
CMOS Generic 24-Pin Reprogrammable
S
OUTPUT
I/O
17
8
I
3901 North First Street
CELL
= 12 ns
8
6
NC
NC
NC
USE ULTRA37000™ FOR
ALL NEW DESIGNS
I
I
I
I
5
6
7
8
9
10
11
121314 1516 1718
4 3 2
OUTPUT
I/O
7
PLDC20G10B
I
18
PLDC20G10
CELL
STD PLCC
5
PROGRAMMABLE
8
Top View
AND ARRAY
1
2827 26
Functional Description
Cypress PLD devices are high-speed electrically program-
mable logic devices. These devices utilize the sum-of-products
(AND-OR) structure providing users the ability to program
custom logic functions for unique requirements.
In an unprogrammed state the AND gates are connected via
EPROM cells to both the true and complement of every input.
By selectively programming the EPROM cells, AND gates may
be connected to either the true or complement or disconnected
from both true and complement inputs.
OUTPUT
• CMOS EPROM technology for reprogrammability
• Highly reliable
I/O
19
6
I
CELL
— Uses proven EPROM technology
— Fully AC and DC tested
— Security feature prevents logic pattern duplication
— ±10% power supply voltage and higher noise
25
24
23
22
21
20
19
8
4
immunity
I/O
I/O
I/O
I/O
I/O
I/O
NC
3
5
7
2
4
6
OUTPUT
I/O
5
I
20
CELL
3
8
San Jose
OUTPUT
I/O
NC
21
4
I
CELL
I
I
I
I
I
I
2
8
,
5
6
7
8
9
10
11
CA 95134
121314 1516 1718
4 3 2
JEDEC PLCC
CG7C323B–A
CG7C323–A
OUTPUT
I/O
22
3
Top View
I
CELL
8
1
1
2827 26
Logic Device
Revised April 20, 2004
PLDC20G10B
OUTPUT
I/O
25
24
23
22
21
20
19
23
2
I
CELL
PLDC20G10
[1]
8
0
I/O
I/O
I/O
NC
I/O
I/O
I/O
408-943-2600
2
3
4
5
6
7
CP/I
V
24
1
CC

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PLDC20G10-35PC Summary of contents

Page 1

... I/O 7 12131415161718 Note: 1. The CG7C323 is the PLDC20G10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The difference is in the location of the “no connect” pins. Cypress Semiconductor Corporation Document #: 38-03010 Rev. *A USE ULTRA37000™ FOR ...

Page 2

... Preload is important for testing the functionality of the Cypress PLD device. 20G10 Functional Description The PLDC20G10 is a generic 24-pin device that can be programmed to logic functions that include but are not limited to: 20L10, 20L8, 20R8, 20R6, 20R4, 12L10, 14L8, 16L6, 18L4, 20L2, and 20V8 ...

Page 3

... Product Term OE/Registered/Active HIGH 0 Product Term OE/Combinatorial/Active LOW 1 Product Term OE/Combinatorial/Active HIGH 0 Pin 13 OE/Registered/Active LOW 1 Pin 13 OE/Registered/Active HIGH 0 Pin 13 OE/Combinatorial/Active LOW 1 Pin 13 OE/Combinatorial/Active HIGH Figure 2. Product Term OE/Active HIGH PLDC20G10B PLDC20G10 OUTPUT ENABLE MUX C 2 PIN 13 Configuration Figure 4. Pin 13 OE/Active HIGH ...

Page 4

... PIN 13 Figure 7. Pin 13 OE/Active Low Note: 2. Bidirectional I/O configurations are possible only when the combinatorial output option is selected Document #: 38-03010 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS [ Figure 6. Product Term OE/Active HIGH Figure 8. Pin 13 OE/Active HIGH PLDC20G10B PLDC20G10 PIN 13 Page ...

Page 5

... Tested initially and after any design or process changes that may affect these parameters. Document #: 38-03010 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS DC Programming Voltage PLDC20G10B and CG7C323B–A ............................... 13.0V PLDC20G10 and CG7C323–A.................................... 14.0V Latch-Up Current ..................................................... >200 mA Static Discharge Voltage.............................................. >500V (per MIL-STD-883, Method 8015) ...

Page 6

... Min. Max. Min. Max. Min. Max. Min. Max 45.4 [ B–20 Min. Max. Min. Max. Min. Max. Min. Max and t ER PZX PXZ + PLDC20G10B PLDC20G10 R1 238Ω (319Ω MIL) R2 170Ω (236Ω MIL) (b) 136 Ω OUTPUT 2.13V=V Commercial B–20 – ...

Page 7

... REGISTERED FEEDBACK REGISTERED OUTPUTS COMBINATORIAL OUTPUTS Document #: 38-03010 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS [ B–20 Min. Max. Min. Max. Min. Max. Min. Max 33 PXZ PLDC20G10B PLDC20G10 Military/Industrial B–25 –30 – 30.3 25.0 16.6 t PZX t ER Page Unit MHz t EA ...

Page 8

... OE 0 • • • • • • Document #: 38-03010 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 OUTPUT CELL 23 OUTPUT CELL 22 OUTPUT CELL 21 OUTPUT CELL 20 OUTPUT CELL 19 OUTPUT CELL 18 OUTPUT CELL 17 OUTPUT CELL 16 OUTPUT CELL 15 OUTPUT CELL ...

Page 9

... Ordering Information (ns) (ns) (ns) (mA) Ordering Code PLDC20G10B–15PC PLDC20G10B–15WC 100 PLDC20G10B–20DMB PLDC20G10–25JC PLDC20G10–25PC/PI PLDC20G10–25WC PLDC20G10–30DMB PLDC20G10–30LMB PLDC20G10–30WMB PLDC20G10–35JC PLDC20G10–35PC MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Document #: 38-03010 Rev. *A USE ULTRA37000™ FOR ...

Page 10

... Package Diagrams Document #: 38-03010 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D- 9 Config.A 28-Lead Plastic Leaded Chip Carrier J64 PLDC20G10B PLDC20G10 51-80031-** 51-85001-*A Page ...

Page 11

... Package Diagrams (continued) Document #: 38-03010 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS 28-Square Leadless Chip Carrier L64 MIL-STD-1835 C-4 PLDC20G10B PLDC20G10 51-80051-** Page ...

Page 12

... Package Diagrams (continued) Document #: 38-03010 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS 28-Pin Windowed Leaded Chip Carrier H64 PLDC20G10B PLDC20G10 51-80077-** Page ...

Page 13

... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. USE ULTRA37000™ FOR ALL NEW DESIGNS 24-Lead (300-Mil) PDIP P13 24-Lead (300-Mil) Windowed CerDIP W14 MIL-STD-1835 D-9 Config. A PLDC20G10B PLDC20G10 51-85013-*B 51-80086-** Page ...

Page 14

... Document History Page Document Title: PLDC20G10B/PLDC20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Document Number: 38-03010 REV. ECN NO. Issue Date ** 106292 04/25/01 *A 213375 See ECN Document #: 38-03010 Rev. *A USE ULTRA37000™ FOR ALL NEW DESIGNS Orig. of Change SZV Change from Spec number: 38-00019 to 38-03010 FSG Added note to title page: “ ...

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