LM4855ITL/NOPB National Semiconductor, LM4855ITL/NOPB Datasheet - Page 16

IC AMP AUDIO PWR 1.5W AB 18USMD

LM4855ITL/NOPB

Manufacturer Part Number
LM4855ITL/NOPB
Description
IC AMP AUDIO PWR 1.5W AB 18USMD
Manufacturer
National Semiconductor
Series
Boomer®r
Type
Class ABr
Datasheet

Specifications of LM4855ITL/NOPB

Output Type
1-Channel (Mono) with Stereo Headphones
Max Output Power X Channels @ Load
1.5W x 1 @ 4 Ohms; 115mW x 2 @ 32 Ohms
Voltage - Supply
2.6 V ~ 5 V
Features
Depop, Mute, Shutdown, SPI, Thermal Protection, Volume Control
Mounting Type
Surface Mount
Package / Case
18-MicroSMD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LM4855ITL
LM4855ITLNOPB
LM4855ITLNOPBTR
LM4855ITLNOPBTR
LM4855ITLTR
www.national.com
APPLICATION INFORMATION
SPI OPERATIONAL REQUIREMENTS
1. The data bits are transmitted with the LSB first.
2. The maximum clock rate is 10MHz for the CLK pin.
3. CLK must remain logic-high for at least 50ns (t
the rising edge of CLK, and CLK must remain logic-low for at
least 50ns (t
4. The serial data bits are sampled at the rising edge of CLK.
Any transition on DATA must occur at least 20ns (t
the rising edge of CLK. Also, any transition on DATA must
occur at least 20ns (t
stabilize before the next rising edge of CLK.
5. ENB should be logic-high only during serial data transmis-
sion.
EXPOSED-DAP MOUNTING CONSIDERATIONS
The LM4855’s exposed-DAP (die attach paddle) package
(LD) provides a low thermal resistance between the die and
the PCB to which the part is mounted and soldered. This
allows rapid heat transfer from the die to the surrounding
PCB copper area heatsink, copper traces, ground plane, and
finally, surrounding air. The result is a low voltage audio
power amplifier that produces 1.1W dissipation in a 8Ω load
at ≤ 1% THD+N. This high power is achieved through careful
consideration of necessary thermal design. Failing to opti-
mize thermal design may compromise the LM4855’s high
power performance and activate unwanted, though neces-
sary, thermal shutdown protection.
The LD package must have its DAP soldered to a copper
pad on the PCB. The DAP’s PCB copper pad is then, ideally,
connected to a large plane of continuous unbroken copper.
This plane forms a thermal mass, heat sink, and radiation
area. Place the heat sink area on either outside plane in the
case of a two-sided or multi-layer PCB. (The heat sink area
can also be placed on an inner layer of a multi-layer board.
The thermal resistance, however, will be higher.) Connect
the DAP copper pad to the inner layer or backside copper
heat sink area with 6 (3 X 2) (LD) vias. The via diameter
should be 0.012in - 0.013in with a 1.27mm pitch. Ensure
efficient thermal conductivity by plugging and tenting the vias
with plating and solder mask, respectively.
Best thermal performance is achieved with the largest prac-
tical copper heat sink area. If the heatsink and amplifier
(Continued)
CL
) after the falling edge of CLK.
DH
) after the rising edge of CLK and
FIGURE 2. SPI Timing Diagram
DS
CH
) before
) after
16
6. ENB must be logic-high at least 20ns (t
rising edge of CLK, and ENB has to remain logic-high at
least 20ns (t
7. If ENB remains logic-low for more than 10ns before all 8
bits are transmitted then the data latch will be aborted.
8. If ENB is logic-high for more than 8 CLK pulses then only
the first 8 data bits will be latched and activated when ENB
transitions to logic-low.
9. ENB must remain logic-low for at least 30ns (t
in the data.
10. Coincidental rising or falling edges of CLK and ENB are
not allowed. If CLK is to be held logic-high after the data
transmission, the falling edge of CLK must occur at least
20ns (t
set of data.
share the same PCB layer, a nominal 2.5in
necessary for 5V operation with a 4Ω load. Heatsink areas
not placed on the same PCB layer as the LM4855 should be
5in
The last two area recommendations apply for 25˚C ambient
temperature. Increase the area to compensate for ambient
temperatures above 25˚C. In all circumstances and under all
conditions, the junction temperature must be held below
150˚C to prevent activating the LM4855’s thermal shutdown
protection. Further detailed and specific information con-
cerning PCB layout and fabrication and mounting an LD
(LLP) is found in National Semiconductor’s AN1187.
PCB LAYOUT AND SUPPLY REGULATION
CONSIDERATIONS FOR DRIVING 3Ω AND 4Ω LOADS
Power dissipated by a load is a function of the voltage swing
across the load and the load’s impedance. As load imped-
ance decreases, load dissipation becomes increasingly de-
pendent on the interconnect (PCB trace and wire) resistance
between the amplifier output pins and the load’s connec-
tions. Residual trace resistance causes a voltage drop,
which results in power dissipated in the trace and not in the
load as desired. For example, 0.1Ω trace resistance reduces
the output power dissipated by a 4Ω load from 1.7W to 1.6W.
The problem of decreased load dissipation is exacerbated
as load impedance decreases. Therefore, to maintain the
2
(min) for the same supply voltage and load resistance.
CS
) before ENB transitions to logic-high for the next
EH
) after the eighth rising edge of CLK.
200395D2
ES
) before the first
2
(min) area is
EL
) to latch

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