UPD8872CY NEC, UPD8872CY Datasheet

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UPD8872CY

Manufacturer Part Number
UPD8872CY
Description
(5400 + 5400) PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR
Manufacturer
NEC
Datasheet

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Document No. S15330EJ3V0DS00 (3rd edition)
Date Published July 2003 NS CP (K)
Printed in Japan
DESCRIPTION
electrical signal and has the function of color separation.
transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for
1200 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
• Valid photocell
• Photocell pitch
• Line spacing
• Color filter
• Resolution
• Drive clock level : CMOS output under 5 V operation
• Data rate
• Power supply
• On-chip circuits : Reset feed-through level clamp circuits
ORDERING INFORMATION
µ
The
The
Part Number
PD8872CY
µ
µ
PD8872 has 3 rows of (5400 + 5400) staggered pixels, and each row has a dual-sided readout-type charge
PD8872 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
(5400 + 5400) PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
: (5400 + 5400) staggered pixels × 3
: 5.25
: 63
: Primary colors (red, green and blue), pigment filter (with light resistance 10
: 48 dot/mm A4 (210 × 297 mm) size (shorter side)
: 10 MHz Max.
: +12 V
10.5
1200 dpi US letter (8.5” × 11”) size (shorter side)
Voltage amplifiers
µ
m (12 lines) Red line - Green line, Green line - Blue line
µ
µ
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
m
m (2 lines) Odd line - Even line (for each color)
The mark
DATA SHEET
shows major revised points.
Package
MOS INTEGRATED CIRCUIT
µ
PD8872
7
lx•hour)

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UPD8872CY Summary of contents

Page 1

... The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S15330EJ3V0DS00 (3rd edition) ...

Page 2

BLOCK DIAGRAM φ GND GND OUT 20 (Blue OUT 21 (Green OUT 22 (Red φ φ φ CLB 2 CCD analog shift ...

Page 3

... Reset feed-through level clamp clock CLB φ Last stage shift register clock 1 No connection NC No connection NC No connection NC Shift register clock 2 Shift register clock 1 Transfer gate clock 3 φ TG3 (for Red) Ground GND Caution Connect the No connection pins (NC) to GND OUT OUT OUT φ 1L ...

Page 4

PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing) 5.25 µ m 5.25 µ m 5.25 µ m 5.25 µ m Green photocell array 5.25 µ m 5.25 µ m 5.25 µ m 5.25 µ m 5.25 µ ...

Page 5

ABSOLUTE MAXIMUM RATINGS (T Parameter Output drain voltage V OD Shift register clock voltage φ 1 Reset gate clock voltage V φ RB Reset feed-through level clamp clock V φ CLB voltage Transfer gate clock voltage V ...

Page 6

ELECTRICAL CHARACTERISTICS = +25° data rate ( MHz, storage time = 5.5 ms, input signal clock = 5 V φ light source : 3200 K halogen lamp + C-500S ...

Page 7

... C CLB 3 φ CLB φ − C TG1 13 φ TG φ − TG2 12 φ − TG3 10 φ 2) are each connected inside of the device. Data Sheet S15330EJ3V0DS µ PD8872 Typ. Max. Unit − 500 pF − 500 pF − 1000 pF − 500 pF − 500 pF − ...

Page 8

TIMING CHART 1-1 (Bit clamp mode, for each color) φ φ TG1 to TG3 φ φ φ φ φ RB Note φ CLB OUT OUT φ φ Note Set the RB ...

Page 9

TIMING CHART 1-2 (Line clamp mode, for each color) φ φ TG1 to TG3 φ φ φ φ φ RB Note φ CLB φ φ ( TG1 to TG3 OUT OUT ...

Page 10

TIMING CHART 2 (Bit clamp mode, for each color) φ 1 φ 2 φ 1L φ 90% φ 90% φ CLB 10% RFTN RFTN V OUT Symbol t1, t2 t1’, ...

Page 11

TIMING CHART 3 (Line clamp mode, for each color) φ 1 φ 2 φ 1L φ 90% φ RB 10% "H" φ CLB RFTN RFTN V OUT Symbol t1, t2 t1’, t2’ t5, ...

Page 12

TG1 to TG3 TIMING CHART φ φ TG1 to TG3 φ 1 φ 2 φ RB φ CLB (Bit clamp mode) φ CLB (Line clamp mode) Symbol t7 t9, t10 t12 t13, t14 t15, ...

Page 13

Remark Adjust cross points ( 1, 2), ( ...

Page 14

DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : V sat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage ...

Page 15

Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : ...

Page 16

Register imbalance: RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels ∑ – ...

Page 17

STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC 0.5 0.25 0 Operating Ambient Temperature T TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (T 100 B ...

Page 18

... Caution Connect the No connection pins (NC) to GND. Remarks 1. The inverters shown in the above application circuit example are the 74HC04 (data rate < 2 MHz) or the 74AC04 (2 ≤ data rate < 10 MHz). 2. Inverters the above application circuit example are shown in the figure below. ...

Page 19

PACKAGE DRAWING µ PD8872CY CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400) ) (Unit : mm) 44.0±0.3 1st valid pixel 1 0.5±0 37.5 1.02±0.15 0.46±0.1 2.54±0.25 9.25±0 2.0 (1.79) 4.39±0.4 2.55±0.2 (5.42) 4.21±0.5 Name ...

Page 20

RECOMMENDED SOLDERING CONDITIONS When soldering this product highly recommended to observe the conditions as shown below. If other soldering processes are used the soldering is performed under different conditions, please make sure to consult with our ...

Page 21

... Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 MΩ. Data Sheet S15330EJ3V0DS µ ...

Page 22

Data Sheet S15330EJ3V0DS µ PD8872 ...

Page 23

... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...

Page 24

... NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • ...

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