UPD3728DZ NEC, UPD3728DZ Datasheet
UPD3728DZ
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UPD3728DZ Summary of contents
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... CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S15417EJ2V0DS00 (2nd edition) ...
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BLOCK DIAGRAM φ φ CLB GND V 2 OUT 32 (Blue, even) GND OUT 34 (Blue, odd) GND OUT 36 (Green, odd OUT 1 (Green, even) GND 2 ...
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... Reset gate clock Shift register clock 10 No connection No connection No connection Shift register clock 1 Shift register clock 2 φ Transfer gate clock 3 (for Red) Ground No connection No connection Caution Connect the No connection pins (NC) to GND. PHOTOCELL STRUCTURE DIAGRAM µ m µ Channel stopper Aluminum shield ...
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ABSOLUTE MAXIMUM RATINGS (T Parameter Output drain voltage Shift register clock voltage Reset gate clock voltage Reset feed-through level clamp clock voltage Transfer gate clock voltage Note Operating ambient temperature Storage temperature Note Use at the condition without dew condensation. ...
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ELECTRICAL CHARACTERISTICS = +25° MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 V φ light source: 3200 K halogen lamp +C-500S ...
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... Reset gate clock pin capacitance Reset feed-through level clamp clock pin capacitance Transfer gate clock pin capacitance Remark Pins 13 φ 1) and pin 9 ( φ 10) are connected each other inside of the device. Pins 14 φ 2) and pin 28 ( φ 20) are connected each other inside of the device. 6 ...
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TIMING CHART 1 (Bit clamp mode, for each color) φ φ TG1 to TG3 φ φ 10) φ φ 20) φ 1L φ RB φ CLB Note OUT ...
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TIMING CHART 2 (Bit clamp mode, for each color) φ φ 10) φ φ 20) φ 1L φ RB φ CLB OUT OUT Symbol t1, t2 t1’, t2’ t5, ...
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TIMING CHART 3 (Bit clamp, for each color) φ φ TG1 to TG3 φ φ 10) φ φ 20) φ 1L φ RB φ CLB Symbol t11 t12 t13, t14 t15, t16 Notes 1. Input the ...
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φ φ φ φ 1, φ φ φ φ 2 and φ φ φ φ 10, φ φ φ φ 20 cross points φ 1 φ 2 φ 10 φ 20 φ φ φ φ 1L, φ φ φ φ ...
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TIMING CHART 4 (Line clamp mode, for each color) φ φ TG1- TG3 φ φ 10) φ φ 20) φ 1L φ RB φ CLB Note OUT OUT ...
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TIMING CHART 5 (Line clamp mode, for each color) φ φ 10) 10% 90% φ φ 20) φ 1L 10% φ RB "H" φ CLB OUT OUT Symbol t1, t2 t1’, ...
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TIMING CHART 6 (Line clamp mode, for each color) φ φ TG1 to TG3 φ φ 10) φ φ 20) 90% φ 1L φ RB φ CLB Symbol t12 t13, t14 t15, t16 t17, t18 t19 ...
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DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : V sat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage ...
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Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : ...
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Register imbalance : RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. This is calculated by the following formula. n ...
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STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC 0.5 0.25 0 Operating Ambient Temperature T TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter 100 ...
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... APPLICATION CIRCUIT EXAMPLE + µ µ 10 F/ Ω φ Ω 2 Ω 2 Ω φ Ω Caution Connect the No connection pins (NC) to GND. 18 µ PD3728DZ OUT OUT 2 35 GND GND OUT OUT 4 33 GND GND OUT OUT 6 31 GND GND 47 Ω φ V CLB OD 47 Ω ...
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Remarks 1. Pin 9 ( φ 10) and pin 28 ( φ 20) should be open to decrease the influence of input clock noise to output signal waveform, in case of operating at low or middle speed range; data rate ...
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PACKAGE DRAWING CCD LINEAR IMAGE SENSOR 36-PIN CERAMIC DIP (15.24 mm (600)) 94.00±0.7 46.00±0.5 1.00±0.08 1 35.00±0.6 The 1st valid pixel index mark 24.13±0.2 20.32±0.13 48.26±0.4 20 3.00±0.08 11.00±0.15 1.00 (6.00) 2.8±0.08 1.27 2.54 0.46±0.05 20.32±0.13 1.00±0.2 4.00±0.2 Name Dimensions ...
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RECOMMENDED SOLDERING CONDITIONS When soldering this product highly recommended to observe the conditions as shown below. If other soldering processes are used the soldering is performed under different conditions, please make sure to consult with our ...
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NOTES ON HANDLING THE PACKAGES 1 MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when ...
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... Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 MΩ. Data Sheet S15417EJ2V0DS µ ...
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Data Sheet S15417EJ2V0DS µ µ µ µ PD3728DZ ...
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Data Sheet S15417EJ2V0DS µ µ µ µ PD3728DZ 25 ...
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Data Sheet S15417EJ2V0DS µ µ µ µ PD3728DZ ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • ...