24C16 STMicroelectronics, 24C16 Datasheet

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24C16

Manufacturer Part Number
24C16
Description
24C1616 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection
Manufacturer
STMicroelectronics
Datasheet

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DESCRIPTION
This specification covers a range of 16 Kbit I
EEPROM products, the ST24/25C16 and the
ST24/25W16. In the text, products are referred to
as ST24/25x16 where "x" is: "C" for Standard ver-
sion and "W" for hardware Write Control version.
The ST24/25x16 are 16 Kbit electrically erasable
programmable memories (EEPROM), organized
as 8 blocks of 256 x8 bits. These are manufactured
in STMicroelectronics’s Hi-Endurance Advanced
CMOS technology which guarantees an endur-
Table 1. Signal Names
February 1999
PRE
PB0, PB1
SDA
SCL
MODE
WC
V
V
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
– 4.5V to 5.5V for ST24x16 versions
– 2.5V to 5.5V for ST25x16 versions
HARDWARE WRITE CONTROL VERSIONS:
ST24W16 and ST25W16
TWO WIRE SERIAL INTERFACE, FULLY I
BUS COMPATIBLE
BYTE and MULTIBYTE WRITE (up to 8
BYTES) for the ST24C16
PAGE WRITE (up to 16 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
CC
SS
Write Protect Enable
Protect Block Select
Serial Data Address Input/Output
Serial Clock
Multybyte/Page Write Mode
(C version)
Write Control (W version)
Supply Voltage
Ground
with User-Defined Block Write Protection
2
C bus
2
C
16 Kbit Serial I
Figure 1. Logic Diagram
Note: WC signal is only available for ST24/25W16 products.
MODE/WC*
PB0-PB1
0.25mm Frame
ST24W16, ST25W16
PSDIP8 (B)
8
ST24C16, ST25C16
PRE
SCL
1
2
2
V CC
C Bus EEPROM
V SS
ST24x16
ST25x16
150mil Width
SO8 (M)
8
1
AI00866B
SDA
1/17

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24C16 Summary of contents

Page 1

... ST25x16 versions HARDWARE WRITE CONTROL VERSIONS: ST24W16 and ST25W16 TWO WIRE SERIAL INTERFACE, FULLY I BUS COMPATIBLE BYTE and MULTIBYTE WRITE ( BYTES) for the ST24C16 PAGE WRITE ( BYTES) BYTE, RANDOM and SEQUENTIAL READ MODES SELF TIMED PROGRAMING CYCLE AUTOMATIC ADDRESS INCREMENTING ...

Page 2

... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. ...

Page 3

Table 3. Device Select Code Bit b7 Device Select 1 Note: The MSB b7 is sent first. Table 4. Operating Modes Mode RW bit Current Address Read Random Address Read Sequential Read Byte Write Multibyte Write Page Write Note: X ...

Page 4

ST24/25C16, ST24/25W16 SIGNALS DESCRIPTION Serial Clock (SCL). The SCL input signal is used to synchronise all data in and out of the memory. A resistor can be connected from the SCL line act as a pull up ...

Page 5

Table 5. Input Parameters Symbol C Input Capacitance (SDA Input Capacitance (other pins Input Impedance (ST24/25W16) WCL Z WC Input Impedance (ST24/25W16) WCH Low-pass filter input time constant t LP (SDA and SCL) Note: ...

Page 6

ST24/25C16, ST24/25W16 Table 7. AC Characteristics ( – Symbol Alt t t Clock Rise Time CH1CH2 Clock Fall Time CL1CL2 Input Rise Time ...

Page 7

Figure 5. AC Waveforms SCL SDA IN START CONDITION SCL tCLQV SDA OUT SCL SDA IN tCHDH STOP CONDITION tCHCL tDLCL tCHDX tCLDX SDA SDA INPUT CHANGE tCLQX DATA VALID DATA OUTPUT tW WRITE CYCLE ST24/25C16, ST24/25W16 tCLCH tDXCX tCHDH ...

Page 8

ST24/25C16, ST24/25W16 2 Figure Bus Protocol SCL SDA START CONDITION SCL MSB SDA START CONDITION 1 SCL MSB SDA Stop Condition. STOP is identified by a low to high transition of the SDA line while the clock ...

Page 9

Figure 7. Memory Protection 7FFh 700h 600h 500h 400h Write Operations The Multibyte Write mode (only available on the ST24/25C16 versions) is selected when the MODE pin and the Page Write mode when MODE IH pin is ...

Page 10

ST24/25C16, ST24/25W16 Page Write. For the Page Write mode, the MODE pin must The Page Write mode allows bytes to be written in a single write cycle, provided that they are all ...

Page 11

Write Protection. Data in the upper four blocks of 256 bytes of the memory may be write protected. The memory is write protected between a boundary address and the top of memory (address 7FFh).The boundary address is user defined by ...

Page 12

ST24/25C16, ST24/25W16 Figure 10. Write Modes Sequence with Write Control = 1 (ST24/25W16) WC BYTE WRITE WC PAGE WRITE WC (cont'd) PAGE WRITE (cont'd) Read Operation Read operations are independent of the state of the MODE signal. On delivery, the ...

Page 13

Figure 11. Read Modes Sequence CURRENT ADDRESS READ RANDOM ADDRESS READ SEQUENTIAL CURRENT READ SEQUENTIAL RANDOM READ Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical. ...

Page 14

... Devices are shipped from the factory with the memory content set at all "1’s" (FFh). For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 14/17 ST24C16 Package ...

Page 15

PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame Symb Typ 7. 2. Drawing is not to scale. mm Min Max 3.90 ...

Page 16

ST24/25C16, ST24/25W16 SO8 - 8 lead Plastic Small Outline, 150 mils body width Symb Typ 1. SO-a Drawing is not to scale. 16/17 ...

Page 17

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...

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