74F373 Fairchild Semiconductor, 74F373 Datasheet

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74F373

Manufacturer Part Number
74F373
Description
Octal transparent latch 3-State 74F373Octal Transparent Latch with TRI-STATE Outputs 74F373Octal Transparent Latch with 3-STATE Outputs
Manufacturer
Fairchild Semiconductor
Datasheet

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© 2000 Fairchild Semiconductor Corporation
74F373SC
74F373SJ
74F373MSA
74F373PC
74F373
Octal Transparent Latch with 3-STATE Outputs
General Description
The 74F373 consists of eight latches with 3-STATE outputs
for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup
times is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Order Number
Package Number
MSA20
IEEE/IEC
M20B
M20D
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS009523
Features
Connection Diagram
Eight latches in a single package
3-STATE outputs for bus interfacing
Guaranteed 4000V minimum ESD protection
Package Description
May 1988
Revised September 2000
www.fairchildsemi.com

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74F373 Summary of contents

Page 1

... Octal Transparent Latch with 3-STATE Outputs General Description The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched ...

Page 2

... O –O 3-STATE Latch Outputs 0 7 Functional Description The 74F373 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the D inputs enters the latches. In this condition n the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the ...

Page 3

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2) Input Current (Note 5.0 mA Voltage Applied to Output in HIGH State ...

Page 4

AC Electrical Characteristics Symbol Parameter t Propagation Delay PLH PHL Propagation Delay PLH PHL n t Output Enable Time PZH t PZL t Output Disable Time PHZ t PLZ ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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