MC68HC705P9CP Freescale Semiconductor, Inc, MC68HC705P9CP Datasheet

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MC68HC705P9CP

Manufacturer Part Number
MC68HC705P9CP
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Freescale Semiconductor, Inc.
MC68HC705P9
Technical Data
M68HC05
Microcontrollers
MC68HC705P9/D
Rev. 4.0, 4/2002
For More Information On This Product,
Go to: www.freescale.com

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MC68HC705P9CP Summary of contents

Page 1

... Freescale Semiconductor, Inc. M68HC05 Microcontrollers For More Information On This Product, Go to: www.freescale.com MC68HC705P9 Technical Data MC68HC705P9/D Rev. 4.0, 4/2002 ...

Page 2

... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

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... Freescale Semiconductor, Inc. MC68HC705P9 Technical Data To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.motorola.com/semiconductors/ The following revision history table summarizes changes contained in this document ...

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... Freescale Semiconductor, Inc. Revision History Revision Date Level April, 2002 4.0 Advance Information 4 Revision History Description Reformatted to meet current publication standards Technical Data For More Information On This Product, Go to: www.freescale.com Page Number(s) Throughout MC68HC908GT16 • MC68HC908GT8 MOTOROLA ...

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... Freescale Semiconductor, Inc. Technical Data — MC68HC705P9 Section 1. General Description . . . . . . . . . . . . . . . . . . . . 21 Section 2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . 25 Section 3. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Section 4. Central Processor Unit (CPU Section 5. Resets and Interrupts . . . . . . . . . . . . . . . . . . . 65 Section 6. Low Power Modes Section 7. Parallel Input/Output (I/O) Ports . . . . . . . . . . 81 Section 8. Computer Operating Properly Section 9. Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Section 10. Serial Input/Output Port (SIOP 117 Section 11 ...

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... Freescale Semiconductor, Inc. List of Sections Technical Data 6 For More Information On This Product, List of Sections Go to: www.freescale.com MC68HC705P9 — Rev. 4.0 MOTOROLA ...

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... Freescale Semiconductor, Inc. Technical Data — MC68HC705P9 1.1 1.2 1.3 1.4 2.1 2.2 2.3 2.3.1 2.3.2 2.3.2.1 2.3.2.2 2.3.2.3 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.3.9 MC68HC705P9 — Rev. 4.0 MOTOROLA For More Information On This Product, Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Programmable Options ...

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... Freescale Semiconductor, Inc. Table of Contents 3.1 3.2 3.3 3.4 3.5 3.6 3.6.1 3.6.1.1 3.6.1.2 3.6.2 3.7 4.1 4.2 4.3 4.4 4.5 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 4.7 4.7.1 4.7.1.1 4.7.1.2 4.7.1.3 Technical Data 8 For More Information On This Product, Section 3. Memory Contents ...

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... Freescale Semiconductor, Inc. 4.7.1.4 4.7.1.5 4.7.1.6 4.7.1.7 4.7.1.8 4.7.2 4.7.2.1 4.7.2.2 4.7.2.3 4.7.2.4 4.7.2.5 4.7.3 4.8 5.1 5.2 5.2.1 5.2.2 5.2.3 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.3.1 5.4.3.2 5.4.3.3 5.4.4 MC68HC705P9 — Rev. 4.0 MOTOROLA For More Information On This Product, Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Indexed, No Offset ...

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... Freescale Semiconductor, Inc. Table of Contents 6.1 6.2 6.3 6.4 7.1 7.2 7.3 7.3.1 7.3.2 7.4 7.4.1 7.4.2 7.5 7.5.1 7.5.2 7.6 7.6.1 7.6.2 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 Technical Data 10 For More Information On This Product, Section 6. Low Power Modes Contents ...

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... Freescale Semiconductor, Inc. 8.5 8.6 8.7 8.7.1 8.7.2 9.1 9.2 9.3 9.4 9.4.1 9.4.1.1 9.4.1.2 9.4.2 9.4.3 9.5 9.6 9.7 9.7.1 9.7.2 9.7.3 9.7.4 9.7.5 9.7.6 9.8 9.8.1 9.8.2 MC68HC705P9 — Rev. 4.0 MOTOROLA For More Information On This Product, Interrupts COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Low-Power Modes ...

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... Freescale Semiconductor, Inc. Table of Contents 10.1 10.2 10.3 10.4 10.4.1 10.4.1.1 10.4.1.2 10.4.1.3 10.4.2 10.5 10.6 10.7 10.7.1 10.7.2 10.7.3 10.8 10.8.1 10.8.2 11.1 11.2 11.3 11.4 11.4.1 11.4.1.1 11.4.1.2 11.5 11.6 Technical Data 12 For More Information On This Product, Section 10. Serial Input/Output Port (SIOP) Contents ...

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... Freescale Semiconductor, Inc. 11.7 11.7.1 11.7.2 11.8 11.8.1 11.8.2 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 Maximum Supply Current vs. Internal Clock Frequency .145 12.11 5.0-Volt Control Timing 12.12 3.3 V Control Timing 13.1 13.2 13.3 13.4 13.5 MC68HC705P9 — Rev. 4.0 ...

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... Freescale Semiconductor, Inc. Table of Contents 14.1 14.2 14.3 Technical Data 14 For More Information On This Product, Section 14. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 Index Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Table of Contents Go to: www.freescale.com MC68HC705P9 — Rev. 4.0 MOTOROLA ...

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... Freescale Semiconductor, Inc. Technical Data — MC68HC705P9 Figure 1-1 2-1 2-2 2-3 2-4 2-5 3-1 3-2 3-3 3-4 3-5 4-1 4-2 4-3 4-4 4-5 4-6 5-1 5-2 5-3 5-4 5-5 5-6 5-7 MC68HC705P9 — Rev. 4.0 MOTOROLA For More Information On This Product, Title MC68HC705P9 Block Diagram ...

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... Freescale Semiconductor, Inc. List of Figures Figure 6-1 6-2 6-3 6-4 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 Port C I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7-11 Port D Data Register (PORTD 7-12 Data Direction Register D (DDRD 7-13 Port D I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8-1 9-1 9-2 9-3 ...

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... Freescale Semiconductor, Inc. Figure 9-16 Input Capture Registers (ICRH and ICRL 114 9-17 Output Compare Registers (OCRH and OCRL 115 10-1 SIOP Block Diagram 119 10-2 SIOP I/O Register Summary 119 10-3 SIOP Data/Clock Timing 121 10-4 Master/Slave SIOP Shift Register Operation . . . . . . . . . . . . . 123 10-5 SIOP Timing ...

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... Freescale Semiconductor, Inc. List of Figures Technical Data 18 For More Information On This Product, List of Figures Go to: www.freescale.com MC68HC705P9 — Rev. 4.0 MOTOROLA ...

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... Freescale Semiconductor, Inc. Technical Data — MC68HC705P9 Table 1-1 3-1 4-1 4-2 4-3 4-4 4-5 4-6 4-7 5-1 5-2 5-3 5-4 7-1 7-2 7-3 7-4 9-1 9-2 9-3 10-1 SIOP Timing (V 10-2 SIOP Timing (V MC68HC705P9 — Rev. 4.0 MOTOROLA For More Information On This Product, Title Programmable Options ...

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... Freescale Semiconductor, Inc. List of Tables Table 11-1 ADC Characteristics (V 11-2 ADC Input Channel Selection . . . . . . . . . . . . . . . . . . . . . . . . . 135 14-1 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Technical Data 20 For More Information On This Product, Title = 5.0 Vdc .133 DD List of Tables Go to: www.freescale.com Page MC68HC705P9 — Rev. 4.0 MOTOROLA ...

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... Freescale Semiconductor, Inc. Technical Data — MC68HC705P9 1.1 Contents 1.2 1.3 1.4 1.2 Features Features of the MC68HC705P9 include: • • • • MC68HC705P9 — Rev. 4.0 MOTOROLA For More Information On This Product, Section 1. General Description Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Programmable Options Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Four peripheral modules – ...

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... Freescale Semiconductor, Inc. General Description • • • • • • 1.3 Programmable Options The options in COP watchdog External interrupt pin triggering SIOP data format Technical Data 22 For More Information On This Product, 128 bytes of user RAM Bootloader ROM Memory-mapped I/O registers ...

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... Freescale Semiconductor, Inc. 1.4 Structure EPROM/OTPROM — 2104 BYTES BOOTLOADER ROM — 240 BYTES RAM — 128 BYTES CPU CONTROL IRQ/V PP M68HC05 MCU RESET RESET STACK POINTER PROGRAM COUNTER OSC1 INTERNAL OSCILLATOR OSC2 COP WATCHDOG V DD POWER V SS Figure 1-1. MC68HC705P9 Block Diagram MC68HC705P9 — ...

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... Freescale Semiconductor, Inc. General Description Technical Data 24 For More Information On This Product, General Description Go to: www.freescale.com MC68HC705P9 — Rev. 4.0 MOTOROLA ...

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... Freescale Semiconductor, Inc. Technical Data — MC68HC705P9 2.1 Contents 2.2 2.3 2.3.1 2.3.2 2.3.2.1 2.3.2.2 2.3.2.3 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.3.9 MC68HC705P9 — Rev. 4.0 MOTOROLA For More Information On This Product, Section 2. Pin Descriptions Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 V and V ...

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... Freescale Semiconductor, Inc. Pin Descriptions 2.2 Pin Assignments 2.3 Pin Functions 2.3.1 V and and V DD from a single 5-V power supply. Very fast signal transitions occur on the MCU pins, placing high short-duration current demands on the power supply. To prevent noise problems, take special ...

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... Freescale Semiconductor, Inc. 2.3.2 OSC1 and OSC2 The OSC1 and OSC2 pins are the connections for the on-chip oscillator. The oscillator can be driven by any of the following: • • • The frequency of the on-chip oscillator is f internal oscillator output by two to produce the internal clock with a frequency ...

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... Freescale Semiconductor, Inc. Pin Descriptions 2.3.2.2 Ceramic Resonator Connections To reduce cost, use a ceramic resonator in place of the crystal. Figure 2-4 resonator circuit. For the values of any external components, follow the recommendations of the resonator manufacturer. The load capacitance values used in the oscillator circuit design should include all stray layout capacitances ...

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... Freescale Semiconductor, Inc. 2.3.4 IRQ/V PP The IRQ/V • • 2.3.5 PA7–PA0 PA7–PA0 are general-purpose bidirectional I/O port pins. Use data direction register A to configure port A pins as inputs or outputs. 2.3.6 PB7/SCK–PB5/SDO Port 3-pin bidirectional I/O port that shares its pins with the SIOP. ...

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... Freescale Semiconductor, Inc. Pin Descriptions Technical Data 30 For More Information On This Product, Pin Descriptions Go to: www.freescale.com MC68HC705P9 — Rev. 4.0 MOTOROLA ...

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... Freescale Semiconductor, Inc. Technical Data — MC68HC705P9 3.1 Contents 3.2 3.3 3.4 3.5 3.6 3.6.1 3.6.1.1 3.6.1.2 3.6.2 3.7 3.2 Features Features include: • • • MC68HC705P9 — Rev. 4.0 MOTOROLA For More Information On This Product, Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Memory Map Input/Output Register Summary . . . . . . . . . . . . . . . . . . . . . . . .33 RAM ...

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... Freescale Semiconductor, Inc. Memory 3.3 Memory Map $0000 I/O REGISTERS (32 BYTES) $001F $0020 PAGE ZERO USER EPROM (48 BYTES) $004F $0050 UNIMPLEMENTED (48 BYTES) $007F $0080 RAM (128 BYTES) $00FF $0100 USER EPROM (2048 BYTES) $08FF $0900 MASK OPTION REGISTER $0901 UNIMPLEMENTED (5631 BYTES) ...

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... Freescale Semiconductor, Inc. 3.4 Input/Output Register Summary Addr. Name Port A Data Register $0000 (PORTA) See page 83. Port B Data Register $0001 (PORTB) See page 85. Port C Data Register $0002 (PORTC) See page 89. Port D Data Register $0003 (PORTD) See page 92. Data Direction Register A $0004 (DDRA) See page 83 ...

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... Freescale Semiconductor, Inc. Memory Addr. Name $0008 Unimplemented Unimplemented $0009 SIOP Control Register $000A (SCR) See page 125. SIOP Status Register $000B (SSR) See page 126. SIOP Data Register $000C (SDR) See page 127. $000D Unimplemented $0011 Unimplemented Timer Control Register ...

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... Freescale Semiconductor, Inc. Addr. Name Input Capture Register Low $0015 (ICRL) See page 114. Output Compare Register High $0016 (OCRH) See page 115. Output Compare Register Low $0017 (OCRL) See page 115. Timer Register High $0018 (TRH) See page 112. Timer Register Low ...

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... Freescale Semiconductor, Inc. Memory Addr. Name ADC Data Register $001D (ADDR) See page 136. ADC Status/Control Register $001E (ADSCR) See page 134. $001F Reserved Read: Mask Option Register $0900 (MOR) See page 42. COP Register $1FF0 (COPR) See page 97. Figure 3-2. I/O Register Summary (Sheet 3.5 RAM The 128 addresses from $0080– ...

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... Freescale Semiconductor, Inc. 3.6 EPROM/OTPROM An MCU with a quartz window has 2104 bytes of erasable, programmable ROM (EPROM). The quartz window allows EPROM erasure with ultraviolet light. NOTE: Keep the quartz window covered with an opaque material except when programming the MCU. Ambient light may affect MCU operation. ...

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... Freescale Semiconductor, Inc. Memory 3.6.1.1 EPROM Programming Register The EPROM programming register contains the control bits for programming the EPROM/OTPROM. $001C Read: Write: Reset Reserved LATCH — EPROM Bus Latch This read/write bit latches the address and data buses for EPROM/OTPROM programming. Clearing the LATCH bit automatically clears the EPGM bit ...

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... Freescale Semiconductor, Inc. Take the following steps to program a byte of EPROM/OTPROM: 1. Apply 16 the IRQ/V 2. Set the LATCH bit. 3. Write to any EPROM/OTPROM address. 4. Set the EPGM bit for a time Clear the LATCH bit. 3.6.1.2 Bootloader ROM The bootloader ROM, located at addresses $1F00–$1FEF, contains routines for copying an external EPROM to the on-chip EPROM/OTPROM ...

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... Freescale Semiconductor, Inc. Memory IRQ/V 2 MHz 27 OSC1 26 OSC2 RESET PC5/AN1 PC6/AN0 PROGRAM 13 PB7/SCK 330 VERIFY 12 PB6/SDI 330 The logical states of the PC4/AN2 and PC3/AN3 pins select the bootloader function, as Technical Data 40 For More Information On This Product, 2764 MC68HC705P9 10 PA0 PA1 D1 8 PA2 ...

Page 41

... Freescale Semiconductor, Inc. Complete the following steps to bootload the MCU: 1. Turn off all power to the circuit. 2. Install the EPROM containing the code to be downloaded. 3. Install the MCU. 4. Select the bootloader function: 5. Close switch S1. 6. Turn on the V CAUTION: Turn on the V 7. Turn on the V 8 ...

Page 42

... Freescale Semiconductor, Inc. Memory 3.7 Mask Option Register The mask option register (MOR EPROM/OTPROM byte that is programmable only with the bootloader function. The MOR controls: • • • To program the MOR, use the 5-step procedure given in Programming $0900 Read: Write: Reset: Erased: SIOP — ...

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... Freescale Semiconductor, Inc. Technical Data — MC68HC705P9 4.1 Contents 4.2 4.3 4.4 4.5 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 4.7 4.7.1 4.7.1.1 4.7.1.2 4.7.1.3 4.7.1.4 4.7.1.5 4.7.1.6 4.7.1.7 4.7.1.8 4.7.2 4.7.2.1 4.7.2.2 4.7.2.3 4.7.2.4 4.7.2.5 4.7.3 4.8 MC68HC705P9 — Rev. 4.0 ...

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... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 4.2 Features Features include: • • • • • • • • • 4.3 Introduction The central processor unit (CPU) consists of a CPU control unit, an arithmetic/logic unit (ALU), and five CPU registers. The CPU control unit fetches and decodes instructions ...

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... Freescale Semiconductor, Inc. CPU CONTROL UNIT HALF-CARRY FLAG INTERRUPT MASK CARRY/BORROW FLAG Figure 4-1. CPU Programming Model 4.5 Arithmetic/Logic Unit The arithmetic/logic unit (ALU) performs the arithmetic, logic, and manipulation operations decoded from the instruction set by the CPU control unit. The ALU produces the results called for by the program and sets or clears status and control bits in the condition code register (CCR) ...

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... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 4.6 CPU Registers The M68HC05 CPU contains five registers that control and monitor MCU operation: • • • • • CPU registers are not memory mapped. 4.6.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic and logic operations ...

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... Freescale Semiconductor, Inc. 4.6.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next stack location to be used. During a reset or after the reset stack pointer instruction (RSP), the stack pointer is preset to $00FF. The address in the stack pointer decrements after a byte is stacked and increments before a byte is unstacked ...

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... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 4.6.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. The three most significant bits of the program counter are ignored internally and appear as 000. Normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched ...

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... Freescale Semiconductor, Inc. I — Interrupt Mask Setting the interrupt mask disables interrupts interrupt request occurs while the interrupt mask is logic zero, the CPU saves the CPU registers on the stack, sets the interrupt mask, and then fetches the interrupt vector interrupt request occurs while the interrupt mask is set, the interrupt request is latched ...

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... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 4.7.1 Addressing Modes The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: • ...

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... Freescale Semiconductor, Inc. 4.7.1.4 Extended Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended ...

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... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 4.7.1.7 Indexed, 16-Bit Offset Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset ...

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... Freescale Semiconductor, Inc. 4.7.2.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. MC68HC705P9 — Rev. 4.0 MOTOROLA For More Information On This Product, Table 4-1 ...

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... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 4.7.2.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write operations on write-only registers. Technical Data ...

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... Freescale Semiconductor, Inc. 4.7.2.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met ...

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... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 4.7.2.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations ...

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... Freescale Semiconductor, Inc. 4.7.2.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. MC68HC705P9 — Rev. 4.0 MOTOROLA For More Information On This Product, Table 4-5. Control Instructions Instruction Clear Carry Bit Clear Interrupt Mask No Operation Reset Stack Pointer ...

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... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 4.7.3 Instruction Set Summary Table 4-6. Instruction Set Summary (Sheet Source Operation Form ADC #opr ADC opr ADC opr Add with Carry ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr Add without Carry ...

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... Freescale Semiconductor, Inc. Table 4-6. Instruction Set Summary (Sheet Source Operation Form BIL rel Branch if IRQ Pin Low BIT #opr BIT opr BIT opr Bit Test Accumulator with Memory Byte BIT opr,X BIT opr,X BIT ,X BLO rel Branch if Lower (Same as BCS) ...

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... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 4-6. Instruction Set Summary (Sheet Source Operation Form CLR opr CLRA CLRX Clear Byte CLR opr,X CLR ,X CMP #opr CMP opr CMP opr Compare Accumulator with Memory Byte CMP opr,X CMP opr,X CMP ,X ...

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... Freescale Semiconductor, Inc. Table 4-6. Instruction Set Summary (Sheet Source Operation Form JSR opr JSR opr JSR opr,X Jump to Subroutine JSR opr,X JSR ,X LDA #opr LDA opr LDA opr Load Accumulator with Memory Byte LDA opr,X LDA opr,X LDA ,X LDX #opr ...

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... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 4-6. Instruction Set Summary (Sheet Source Operation Form ROR opr RORA RORX Rotate Byte Right through Carry Bit ROR opr,X ROR ,X RSP Reset Stack Pointer RTI Return from Interrupt RTS Return from Subroutine ...

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... Freescale Semiconductor, Inc. Table 4-6. Instruction Set Summary (Sheet Source Operation Form TAX Transfer Accumulator to Index Register TST opr TSTA TSTX Test Memory Byte for Negative or Zero TST opr,X TST ,X TXA Transfer Index Register to Accumulator WAIT Stop CPU Clock and Enable Interrupts ...

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... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Technical Data 64 For More Information On This Product, Central Processor Unit (CPU) Go to: www.freescale.com MC68HC705P9 — Rev. 4.0 MOTOROLA ...

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... Freescale Semiconductor, Inc. Technical Data — MC68HC705P9 5.1 Contents 5.2 5.2.1 5.2.2 5.2.3 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.3.1 5.4.3.2 5.4.3.3 5.4.4 MC68HC705P9 — Rev. 4.0 MOTOROLA For More Information On This Product, Section 5. Resets and Interrupts Resets Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 COP Watchdog Reset ...

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... Freescale Semiconductor, Inc. Resets and Interrupts 5.2 Resets A reset immediately stops the operation of the instruction being executed, initializes certain control bits, and loads the program counter with a user-defined reset vector address. The following sources can generate resets: • • • 5.2.1 Power-On Reset ...

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... Freescale Semiconductor, Inc. OSC1 PIN INTERNAL INTERNAL ADDRESS BUS INTERNAL DATA BUS Notes: 1. Power-on reset threshold is typically between 1 V and Internal clock, internal address bus, and internal data bus are not available externally. 5.2.2 External Reset A logic zero applied to the RESET pin for one and one-half t generates an external reset ...

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... Freescale Semiconductor, Inc. Resets and Interrupts 5.2.3 COP Watchdog Reset A timeout of the COP watchdog generates a COP reset. The COP watchdog is part of a software error detection system and must be cleared periodically to start a new timeout period. To clear the COP watchdog and prevent a COP reset, write a logic zero to bit 0 (COPC) of the COP register at location $1FF0 ...

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... Freescale Semiconductor, Inc. 5.4.1 Software Interrupt The software interrupt (SWI) instruction causes a non-maskable interrupt. 5.4.2 External Interrupt An interrupt signal on the IRQ/V request. When the CPU completes its current instruction, it tests the IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition code register ...

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... Freescale Semiconductor, Inc. Resets and Interrupts IRQ/V latched as long as any source is holding the IRQ/V IRQ/V IRQ (INTERNAL) Interrupt Pulse Width Low (Edge-Triggered) Interrupt Pulse Period The minimum CYC Interrupt Pulse Width Low (Edge-Triggered) Interrupt Pulse Period The minimum CYC Technical Data ...

Page 71

... Freescale Semiconductor, Inc. 5.4.3 Timer Interrupts The capture/compare timer can generate the following interrupts: • • • Setting the I bit in the condition code register disables timer interrupts. 5.4.3.1 Input Capture Interrupt An input capture interrupt request occurs if the input capture flag, ICF, becomes set while the input capture interrupt enable bit, ICIE, is also set ...

Page 72

... Freescale Semiconductor, Inc. Resets and Interrupts 5.4.4 Interrupt Processing The CPU takes the following actions to begin servicing an interrupt: • • • The return from interrupt (RTI) instruction causes the CPU to recover the CPU registers from the stack as shown in STACKING ORDER Technical Data ...

Page 73

... Freescale Semiconductor, Inc. Function Reset Software Interrupt (SWI) External Interrupt Timer Interrupts 1. The COP watchdog is programmable in the mask option register. MC68HC705P9 — Rev. 4.0 MOTOROLA For More Information On This Product, Table 5-4. Reset/Interrupt Vector Addresses Local Global Source Mask Mask Power-On ...

Page 74

... Freescale Semiconductor, Inc. Resets and Interrupts Technical Data 74 For More Information On This Product, FROM RESET YES I BIT SET? NO YES EXTERNAL INTERRUPT? NO TIMER YES INTERRUPT? STACK PC CCR. NO LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. SWI YES INSTRUCTION? NO RTI YES UNSTACK CCR PC. ...

Page 75

... Freescale Semiconductor, Inc. Technical Data — MC68HC705P9 6.1 Contents 6.2 6.3 6.4 6.2 Stop Mode The STOP instruction puts the MCU in its lowest power-consumption mode and has the following effects on the MCU: • • • The STOP instruction does not affect any other registers or any I/O lines. ...

Page 76

... Freescale Semiconductor, Inc. Low Power Modes When the MCU exits stop mode, processing resumes after a stabilization delay of 4064 oscillator cycles. An active edge on the PD7/TCAP pin during stop mode sets the ICF flag when an external interrupt brings the MCU out of stop mode. An external interrupt also latches the value in the timer registers into the input capture registers ...

Page 77

... Freescale Semiconductor, Inc. Figure 6-2 instruction. MC68HC705P9 — Rev. 4.0 MOTOROLA For More Information On This Product, shows the sequence of events caused by the STOP STOP CLEAR I BIT IN CCR CLEAR TIMER INTERRUPT FLAGS AND TIMER INTERRUPT ENABLE BITS CLEAR TIMER PRESCALER TURN OFF OSCILLATOR ...

Page 78

... Freescale Semiconductor, Inc. Low Power Modes 6.3 Wait Mode The WAIT instruction puts the MCU in an intermediate power- consumption mode and has the following effects on the MCU: • • The WAIT instruction does not affect any other registers or any I/O lines. ...

Page 79

... Freescale Semiconductor, Inc. Figure 6-3 instruction. MC68HC705P9 — Rev. 4.0 MOTOROLA For More Information On This Product, shows the sequence of events caused by the WAIT WAIT CLEAR I BIT IN CCR STOP CPU CLOCK RESET? YES YES YES RESTART CPU CLOCK (1) FETCH RESET VECTOR OR (2) SERVICE INTERRUPT a ...

Page 80

... Freescale Semiconductor, Inc. Low Power Modes Figure 6-4 CPU clock and the timer clock. 6.4 Data-Retention Mode In data-retention mode, the MCU retains RAM contents and CPU register contents at V feature allows the MCU to remain in a low-power consumption state during which it retains data, but the CPU cannot execute instructions. ...

Page 81

... Freescale Semiconductor, Inc. Technical Data — MC68HC705P9 Section 7. Parallel Input/Output (I/O) Ports 7.1 Contents 7.2 7.3 7.3.1 7.3.2 7.4 7.4.1 7.4.2 7.5 7.5.1 7.5.2 7.6 7.6.1 7.6.2 7.2 Introduction Twenty bidirectional pins and one input-only pin form four parallel input/output (I/O) ports. All the bidirectional port pins are programmable as inputs or outputs ...

Page 82

... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) Ports Addr. Name: Port A Data Register $0000 (PORTA) See page 83. Port B Data Register $0001 (PORTB) See page 85. Port C Data Register $0002 (PORTC) See page 88. Port D Data Register $0003 (PORTD) See page 91. Data Direction Register A $0004 (DDRA) See page 83 ...

Page 83

... Freescale Semiconductor, Inc. 7.3 Port A Port 8-bit general-purpose I/O port. 7.3.1 Port A Data Register (PORTA) The port A data register contains a latch for each of the eight port A pins. $0000 Read: Write: Reset: PA[7:0] — Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A ...

Page 84

... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) Ports NOTE: Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from Figure 7-4 Writing a logic one to a DDRA bit enables the output buffer for the corresponding port A pin; a logic zero disables the output buffer. ...

Page 85

... Freescale Semiconductor, Inc. 7.4 Port B Port 3-bit I/O port that shares its pins with the serial I/O port (SIOP). NOTE: Do not use port B for general-purpose I/O while the SIOP is enabled. 7.4.1 Port B Data Register (PORTB) The port B data register contains a latch for each of the three port B pins. ...

Page 86

... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) Ports SDI — Serial Data Input When the SIOP is enabled, SDI is the SIOP data input. SDO — Serial Data Output When the SIOP is enabled, SDO is the SIOP data output. 7.4.2 Data Direction Register B (DDRB) Data direction register B determines whether each port B pin is an input or an output ...

Page 87

... Freescale Semiconductor, Inc. Writing a logic one to a DDRB bit enables the output buffer for the corresponding port B pin; a logic zero disables the output buffer. When bit DDRBx is a logic one, reading address $0001 reads the PBx data latch. When bit DDRBx is a logic zero, reading address $0001 reads the voltage level on the pin ...

Page 88

... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) Ports 7.5.1 Port C Data Register (PORTC) The port C data register contains a latch for each of the eight port C pins. $0002 Read: Write: Reset: Alternate Function: PC[7:0] — Port C Data Bits These read/write bits are software programmable. Data direction of each port C pin is under the control of the corresponding bit in data direction register C ...

Page 89

... Freescale Semiconductor, Inc. 7.5.2 Data Direction Register C (DDRC) Data direction register C determines whether each port C pin is an input or an output. $0006 Read: Write: Reset: DDRC[7:0] — Data Direction Register C Bits These read/write bits control port C data direction. Reset clears DDRC[7:0], configuring all port C pins as inputs. ...

Page 90

... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) Ports Writing a logic one to a DDRC bit enables the output buffer for the corresponding port C pin; a logic zero disables the output buffer. When bit DDRCx is a logic one, reading address $0002 reads the PCx data latch. When bit DDRCx is a logic zero, reading address $0002 reads the voltage level on the pin ...

Page 91

... Freescale Semiconductor, Inc. 7.6.1 Port D Data Register (PORTD) The port D data register contains a latch for each of the two port D pins. $0003 Read: Write: Reset: Alternate Function: PD7 and PD5 — Port D Data Bits These read/write bits are software programmable. Data direction of each port D pin is under the control of the corresponding bit in data direction register D ...

Page 92

... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) Ports 7.6.2 Data Direction Register D (DDRD) Data direction register D determines whether each port D pin is an input or an output. $0007 Read: Write: Reset: DDRD5 — Data Direction Register D Bit This read/write bit controls the data direction of pin PD5. Reset clears DDRD5, configuring PD5 as an input ...

Page 93

... Freescale Semiconductor, Inc. Writing a logic one to a DDRD bit enables the output buffer for the corresponding port D pin; a logic zero disables the output buffer. When bit DDRDx is a logic one, reading address $0003 reads the PDx data latch. When bit DDRDx is a logic zero, reading address $0003 reads the voltage level on the pin ...

Page 94

... Freescale Semiconductor, Inc. Parallel Input/Output (I/O) Ports Technical Data 94 For More Information On This Product, Parallel Input/Output (I/O) Ports Go to: www.freescale.com MC68HC705P9 — Rev. 4.0 MOTOROLA ...

Page 95

... Freescale Semiconductor, Inc. Technical Data — MC68HC705P9 Section 8. Computer Operating Properly Watchdog (COP) 8.1 Contents 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.5 8.6 8.7 8.7.1 8.7.2 8.2 Features Features include: • • • MC68HC705P9 — Rev. 4.0 MOTOROLA Computer Operating Properly Watchdog (COP) For More Information On This Product, Features ...

Page 96

... Freescale Semiconductor, Inc. Computer Operating Properly Watchdog (COP) 8.3 Introduction The purpose of the computer operating properly (COP) watchdog is to reset the MCU in case of software failure. Software that is operating properly periodically services the COP watchdog and prevents the reset from occurring. The COP watchdog function is programmable in the mask option register ...

Page 97

... Freescale Semiconductor, Inc. 8.4.3 Clearing the COP Watchdog To clear the COP watchdog and prevent a COP reset, write a logic zero to bit 0 (COPC) of the COP register at location $1FF0. If the main program executes within the COP timeout period, the clearing routine needs to be executed only once. If the main program takes longer than the COP timeout period, the clearing routine must be executed more than once ...

Page 98

... Freescale Semiconductor, Inc. Computer Operating Properly Watchdog (COP) 8.7 Low-Power Modes The STOP and WAIT instructions put the MCU in low-power consumption standby modes. 8.7.1 Stop Mode The STOP instruction clears the COP watchdog counter. Upon exit from stop mode by external reset: • ...

Page 99

... Freescale Semiconductor, Inc. Technical Data — MC68HC705P9 9.1 Contents 9.2 9.3 9.4 9.4.1 9.4.1.1 9.4.1.2 9.4.2 9.4.3 9.5 9.6 9.7 9.7.1 9.7.2 9.7.3 9.7.4 9.7.5 9.7.6 9.8 9.8.1 9.8.2 MC68HC705P9 — Rev. 4.0 MOTOROLA For More Information On This Product, Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Introduction ...

Page 100

... Freescale Semiconductor, Inc. Timer 9.2 Features Features include: • • • • • 9.3 Introduction The timer provides a timing reference for MCU operations. The input capture and output compare functions provide a means to latch the times at which external events occur, to measure input waveforms, and to generate output waveforms and timing delays ...

Page 101

... Freescale Semiconductor, Inc. EDGE SELECT/ TCAP DETECT LOGIC IEDG INTERNAL CLOCK (XTAL 2) 4 INTERNAL DATA BUS 9.4 Operation The timing reference for the input capture and output compare functions is a 16-bit free-running counter. The counter is preceded by a divide-by- four prescaler and rolls over every 2 MHz crystal ...

Page 102

... Freescale Semiconductor, Inc. Timer Addr. Name Timer Control Register $0012 See page 109. Timer Status Register $0013 See page 110. Input Capture Register High $0014 See page 114. Input Capture Register Low $0015 See page 114. Output Compare Register High $0016 See page 115 ...

Page 103

... Freescale Semiconductor, Inc. 9.4.1 Pin Functions The timer uses two pins. 9.4.1.1 PD7/TCAP PD7/TCAP is the input capture pin. When an active edge occurs on PD7/TCAP, the timer transfers the current counter value to the input capture registers. PD7/TCAP is also an I/O port pin. 9.4.1.2 TCMP TCMP is the output-only output compare pin ...

Page 104

... Freescale Semiconductor, Inc. Timer 9.4.3 Output Compare The output compare function is a means of generating an output signal when the 16-bit counter reaches a selected value. Software writes the selected value into the output compare registers. On every fourth internal clock cycle the output compare circuitry compares the value of the counter to the value written in the output compare registers ...

Page 105

... Freescale Semiconductor, Inc. 9.5 Timing Timer Resolution Input Capture Pulse Width Input Capture Pulse Period 2-bit prescaler in the timer is the limiting factor as it counts The minimum CYC Timer Resolution Input Capture Pulse Width Input Capture Pulse Period 2-bit prescaler in the timer is the limiting factor as it counts ...

Page 106

... Freescale Semiconductor, Inc. Timer BUS CLOCK TIMER CLOCKS RESET (EXTERNAL OR END OF POR) TIMER CLOCKS INPUT CAPTURE INPUT CAPTURE INPUT CAPTURE INPUT CAPTURE Note: If the input capture edge occurs in the shaded area between T10 states, then the input capture flag becomes set during the next T11 state. ...

Page 107

... Freescale Semiconductor, Inc. BUS CLOCK TIMER CLOCKS OUTPUT COMPARE REGISTERS REGISTER LATCH OUTPUT COMPARE FLAG AND TCMP NOTES write to the output compare registers may occur at any time, but a compare only occurs at timer state T01. Therefore, the compare may follow the write four cycles. ...

Page 108

... Freescale Semiconductor, Inc. Timer 9.6 Interrupts The following timer sources can generate interrupts: • • • Table 9-3 9.7 I/O Registers The following registers control and monitor the operation of the timer: • • • • • • Technical Data 108 For More Information On This Product, Input capture flag (ICF) — ...

Page 109

... Freescale Semiconductor, Inc. 9.7.1 Timer Control Register The timer control register (TCR) performs the following functions: • • • • • $0012 Read: Write: Reset: ICIE — Input Capture Interrupt Enable This read/write bit enables interrupts caused by an active signal on the PD7/TCAP pin. Reset clears the ICIE bit. ...

Page 110

... Freescale Semiconductor, Inc. Timer Bits 4–2 — Unused These are read/write bits that always read as logic zeros. IEDG — Input Edge The state of this read/write bit determines whether a positive or negative transition on the PD7/TCAP pin triggers a transfer of the contents of the timer registers to the input capture registers. Reset has no effect on the IEDG bit. OLVL — ...

Page 111

... Freescale Semiconductor, Inc. ICF — Input Capture Flag The ICF bit is automatically set when an edge of the selected polarity occurs on the PD7/TCAP pin. Clear the ICF bit by reading the timer status register with ICF set, and then reading the low byte of the input capture registers. Reset has no effect on ICF. OCF — ...

Page 112

... Freescale Semiconductor, Inc. Timer 9.7.3 Timer Registers The read-only timer registers (TRH and TRL) contain the current high and low bytes of the 16-bit counter. Reading TRH before reading TRL causes TRL to be latched until TRL is read. Reading TRL after reading the timer status register clears the timer overflow flag (TOF). Writing to the timer registers has no effect ...

Page 113

... Freescale Semiconductor, Inc. 9.7.4 Alternate Timer Registers The read-only alternate timer registers (ATRH and ATRL) contain the current high and low bytes of the 16-bit counter. Reading ATRH before reading ATRL causes ATRL to be latched until ATRL is read. Reading does not affect the timer overflow flag (TOF). Writing to the alternate timer registers has no effect ...

Page 114

... Freescale Semiconductor, Inc. Timer 9.7.5 Input Capture Registers When a selected edge occurs on the TCAP pin, the current high and low bytes of the 16-bit counter are latched into the read-only input capture registers (ICRH and ICRL). Reading ICRH before reading ICRL inhibits further captures until ICRL is read ...

Page 115

... Freescale Semiconductor, Inc. 9.7.6 Output Compare Registers When the value of the 16-bit counter matches the value in the read/write output compare registers (OCRH and OCRL), the planned TCMP pin action takes place. Writing to OCRH before writing to OCRL inhibits timer compares until OCRL is written. Reading or writing to OCRL after reading the timer status register clears the output compare flag (OCF) ...

Page 116

... Freescale Semiconductor, Inc. Timer 9.8 Low-Power Modes The STOP and WAIT instructions put the MCU in low-power consumption standby modes. 9.8.1 Stop Mode The STOP instruction suspends the timer counter. Upon exit from stop mode by external reset: • • Upon exit from stop mode by external interrupt: • ...

Page 117

... Freescale Semiconductor, Inc. Technical Data — MC68HC705P9 Section 10. Serial Input/Output Port (SIOP) 10.1 Contents 10.2 10.3 10.4 10.4.1 10.4.1.1 10.4.1.2 10.4.1.3 10.4.2 10.5 10.6 10.7 10.7.1 10.7.2 10.7.3 10.8 10.8.1 10.8.2 MC68HC705P9 — Rev. 4.0 MOTOROLA For More Information On This Product, Features ...

Page 118

... Freescale Semiconductor, Inc. Serial Input/Output Port (SIOP) 10.2 Features Features include: • • • • • • • 10.3 Introduction The serial input/output port (SIOP 3-wire master/slave communication port with serial clock, data input, and data output connections. The SIOP enables high-speed synchronous serial data transfer between the MCU and peripheral devices ...

Page 119

... Freescale Semiconductor, Inc. FROM MOR SIOP CONTROL INTERNAL DIVIDE CLOCK (f 2) OSC Addr. Name SIOP Control Register $000A (SCR) See page 125. SIOP Status Register $000B (SSR) See page 126. SIOP Data Register $000C (SDR) See page 127. Figure 10-2. SIOP I/O Register Summary MC68HC705P9 — ...

Page 120

... Freescale Semiconductor, Inc. Serial Input/Output Port (SIOP) 10.4 Operation The master MCU initiates and controls the transfer of data to and from one or more slave peripheral devices. In master mode, a transmission is initiated by writing to the SIOP data register (SDR). Data written to the SDR is parallel-loaded and shifted out serially to the slave device(s). ...

Page 121

... Freescale Semiconductor, Inc. When bit 6 (SPE) of the SIOP control register (SCR) is set, the SIOP is enabled and the PB7/SCK, PB5/SDO, and PB6/SDI pins are dedicated to SIOP functions. Clearing SPE disables the SIOP and the SIOP pins become standard I/O port pins. NOTE: ...

Page 122

... Freescale Semiconductor, Inc. Serial Input/Output Port (SIOP) The first falling edge on PB7/SCK begins a transmission. At this time the first bit of received data is accepted at the PB6/SDI pin and the first bit of transmitted data is presented at the PB5/SDO pin. 10.4.1.2 PB5/SDO The PB5/SDO pin is the SIOP data output. Between transfers, the state of the PB5/SDO pin reflects the value of the last bit shifted out on the previous transmission, if there was one ...

Page 123

... Freescale Semiconductor, Inc. 10.4.2 Data Movement Connecting the SIOP data register of a master MCU with the SIOP of a slave MCU forms a 16-bit circular shift register. During an SIOP transfer, the master shifts out the contents of its SIOP data register on its PB5/SDO pin. At the same time, the slave MCU shifts out the contents of its SIOP data register on its PB5/SDO pin ...

Page 124

... Freescale Semiconductor, Inc. Serial Input/Output Port (SIOP) Frequency of Operation Master Slave Cycle Time Master Slave Clock (SCK) Low Time (f SDO Data Valid Time SDO Hold Time SDI Setup Time SDI Hold Time 5.0 Vdc 10 CYC crystal frequency; f OSC 4. In master mode, the frequency of SCK is f ...

Page 125

... Freescale Semiconductor, Inc. 10.6 Interrupts The SIOP does not generate interrupt requests. 10.7 I/O Registers The following registers control and monitor SIOP operation: • • • 10.7.1 SIOP Control Register The read/write SIOP control register (SCR) contains two bits. One bit enables the SIOP, and the other configures the SIOP for master mode or for slave mode ...

Page 126

... Freescale Semiconductor, Inc. Serial Input/Output Port (SIOP) Clearing SPE during a transmission aborts the transmission, resets the bit counter, and returns the port to its normal I/O function. Reset clears SPE. MSTR — Master Mode Select This read/write bit configures the SIOP for master mode. Setting MSTR initializes the PB7/SCK pin as the serial clock output ...

Page 127

... Freescale Semiconductor, Inc. This clearable, read-only bit is automatically set if the SIOP data register is accessed while a data transfer is in progress. Reading or writing the SIOP data register while a transmission is in progress causes invalid data to be transmitted or read. Clear DCOL by reading the SIOP status register with SPIF set and then accessing the SIOP data register ...

Page 128

... Freescale Semiconductor, Inc. Serial Input/Output Port (SIOP) 10.8 Low-Power Modes The WAIT and STOP instructions put the MCU in low-power consumption standby modes. 10.8.1 Stop Mode The STOP instruction suspends the clock to the SIOP. When the MCU exits stop mode, processing resumes after the internal oscillator stabilization delay of 4064 oscillator cycles ...

Page 129

... Freescale Semiconductor, Inc. Technical Data — MC68HC705P9 Section 11. Analog-to-Digital Converter (ADC) 11.1 Contents 11.2 11.3 11.4 11.4.1 11.4.1.1 11.4.1.2 11.5 11.6 11.7 11.7.1 11.7.2 11.8 11.8.1 11.8.2 11.2 Features Features include: • • • MC68HC705P9 — Rev. 4.0 MOTOROLA For More Information On This Product, Features ...

Page 130

... Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) 11.3 Introduction The ADC consists of a single successive-approximation A/D converter, an input multiplexer to select one of four external or two internal channels, and control circuitry. ADC module. Technical Data 130 For More Information On This Product, Figure 11-1 AN3 ...

Page 131

... Freescale Semiconductor, Inc. Addr. Name ADC Data Register $001D (ADDR) See page 136. ADC Status/Control Register $001E (ADSCR) See page 134. Figure 11-2. ADC I/O Register Summary 11.4 Operation The A/D conversion process is ratiometric, using two reference voltages, V and 11.4.1 Pin Functions The ADC uses five pins and shares them with port C: • ...

Page 132

... Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) 11.4.1.2 PC6/AN0–PC3/AN3 The multiplexer can select one of four external analog input channels (AN0, AN1, AN2, or AN3) for sampling. The conversion takes 32 cycles. The first 12 cycles sample the voltage on the selected input pin by charging an internal capacitor. In the last 20 cycles, a comparator successively compares the output of an internal D/A converter to the sampled analog input ...

Page 133

... Freescale Semiconductor, Inc. 11.6 Timing and Electrical Characteristics Resolution Absolute Accuracy (4.0 > V Conversion Range (PC7/V Conversion Time (Includes Sampling Time) External Clock Internal RC Oscillator (ADRC = 1) Monotonicity Zero Input Reading (V Full-Scale Reading (V Sample Acquisition Time External Clock Internal RC Oscillator (ADRC = 1) Input Capacitance ...

Page 134

... Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) 11.7 I/O Registers The following registers control and monitor operation of the ADC: • • 11.7.1 ADC Status and Control Register The ADC status and control register (ADSCR) contains a conversion complete flag and four writable control bits. Writing to ADSCR clears the conversion complete flag and starts a new conversion sequence ...

Page 135

... Freescale Semiconductor, Inc. When the internal RC oscillator is being used as the ADC clock, two limitations apply: • • ADON — ADC On This read/write bit turns on the ADC. When the ADC is on, it requires a time, t results can be inaccurate. Resets clear the ADON bit. Bits 4–2 — Not used Bits 4– ...

Page 136

... Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) To prevent excess power dissipation, do not use an ADC pin as an analog input and a digital input at the same time. Using one of the port pins as the ADC input does not affect the ability to use the remaining port pins as digital inputs. ...

Page 137

... Freescale Semiconductor, Inc. Technical Data — MC68HC705P9 12.1 Contents 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 Maximum Supply Current vs. Internal Clock Frequency .145 12.11 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.12 3.3 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 MC68HC705P9 — Rev. 4.0 MOTOROLA For More Information On This Product, Section 12 ...

Page 138

... Freescale Semiconductor, Inc. Electrical Specifications 12.2 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table here ...

Page 139

... Freescale Semiconductor, Inc. 12.3 Operating Temperature Range MC68HC705P9P MC68HC705P9C MC68HC705P9V MC68HC705P9M Plastic dual in-line package (PDIP Small outline integrated circuit (SOIC Ceramic dual in-line package (Cerdip Extended temperature range (– Automotive temperature range (–40 to +105 Automotive temperature range (–40 to +125 C) 12.4 Thermal Characteristics ...

Page 140

... Freescale Semiconductor, Inc. Electrical Specifications 12.5 Power Considerations The average chip junction temperature, T Where INT P I/O For most applications, P Ignoring P Solving equations (1) and (2) for K gives: where constant pertaining to the particular part. K can be determined from equation (3) by measuring P known T by solving equations (1) and (2) iteratively for any value of T ...

Page 141

... Freescale Semiconductor, Inc. 12.6 5.0-Volt DC Electrical Characteristics Characteristic Output Voltage I = 10.0 A LOAD I = –10.0 A LOAD Output High Voltage (I = –0.8 mA) LOAD PA7–PA0, PB7/SCK–PB5/SDO, PC7/V TCMP Output Low Voltage (I = 1.6 mA) LOAD PA7–PA0, PB7/SCK–PB5/SDO, PC7/V TCMP Input High Voltage PA7–PA0, PB7/SCK–PB5/SDO, PC7/V ...

Page 142

... Freescale Semiconductor, Inc. Electrical Specifications 12.7 3.3-Volt DC Electrical Characteristics Characteristic Output Voltage (I 10.0 A) LOAD Output High Voltage (I = –0.2 mA) LOAD PA7–PA0, PB7/SCK–PB5/SDO, PC7/V TCMP Output Low Voltage (I = 0.4 mA) LOAD PA7–PA0, PB7/SCK–PB5/SDO, PC7/V TCMP Input High Voltage PA7–PA0, PB7/SCK–PB5/SDO, PC7/V ...

Page 143

... Freescale Semiconductor, Inc. 12.8 Driver Characteristics 5.0 V 0.8 (NOTE 2) 0.7 0.6 0.5 0.4 0.3 0.2 0 –1.0 –2 (mA) NOTES: 1. Shaded area indicates variation in driver characteristics due to changes in temperature and for normal processing tolerances. Within the limited range of values shown, V vs. I curves are approximately straight lines. ...

Page 144

... Freescale Semiconductor, Inc. Electrical Specifications 12.9 Typical Supply Current vs. Internal Clock Frequency 2.0 1.5 1.0 0 0.5 1.0 INTERNAL CLOCK FREQUENCY (MHz) Figure 12-3. Typical Supply Current vs. Internal Clock Frequency Technical Data 144 For More Information On This Product, 5.0 RUN MODE ...

Page 145

... Freescale Semiconductor, Inc. 12.10 Maximum Supply Current vs. Internal Clock Frequency 7 10% DD –40 to +125 C 6.0 Run Mode Wait Mode (ADC On) Wait Mode (ADC Off) 5.0 4.0 3.0 2.0 1 0.5 1.0 INTERNAL CLOCK FREQUENCY (MHz) Figure 12-4. Maximum Supply Current vs. Internal Clock Frequency MC68HC705P9 — ...

Page 146

... Freescale Semiconductor, Inc. Electrical Specifications 12.11 5.0-Volt Control Timing Oscillator Frequency Crystal External Clock Internal Operating Frequency (f Crystal External Clock Cycle Time (1 Crystal Oscillator Startup Time Stop Recovery Startup Time (Crystal Oscillator) RESET Pulse Width Timer Resolution Input Capture Pulse Width ...

Page 147

... Freescale Semiconductor, Inc. 12.12 3.3 V Control Timing Oscillator Frequency Crystal External Clock Internal Operating Frequency (f Crystal External Clock Cycle Time (1 Crystal Oscillator Startup Time Stop Recovery Startup Time (Crystal Oscillator) RESET Pulse Width Timer Resolution Input Capture Pulse Width Input Capture Pulse Period ...

Page 148

... Freescale Semiconductor, Inc. Electrical Specifications Technical Data 148 For More Information On This Product, Electrical Specifications Go to: www.freescale.com MC68HC705P9 — Rev. 4.0 MOTOROLA ...

Page 149

... Freescale Semiconductor, Inc. Advance Information — MC68HC705P9 13.1 Contents 13.2 13.3 13.4 13.5 13.2 Introduction The MC68HC705P9 is available in the following packages: • • • 13.3 28-Pin PDIP — Case #710 MC68HC705P9 — Rev. 4.0 MOTOROLA For More Information On This Product, Section 13. Mechanical Specifications Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 28-Pin PDIP — ...

Page 150

... Freescale Semiconductor, Inc. Mechanical Specifications 13.4 28-Pin Cerdip — Case #733 28 1 -A- N -T- SEATING PLANE 13.5 28-Pin SOIC — Case #751F - 28X 0.010 (0.25 -T- G 26X Technical Data 150 For More Information On This Product 0.25 (0.010 14X 0.010 (0.25 - -T- SEATING PLANE ...

Page 151

... Ordering Information Go to: www.freescale.com Operating Order Number Temperature 0 to +70 C MC68HC705P9P –40 to +85 C MC68HC705P9CP –40 to +105 C MC68HC705P9VP –40 to +125 C MC68HC705P9MP 0 to +70 C MC68HC705P9DW –40 to +85 C MC68HC705P9CDW –40 to +105 C MC68HC705P9VDW –40 to +125 C MC68HC705P9MDW 0 to +70 C MC68HC705P9S –40 to +85 C MC68HC705P9CS – ...

Page 152

... Freescale Semiconductor, Inc. Ordering Information Technical Data 152 For More Information On This Product, Ordering Information Go to: www.freescale.com MC68HC705P9 — Rev. 4.0 MOTOROLA ...

Page 153

... Freescale Semiconductor, Inc. Technical Data — MC68HC705P9 A accumulator ( .49–50, ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC (analog-to-digital converter) block diagram . . . . . . . . . . . . . . . . . . features . . . . . . . . . . . . . . . . . . . . . . . I/O register summary . . . . . . . . . . . . I/O registers . . . . . . . . . . . . . . . . . . . low-power modes . . . . . . . . . . . . . . . ADC data register (ADDR .132, ADC status and control register (ADSCR .132, addressing modes . . . . . . . . . . . . . . . . . . ...

Page 154

... Freescale Semiconductor, Inc. Index CPU registers . . . . . . . . . . .36, 50, 53, 57, accumulator ( .49–50, condition code register (CCR) .45, 55, 69, 71–72, index register ( program counter (PC .52, 55, 66, stack pointer (SP crystal AT-cut . . . . . . . . . . . . . . . . . . . . . . . . . strip . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 155

... Freescale Semiconductor, Inc. PC[7:0] bits . . . . . . . . . . . . . . . . . . . . . PD5 bit . . . . . . . . . . . . . . . . . . . . . . . . PD7 bit . . . . . . . . . . . . . . . . . . . . . . . . SIOP bit . . . . . . . . . . . . . . . . . . . . . . . . SPE bit . . . . . . . . . . . .121–122, 125, SPIF bit . . . . . . . . . . . . . . . . . . . . . . . TOF bit . . . . . . . . . . . . .71, 108, TOIE bit . . . . . . . . . . . . . . . . .71, I/O pins IRQ/V pin . . . . . .22, 29, 38–39, 42, PP OSC1 pin . . . . . . . . . . . . . . . . . . . . . . ...

Page 156

... Freescale Semiconductor, Inc. Index software interrupt . . . . . . . . . . . . . . . . timer interrupts . . . . . . . . . . . . . . . . . . IRQ bit . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ latch . . . . . . . . . . . . . . . . . . . . . . . . . IRQ/V pin . . . . . . . . .22, 29, 38–39, 42 junction temperature . . . . . . . . . . . . . . . . L LATCH bit . . . . . . . . . . . . . . . . . . . . . . . . . low voltage protection . . . . . . . . . . . . . . . . low-power modes ADC in stop and wait modes . . . . . . . COP in stop and wait modes . . . . . . . data-retention mode . . . . . . . . . . . . . . ...

Page 157

... Freescale Semiconductor, Inc. PC7/V pin . . . . . . . . . . . . . . . . . . . .88, RH PD5 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . PD7 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . PD7/TCAP pin . . . . . . .39, 90, 103, pin assignments . . . . . . . . . . . . . . . . . . . . pin functions . . . . . . . . . . . . . . . . . . . . . . . port .29, data direction register A (DDRA port A data register (PORTA port .29, data direction register B (DDRB port B data register (PORTB port .29, data direction register C (DDRC ...

Page 158

... Freescale Semiconductor, Inc. Index SIOP bit . . . . . . . . . . . . . . . . . . . . . . . . . . SIOP control register (SCR .121, 125, SIOP data register (SDR SIOP status register (SSR software failure . . . . . . . . . . . . . . . . . . . . . software interrupt vector . . . . . . . . . . . . . . SPE bit . . . . . . . . . . . . . . .121–122, 125, specifications See "electrical specifications." See "mechanical specifications." SPIF bit . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 159

... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

Page 160

... Freescale Semiconductor, Inc. Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center ...

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