CDP1854ACD3 Intersil Corporation, CDP1854ACD3 Datasheet
CDP1854ACD3
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CDP1854ACD3 Summary of contents
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... Fully Programmable with Externally Selectable Word Length (5-8 Bits), Parity Inhibit, Even/Odd Parity, and 1, 1-1/ Stop Bits Ordering Information PACK- TEMP. 5V/200K AGE RANGE BAUD o o SBDIP - +125 C CDP1854ACD3 CDP1854ACD3 D40.6 Pinouts CDP1854A/3, CDP1854AC/3 (SBDIP) (MODE 0) TOP VIEW VDD 1 MODE ( RRD 4 ...
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Absolute Maximum Ratings DC Supply-Voltage Range (All voltages referenced to V terminal) SS CDP1854A ...
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Specifications CDP1854A/3, CDP1854AC/3 Operating Conditions Full Package-Temperature Range. For maximum reliability, operating conditions should be selected A so that operation is always within the following ranges: PARAMETER DC Operating Voltage Range Input Voltage Range Baud Rate (Receive ...
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Dynamic Electrical Specifications PARAMETER RECEIVER TIMING - MODE 1 Clock Period Pulse Width Clock Low Level Clock High Level TPB Setup Time Data Start Bit to Clock Propagation Delay Time TPB to DATA AVAILABLE Clock to DATA AVAILABLE Clock to ...
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TRANSMITTER HOLDING REGISTER LOADED (NOTE 1) T CLOCK WRITE (TPB) (NOTE TTH THRE SDO NOTES: 1. The holding register is loaded on the trailing edge of TPB. 2. The transmitter shift register, if empty, is loaded ...
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Dynamic Electrical Specifications PARAMETER CPU INTERFACE - WRITE TIMING - MODE 1 Pulse Width TPB Setup Time RSEL to Write Data to Write Hold Time RSEL after Write Data after Write TPB (NOTE 1) RSEL T BUS 0- T BUS ...
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Dynamic Electrical Specifications PARAMETER CPU INTERFACE - READ TIMING - MODE 1 Pulse Width TPB Setup Time RSEL to TPB Hold Time RSEL after TPB Propagation Delay Time Read to Data Valid Time RESEL to Data Valid Time TPB RSEL ...
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Dynamic Electrical Specifications PARAMETER INTERFACE TIMING - MODE 0 Pulse Width CRL MR Setup Time Control Word to CRL Hold Time Control Word after CRL Propagation Delay Time SFD High to SOD SFD Low to SOD RRD High to Receiver ...
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Dynamic Electrical Specifications PARAMETER TRANSMITTER TIMING - MODE 0 Clock Period Pulse Width Clock Low Level Clock High Level THRL Setup Time THRL to Clock Data to THRL Hold Time Data after THRL Propagation Delay Time Clock to Data Start ...
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CLOCK t THC THRL t THTH SDO t TTHR THRE TSRE BUS 0 T BUS 7 NOTES: 1. The holding register is loaded on the trailing edge of THRL. 2. The transmitter ...
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Dynamic Electrical Specifications PARAMETER RECEIVER TIMING - MODE 0 Clock Period Pulse Width Clock Low Level Clock High Level DATA AVAILABLE RESET Setup Time Data Start Bit to Clock Propagation Delay Time DATA AVAILABLE RESET to Data Available Clock to ...
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... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...