CY7C197-35PC Cypress Semiconductor Corporation., CY7C197-35PC Datasheet

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CY7C197-35PC

Manufacturer Part Number
CY7C197-35PC
Description
256Kx1 Static RAM
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-05049 Rev. **
Features
Functional Description
The CY7C197 is a high-performance CMOS static RAM orga-
nized as 256K words by 1 bit. Easy memory expansion is pro-
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
• High speed
• CMOS for optimum speed/power
• Low active power
• Low standby power
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Logic Block Diagram
— 12 ns
— 880 mW
— 220 mW
A
A
A
A
A
A
A
A
A
A
13
14
15
16
17
0
1
2
3
4
A
5
A
6
A
7
INPUT BUFFER
DECODER
COLUMN
A
1024 x 256
8
ARRAY
A
9
A
10
A
11
A
12
POWER
DOWN
7C197-12
150
12
30
3901 North First Street
7C197-15
DI
DO
C197-1
CE
WE
140
15
30
vided by an active LOW Chip Enable (CE) and three-state driv-
ers. The CY7C197 has an automatic power-down feature,
reducing the power consumption by 75% when deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW. Data on the
input pin (D
the address pins (A
Reading the device is accomplished by taking chip enable
(CE) LOW while Write Enable (WE) remains HIGH. Under
these conditions the contents of the memory location specified
on the address pins will appear on the data output (D
The output pin stays in a high-impedance state when Chip
Enable (CE) is HIGH or Write Enable (WE) is LOW.
The CY7C197 utilizes a die coat to insure alpha immunity.
Pin Configurations
D
GND
OUT
WE
7C197-20
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
135
20
30
1
2
3
4
5
6
7
8
9
10
11
12
DIP/SOJ
Top View
IN
San Jose
7C197
) is written into the memory location specified on
13
24
23
22
21
20
19
18
17
16
15
14
0
7C197-25
C197-2
through A
A
256Kx1 Static RAM
V
A
A
A
A
A
A
A
A
D
CE
12
CC
17
16
15
14
13
11
10
9
IN
25
95
30
CA 95134
17
D
OUT
).
NC
NC
A
A
A
A
A
A
3
4
5
6
7
8
7C197-35
Revised August 24, 2001
4
5
6
7
8
9
10
11
12
35
95
30
1314151617
Top View
3 2 1
7C197
LCC
CY7C197
28
27
408-943-2600
26
25
24
23
22
21
20
19
18
7C197-45
A
C197-3
NC
A
A
A
A
A
A
NC
12
16
15
14
13
11
10
OUT
45
30
) pin.

Related parts for CY7C197-35PC

CY7C197-35PC Summary of contents

Page 1

... The output pin stays in a high-impedance state when Chip Enable (CE) is HIGH or Write Enable (WE) is LOW. The CY7C197 utilizes a die coat to insure alpha immunity. Pin Configurations DI DIP/SOJ ...

Page 2

... MAX Max > V 0.3V [3] V > < 0. [1] 0. Ambient Temperature +70 C 7C197-12 7C197-15 Min. Max. Min. 2.4 2.4 0.4 2 0.3V 0.5 0.8 0 300 150 power-up, otherwise I will exceed values given CY7C197 + 0. 10% Max. Unit V 0 +0.3V 0 300 mA 140 Page ...

Page 3

... C197-4 (b) 1.90V = < for the -20 and slower speeds. 7C197-20 7C197-25, 35, 45 Min. Max. Min. 2.4 2.4 0.4 2 0.3V 0.5 0.8 0 300 135 Max ALL INPUT PULSES 3.0V 90% 10% GND < CY7C197 Max. Unit V 0 0.3V 0 300 Unit pF pF 90% 10% < C197-5 Page ...

Page 4

... HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05049 Rev. ** [6] 7C197-15 7C197- and 30-pF load capacitance less than t and t is less than t HZCE LZCE HZWE CY7C197 7C197-25 7C197-35 7C197- for any given device. LZWE Page Unit ns ...

Page 5

... DATA IN DATA OUT Notes: 10 HIGH for read cycle. 11. Device is continuously selected Document #: 38-05049 Rev OHA ACE 50% [ SCE HZWE DATA UNDEFINED . IL DATA VALID t HZCE IMPEDANCE DATA VALID PWE DATA VALID t LZWE HIGH IMPEDANCE CY7C197 C197-6 HIGH ICC ISB C197-7 C197-8 Page ...

Page 6

... Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled) ADDRESS DATA IN DATA OUT Note: 12 goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05049 Rev. ** [9, 12 SCE PWE t SD DATA VALID CY7C197 HIGH IMPEDANCE C197-9 Page ...

Page 7

... OUTPUT VOLTAGE(V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 0.0 1.0 2.0 125 OUTPUT VOLTAGE(V) NORMALIZED I vs. CYCLE TIME CC 1.25 V =5. =25°C A 1.00 V =0.5V IN 0.75 0.50 800 1000 CYCLE FREQUENCY (MHz) CY7C197 =5.0V =25°C 3.0 4.0 =5.0V =25°C 3.0 4.0 40 Page ...

Page 8

... Data In Ordering Information Speed (ns) Ordering Code 12 CY7C197-12PC CY7C197-12VC 15 CY7C197-15PC CY7C197-15VC 20 CY7C197-20PC CY7C197-20VC 25 CY7C197-25PC CY7C197-25VC 35 CY7C197-35PC CY7C197-35VC 45 CY7C197-45PC CY7C197-45VC Document #: 38-05049 Rev. ** Input/Output Deselect/Power-Down Read Write Package Name Package Type P13 24-Lead (300-Mil) Molded DIP V13 24-Lead Molded SOJ P13 24-Lead (300-Mil) Molded DIP ...

Page 9

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 24-Lead (300-Mil) Molded DIP P13/P13A 24-Lead (300-Mil) Molded SOJ V13 CY7C197 51-85013-A 51-85030-A Page ...

Page 10

... Document Title: CY7C197 256K x 1 Static RAM Document Number: 38-05049 Issue REV. ECN NO. Date ** 107151 09/10/01 Document #: 38-05049 Rev. ** Orig. of Change Description of Change SZV Change from Spec number: 38-00078 to 38-05049 CY7C197 Page ...

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