CS5530A-UCE Advanced Micro Devices, CS5530A-UCE Datasheet

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CS5530A-UCE

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CS5530A-UCE
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AMD Geode CS5530A Companion Device
Manufacturer
Advanced Micro Devices
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AMD Geode
CS5530A
Companion Device Data Book
October 2003
Publication ID: May 2001, Revision 1.1
AMD Geode™ CS5530A Companion Device Data Book

Related parts for CS5530A-UCE

CS5530A-UCE Summary of contents

Page 1

... AMD Geode Companion Device Data Book October 2003 Publication ID: May 2001, Revision 1.1 AMD Geode™ CS5530A Companion Device Data Book ™ CS5530A ...

Page 2

... XpressAUDIO are trademarks of Advanced Micro Devices, Inc. Microsoft, Windows, and Windows NT are registered trademarks of Microsoft Corporation in the U.S. and/ or other jurisdictions. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 2 AMD Geode™ CS5530A Companion Device Data Book ...

Page 3

... Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.0 AMD Geode™ CS5530A Companion Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.0 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 Processor Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 ISA Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4 AT Compatibility Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 IDE Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7 XpressAUDIO™ ...

Page 4

... AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 6.6 Display Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 7.0 Test Mode Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 7.1 NAND Tree Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 7.2 I/O Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 8.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Appendix A Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 A.1 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 4 AMD Geode™ CS5530A Companion Device Data Book Contents ...

Page 5

... PCI and IRQ Interrupt Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 4-17. SMI Generation for NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 4-18. External RTC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 4-19. CS5530A and IDE Channel Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 4-20. PRD Table Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Figure 4-21. AC97 Signal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 4-22. ...

Page 6

... Revision 1.1 6 AMD Geode™ CS5530A Companion Device Data Book List of Figures ...

Page 7

... I/O Recovery Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 4-39. ROM Interface Related Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 4-40. DMA Shadow Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 4-41. PIT Control and I/O Port 061h Associated Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 4-42. PIT Shadow Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 AMD Geode™ CS5530A Companion Device Data Book Revision 1.1 List of Tables 7 ...

Page 8

... Table 5-17. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers . . . . . . . . . . . . . . . . . . 181 Table 5-18. F2 Index xxh: PCI Header Registers for IDE Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 184 Table 5-19. F2BAR+I/O Offset xxh: IDE Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 8 AMD Geode™ CS5530A Companion Device Data Book List of Tables ...

Page 9

... Table 6-3. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Table 6-4. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Table 6-5. System Conditions Used to Determine CS5530A’s Current Used During the “On” State . . 237 Table 6-6. DC Characteristics During Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Table 6-7. Drive Level and Measurement Points for AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 239 Table 6-8 ...

Page 10

... Revision 1.1 10 AMD Geode™ CS5530A Companion Device Data Book List of Tables ...

Page 11

... AMD’s WebPAD system, and thermal design is eased allowing for fanless system design. The CS5530A is a PCI-to-ISA bridge (South Bridge), ACPI- compliant chipset that provides AT/ISA style functionality. The device contains state-of-the-art power management that enables systems, especially battery powered systems, to significantly reduce power consumption ...

Page 12

... Digital RGB interface drives TFT panels or standard NTSC/PAL encoders — 1280x1024 @ 85 Hz Universal Serial Bus Two independent USB interfaces: — Open Host Controller Interface (OpenHCI) specification compliant — Second generation proven core design AMD Geode™ CS5530A Companion Device Data Book ...

Page 13

... The traditional south bridge functionality included in the CS5530A companion device has been designed to support the GX1processor. When combined with a GX1 processor, the CS5530A provides a bridge which supports a standard ISA bus and system ROM. As part of the video subsystem, the CS5530A provides MPEG video acceleration and a digital RGB interface, to allow direct connection to TFT LCD panels ...

Page 14

... Revision 1.1 2.2 PCI Bus Interface The CS5530A provides a PCI bus interface that is both a slave for PCI cycles initiated by the CPU or other PCI mas- ter devices, and a non-preemptable master for DMA trans- fer cycles. The chip also is a standard PCI master for the IDE controllers and audio I/O logic ...

Page 15

... The CS5530A provides an AC97 Specification Revision 1.3, 2.0, and 2.1 compatible interface. Any AC97 codec which supports an independent input and output sample rate conversion interface can be used with the CS5530A. This type of codec allows for a design which meets the requirements for PC97 and PC98-compliant audio as defined by Microsoft Corporation ...

Page 16

... Revision 1.1 2.8 Display Subsystem Extensions The CS5530A incorporates extensions to the GX1 proces- sor’s display subsystem. These include: • Video Accelerator — Buffers and formats input YUV video data from the processor — 8-bit interface to the processor — X & Y scaler with bilinear filter — ...

Page 17

... Architecture Overview 2.9 Clock Generation In a CS5530A/GX1 processor based system, the CS5530A generates only the video DOT clock (DCLK) for the CPU and the ISA clock. All other clocks are generated by an external clock chip. The ISACLK is created by dividing the PCICLK. For ISA compatibility, the ISACLK nominally runs at 8 ...

Page 18

... Revision 1.1 18 Architecture Overview AMD Geode™ CS5530A Companion Device Data Book ...

Page 19

... Signal Definitions This section defines the signals and describes the external interface of the Geode CS5530A. Figure 3-1 shows the pins organized by their functional groupings (internal test and electrical pins are not shown). INTR SMI# IRQ13 PSERIAL CPU Interface SUSP# SUSPA# SUSP_3V ...

Page 20

... The tables in this section use several common abbrevia- tions. Table 3-1 lists the mnemonics and their meanings. Figure 3-2 shows the pin assignment for the CS5530A with Tables 3-2 and 3-3 listing the pin assignments sorted by pin number and alphabetically by signal name, respectively. ...

Page 21

... DRQ2 SA18 IOR# IRQ5 IRQ8# IRQ4 IRQ10 SBHE# DRQ0 MEMR# DRQ6 0WS# CHRDY SA17 IRQ1 IRQ6 TC CS16# IRQ12 IRQ11 Order Number: CS5530A-UCE Revision 1 AD12 AD10 AD15 PAR SERR# DVSL# C/BE2# AD17 AD16 C/BE0# AD11 AD14 C/BE1# PERR# TRDY# IRDY# AD18 AD19 ...

Page 22

... D17 V DD D18 AD8 D19 V SS D20 V SS D21 V DD D22 V SS D23 V SS D24 GNT# AMD Geode™ CS5530A Companion Device Data Book Signal Definitions Signal Name Pin Limited ISA Master No. ISA Mode Mode D25 AD26 D26 C/BE3# E1 FP_HSYNC_OUT SMEMW# E2 FP_DATA10 ...

Page 23

... T23 V DD T24 IDE_DACK1# T25 IDE_IOW1# T26 IDE_DACK0 (DAC) DD1 U2 V _USB DD U3 SYNC U4 SDATA_IN AMD Geode™ CS5530A Companion Device Data Book Signal Name Pin Limited ISA Master No. ISA Mode Mode U23 IDE_DATA7 U24 IDE_DATA6 U25 IDE_ADDR0 U26 IDE_ADDR1 V1 SDATA_OUT ...

Page 24

... AF5 SA6/SD6 SD6 AF6 SA4/SD4 SD4 AF7 DACK3# AF8 DACK2# AF9 BALE AF10 ZEROWS# AF11 IOCHRDY AF12 SA17 AMD Geode™ CS5530A Companion Device Data Book Signal Definitions Signal Name Pin Limited ISA Master No. ISA Mode Mode AF13 IRQ1 AF14 IRQ6 ...

Page 25

... BALE O BIT_CLK I C/BE0# I/O C/BE1# I/O C/BE2# I/O C/BE3# I/O CLK_14MHZ I (SMT) CLK_32K I/O CPU_RST O AMD Geode™ CS5530A Companion Device Data Book Signal Name Buffer Pin Limited ISA 2 Type No. Mode PCI A15 DACK0# PCI D14 DACK1# PCI C16 DACK2# PCI ...

Page 26

... IDE AD2 IDE AC2 IDE R26 NC IDE R25 NC IDE AD2 5 NC IDE AE26 NC AMD Geode™ CS5530A Companion Device Data Book Signal Definitions ISA Master Pin Buffer Pin 1 2 Mode Type Type No. O IDE R24 O IDE T25 O IDE W25 I PCI A14 ...

Page 27

... I PIXEL21 I PIXEL22 I PIXEL23 I PLLAGD I, Analog PLLDGN I, Analog PLLDVD I, Analog PLLTEST -- PLLVAA I, Analog POR# I POWER_EN O PSERIAL I AMD Geode™ CS5530A Companion Device Data Book Signal Name Buffer Pin Limited ISA 2 Type No. Mode -- AD2 REQ# -- AD3 SA0/SD0 -- AE1 SA1/SD1 -- AE2 SA2/SD2 -- AF1 SA3/SD3 ...

Page 28

... AC4 -- AC5 -- AC9 -- AD2 0 -- C18 -- C21 -- D19 -- D20 -- D22 -- D23 -- E23 -- E4 -- F23 AMD Geode™ CS5530A Companion Device Data Book Signal Definitions ISA Master Pin Buffer Pin 1 2 Mode Type Type No. GND -- G23 GND -- H23 GND -- H4 GND -- J23 GND -- K23 GND -- K4 ...

Page 29

... This is only used if interfacing to a compatible digital NTSC/PAL encoder device. DOT Clock DOT clock is generated by the CS5530A and typically connects to the pro- cessor to create the clock used by the graphics subsystem. The minimum frequency of DCLK is 10 MHz and the maximum is 200 MHz. However, when DCLK is used as the graphics subsystem clock, the Geode processor determines the maximum DCLK frequency ...

Page 30

... INTR should be asserted. I Power Management Serial Interface PSERIAL is the unidirectional serial data link between the GX1 processor and the CS5530A. An 8-bit serial data packet carries status on power man- agement events within the CPU. Data is clocked synchronous to the PCI- CLK input clock. CPU Suspend SUSP# asserted requests that the CPU enters Suspend mode and the CPU asserts SUSPA# after completion ...

Page 31

... The USB controller uses INTA# as its output signal. Refer to PCIUSB Index 3Dh. PCI Bus Request The CS5530A asserts REQ# in response to a DMA request or ISA master request to gain ownership of the PCI bus. The REQ# and GNT# signals are used to arbitrate for the PCI bus. ...

Page 32

... IRDY# is driven by the master to indicate valid data on a write transaction, or that it is ready to receive data on a read transaction. When the CS5530A is a PCI slave, IRDY input that can delay the beginning of a write transaction or the completion of a read transaction. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. ...

Page 33

... PCI master during a read data phase. When the CS5530A is a PCI master, PERR output during read trans- fers and an input during write transfers. When the CS5530A is a PCI slave, PERR input during read transfers and an output during write trans- fers ...

Page 34

... Controls the direction of the external 5.0V tolerant transceiver on bits [15:0] of the SA bus. When low, the SA bus is driven out. When high, the SA bus is driven into the CS5530A by the external transceiver. Limited ISA Mode: Flat Panel Data Port Line 16 Refer to Section 3.2.11 "Display Interface" on page 40 for this signal’s defini- tion ...

Page 35

... Function selection is made through F0 Index 53h[2 SMEMR RTCALE. System Bus High Enable The CS5530A or ISA master asserts SBHE# to indicate that SD[15:8] will be used to transfer a byte at an odd address. SBHE output during non-ISA master DMA operations driven as the inversion of AD0 during 8-bit DMA cycles forced low for all 16-bit DMA cycles ...

Page 36

... Description I/O Channel Ready IOCHRDY deasserted indicates that an ISA slave requires additional wait states. When the CS5530A is an ISA slave, IOCHRDY is an output indicating addi- tional wait states are required. I Zero Wait States ZEROWS# asserted indicates that an ISA 8- or 16-bit memory slave can shorten the current cycle ...

Page 37

... Pin Signal Name No. Type KBROMCS# AE4 O AMD Geode™ CS5530A Companion Device Data Book Description I DMA Request - Channels 7 through 5 and 3 through 0 DRQ inputs are asserted by ISA DMA devices to request a DMA transfer. The request must remain asserted until the corresponding DACK is asserted. ...

Page 38

... Read Cycle — STROBE0 and STROBE1 Write Cycle — DMARDY0# and DMARDY1# I DMA Request Channels 0 and 1 The DREQ is used to request a DMA transfer from the CS5530A. The direc- I tion of the transfers are determined by the IDE_IOR/IOW signals. DMA Acknowledge Channels 0 and 1 The DACK# acknowledges the DREQ request to initiate DMA transfers. ...

Page 39

... AD22 GPIO3 AF24 I/O GPIO2 AF25 I/O AMD Geode™ CS5530A Companion Device Data Book Description Power Enable This pin enables the power to a self-powered USB hub. I Over Current This pin indicates the USB hub has detected an overcurrent on the USB. USB Port 1 Data Positive This pin is the Universal Serial Bus Data Positive for port 1 ...

Page 40

... Otherwise, the pixel data is sent in RGB 5:6:5 format which has been dithered by the processor. The other eight bits are used in conjunction with VID_DATA[7:0] to provide 16-bit video data. This bus is sampled by the PCLK input. AMD Geode™ CS5530A Companion Device Data Book Signal Definitions ...

Page 41

... DAC) Analog EXTVREFIN T2 (Video DAC) Analog AMD Geode™ CS5530A Companion Device Data Book Description I Display Enable Input This signal qualifies active data on the pixel input port used to qualify active pixel data for all display modes and configurations and is not specific to flat panel display ...

Page 42

... ISA Master Mode: System Address Bus Lines 15 through 0 These pins function as SA[15:0] and the pins designated as SA/SD[15:0] function only as SD[15:0]. Note that SA[19:16] are dedicated address pins and GPIO[7:4] function as SA[23:20] only. AMD Geode™ CS5530A Companion Device Data Book Signal Definitions (pin U1) and AV (pin N4). DD1 DD3 (pin P2) ...

Page 43

... CRT. -- ISA Master Mode: No Function In the ISA Master mode of operation, the CS5530A can not support TFT flat panels or TV controllers. Limited ISA Mode: Flat Panel Vertical Sync Output This is the vertical sync for an attached active matrix TFT flat panel. This represents a delayed version of the input flat panel vertical sync signal with the appropriate pipeline delay relative to the pixel data ...

Page 44

... VID_DATA input port. If the VID_RDY signal is also asserted, the data will advance. Video Ready This signal indicates that the CS5530A is ready to receive the next piece of video data on the VID_DATA port. If the VID_VAL signal is also asserted, the data will advance. AMD Geode™ CS5530A Companion Device Data Book Signal Definitions supply to an attached flat panel ...

Page 45

... Table 3-3 (Total of 20) 3.2.14 Internal Test and Measurement Pin Signal Name No. TEST D3 AMD Geode™ CS5530A Companion Device Data Book Description -- PLLTEST Internal test pin. This pin should not be connected for normal operation. I Analog PLL Power ( PLLVAA is the analog positive rail power connection to the PLL. ...

Page 46

... Revision 1.1 46 Signal Definitions AMD Geode™ CS5530A Companion Device Data Book ...

Page 47

... Note that this Functional Description section of the data book describes many of the registers used for configuration of the CS5530A; however, not all registers are reported in detail. Some tables in the following subsections show only the bits (not the entire register) associated with a specific function being discussed ...

Page 48

... Revision 1.1 4.1 Processor Interface The CS5530A interface to the GX1 processor consists of seven miscellaneous connections, the PCI bus interface signals, plus the display controller connections. Figure 4-1 shows the interface requirements. Note that the PC/AT leg- acy pins NMI, WM_RST, and A20M are all virtual functions executed in SMM (System Management Mode) by the BIOS ...

Page 49

... CS5530A Processor Companion Device Note: Connect PIXEL[17:16] PIXEL[9:8], and PIXEL[1:0] on the CS5530A to ground. See Figure 4-3 "PIXEL Signal Connections" on page 50. Figure 4-2. Portable/Desktop Display Subsystem Configurations AMD Geode™ CS5530A Companion Device Data Book The CS5530A also supports both portable and desktop configurations ...

Page 50

... For more information on the Serial Packet Register refer- enced in Table 4-1, refer to the AMD Geode™ GX1 Proces- sor Data Book. The CS5530A decodes the serial packet after each trans- mission and performs the power management tasks related to video retrace. Table 4-1. GX1 Processor Serial Packet Register ...

Page 51

... Wait Cycle Control (Read Only): This function is not supported in the CS5530A always disabled (always reads 0). 6 Parity Error: Allow the CS5530A to check for parity errors on PCI cycles for which target, and to assert PERR# when a parity error is detected Disable (Default Enable. 5 VGA Palette Snoop Enable (Read Only): This function is not supported in the CS5530A always disabled (always reads 0) ...

Page 52

... Subtractive Decode: These bits determine the point at which the CS5530A accepts cycles that are not claimed by another device. The CS5530A defaults to taking subtractive decode cycles in the default cycle clock, but can be moved up to the Slow Decode cycle point if all other PCI devices decode in the fast or medium clocks. Disabling subtractive decode must be done with care, as all ISA and ROM cycles are decoded subtractively ...

Page 53

... Table 4-5. PERR#/SERR# Associated Register Bits Bit Description F0 Index 04h-05h 6 Parity Error: Allow the CS5530A to check for parity errors on PCI cycles for which target, and to assert PERR# when a parity error is detected Disable (Default Enable. F0 Index 06h-07h 15 Detected Parity Error: This bit is set whenever a parity error is detected. ...

Page 54

... F0 Index 43h 1 PCI Retry Cycles: When the CS5530A is a PCI target and the PCI buffer is not empty, allow the PCI bus to retry cycles Disable Enable. This bit works in conjunction with PCI bus delayed transactions bit. F0 Index 42h[5] must = 1 for this bit to be valid. ...

Page 55

... POR# CPU_RST PCI_RST# POR# minimum pulse width for CS5530A only (i.e., not a system specification) = 100 µs and 14 MHz must be running. AMD Geode™ CS5530A Companion Device Data Book At any state, Power-on/Resume/Reset, the 14.31818 MHz oscillator must be active for the resets to function. ...

Page 56

... DCLK is used as the graphics subsystem clock. For applications that do not use the GX1 processor’s graphics subsystem, this is an available clock for general purpose use. The system clock distribution for a CS5530A/GX1 based system is shown in Figure 4-6. AMD Geode™ CS5530A Companion Device ...

Page 57

... N = 66: Bits [22:12] = 073h (found in Table 4-10), clear bit 23 Result: DCLK = 135 AMD Geode™ CS5530A Companion Device Data Book Revision 1.1 The BIOS has been provided with a complete table of divi- sor values for supported graphics clock frequencies. Many combinations of divider values and VCO frequencies are possible to achieve a certain output clock frequency ...

Page 58

... PD divisor of 1* 10111 = PD divisor of 3 100 = ID divisor of 6 001 = ID divisor of 3 110 = ID divisor of 8 011 = ID divisor of 5 AMD Geode™ CS5530A Companion Device Data Book Resets and Clocks Reset Value = 00000000h 11000 = PD divisor of 11 11001 = PD divisor of 21 11010 = PD divisor of 15 ...

Page 59

... AMD Geode™ CS5530A Companion Device Data Book Reg. Reg. Reg. Value N Value N Value 331 247 7D0 196 143 662 246 7A1 195 286 ...

Page 60

... Save-to-RAM — Extreme 3 Volt Suspend with only the contents of RAM still powered 4.4.1.1 On System is running and the CPU is actively executing code. Base Address Register — F1BAR (R/W) AMD Geode™ CS5530A Companion Device Data Book Power Management Reset Value = 00000000h ...

Page 61

... SMI handler reads the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The latter is the preferred method. The IRQ speedup method is provided for software compatibility with earlier revisions of the CS5530A. This bit has no effect if the Suspend Modulation feature is disabled (bit 0 = 0). ...

Page 62

... CPU Clock Stop Normal SUSP#/ SUSPA# handshake Full system Suspend. Note: This register configures the CS5530A to support a 3 Volt Suspend. Setting bit 0 causes the SUSP_3V pin to assert after the appropriate conditions, stopping the system clocks. A delay programmable (bits 7:4) to allow for a delay for the clock chip and CPU PLL to stabilize when an event Resumes the system ...

Page 63

... Port 061h, SMI, and/or accessing the graphics controller. Since the graphics controller is integrated in the GX1 pro- cessor, the indication of graphics activity is sent to the CS5530A via the serial link (see Section 4.1.2 "PSERIAL Pin Interface" on page 50 for more information on serial link) and is automatically decoded. Graphics activity is ...

Page 64

... IRQ Speedup Timer Count Register (R/W) Video Speedup Timer Count Register (R/W) Suspend Modulation OFF Count Register (R/W) Suspend Modulation ON Count Register (R/W) AMD Geode™ CS5530A Companion Device Data Book Power Management Reset Value = 00h Reset Value = 00h Reset Value = 00h ...

Page 65

... SMI handler reads the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The latter is the preferred method. The IRQ speedup method is provided for software compatibility with earlier revisions of the CS5530A. This bit has no effect if the Suspend Modulation feature is disabled (bit 0 = 0). ...

Page 66

... It is provided here to assist in a Save-to-Disk operation. 66 The PC/AT compatible floppy port is not part of the CS5530A floppy is attached on the ISA bus in a SuperI some other means, some of the FDC regis- ters are shadowed in the CS5530A because they cannot be safely read ...

Page 67

... IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external SMI source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530A pins can be used to wake- up the system from Suspend when the clocks are stopped. As long as the 32 KHz clock remains active, internal SMI events are also Resume events ...

Page 68

... Power Management Enable Register 1 (R/W) Power Management Enable Register 2 (R/W) Power Management Enable Register 3 (R/W) Miscellaneous Device Control Register (R/W) AMD Geode™ CS5530A Companion Device Data Book Power Management Reset Value = 00h Reset Value = 00h Reset Value = 00h ...

Page 69

... To enable this timer set F0 Index 81h[ Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[2]. AMD Geode™ CS5530A Companion Device Data Book Power Management Enable Register 2 (R/W) Power Management Enable Register 3 (R/W) Miscellaneous Device Control Register (R/W) Parallel / Serial Idle Timer Count Register (R/W) Revision 1 ...

Page 70

... Power Management Enable Register 2 (R/W) Power Management Enable Register 3 (R/W) Miscellaneous Device Control Register (R/W) Floppy Disk Idle Timer Count Register (R/W) AMD Geode™ CS5530A Companion Device Data Book Power Management Reset Value = 00h Reset Value = 00h Reset Value = 00h ...

Page 71

... To enable this timer set F0 Index 81h[ Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[0]. AMD Geode™ CS5530A Companion Device Data Book Power Management Enable Register 2 (R/W) Power Management Enable Register 3 (R/W) Miscellaneous Device Control Register (R/W) Revision 1 ...

Page 72

... Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[4]. 72 Power Management Enable Register 4 (R/W) Miscellaneous Device Control Register (R/W) AMD Geode™ CS5530A Companion Device Data Book Power Management Reset Value = 00h Reset Value = 00h Reset Value = 0000h ...

Page 73

... Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored. Note: A “1” mask bit means that the address bit is ignored for comparison. AMD Geode™ CS5530A Companion Device Data Book Power Management Enable Register 4 (R/W) ...

Page 74

... Note: A “1” mask bit means that the address bit is ignored for comparison. 74 Power Management Enable Register 4 (R/W) Power Management Enable Register 3 (R/W) User Defined Device 2 Control Register (R/W) AMD Geode™ CS5530A Companion Device Data Book Power Management Reset Value = 00h Reset Value = 00h Reset Value = 0000h ...

Page 75

... Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored. Note: A “1” mask bit means that the address bit is ignored for comparison. AMD Geode™ CS5530A Companion Device Data Book Power Management Enable Register 4 (R/W) ...

Page 76

... In a GX1 processor based system the graphics controller is embedded in the CPU, so video activity is communicated to the CS5530A via the serial connection (PSERIAL register, bit 0) from the processor. The CS5530A also detects accesses to standard VGA space on PCI (3Bxh, 3Cxh, 3Dxh and A000h-B7FFh) in the event an external VGA controller is being used. ...

Page 77

... Power Management 4.4.3.2 General Purpose Timers The CS5530A contains two general purpose timers, Gen- eral Purpose Timer 1 (F0 Index 88h) and General Purpose Timer 2 (F0 Index 8Ah). These two timers are similar to the Device Idle Timers in that they count down to zero unless re-triggered, and generate an SMI when they reach zero ...

Page 78

... F0 Index 92h[7] selects whether a rising falling-edge transition acts as a reload. For GPIO7 to work here, it must first be configured as an input (F0 Index 90h[7] = 0). 1:0 Reserved: Set General Purpose Timer 2 Count Register (R/W) AMD Geode™ CS5530A Companion Device Data Book Power Management Reset Value = 00h Reset Value = 00h ...

Page 79

... Timer SMI enable bit. V-ACPI I/O Register Space The register space designated as V-ACPI (Virtualized ACPI) I/O does not physically exist in the CS5530A. ACPI is supported in the CS5530A by virtualizing this register space. In order for ACPI to be supported, the V-ACPI mod- ule must be included in the BIOS. The register descriptions that follow are supplied here for reference only ...

Page 80

... Revision 1.1 4.4.3.4 General Purpose I/O Pins The CS5530A provides up to eight GPIO (general purpose I/O) pins. Five of the pins (GPIO[7:4] and GPIO1) have alternate functions. Table 4-31 shows the bits used for GPIO pin function selection. Each GPIO pin can be configured as an input or output. ...

Page 81

... Disable Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting Index 84h/F4h[1]. AMD Geode™ CS5530A Companion Device Data Book GPIO Control Register 1 (R/W) GPIO Control Register 2 (R/W) Revision 1.1 ...

Page 82

... For information regarding the location of the corresponding mirror register, refer to the note in the footer of the register description. Keep in mind, all SMI sources in the CS5530A are reported into the Top Level SMI Status Registers (F1BAR+Memory Offset 00h/02h); however, this discussion is regarding power management SMIs. For details regarding audio SMI events/reporting, refer to Section 4.7.2.2 " ...

Page 83

... GTMR_TRP_SMI Bits [8:0] Other_SMI Top Level Figure 4-7. General Purpose Timer and UDEF Trap SMI Tree Example AMD Geode™ CS5530A Companion Device Data Book SMM software reads SMI Header If Bit (Internal SMI) SMI Deasserted after all SMI Sources are Cleared (i ...

Page 84

... A read-only “Mirror” version of this register exists at F1BAR+Memory Offset 00h. If the value of the register must be read without clearing the SMI source (and consequently deasserting SMI), the Mirror register may be read instead. 84 Top Level SMI Status Register (RC) AMD Geode™ CS5530A Companion Device Data Book Power Management Reset Value = 0000h ...

Page 85

... GPIO3 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO3 pin No Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling Index 97h[0]. AMD Geode™ CS5530A Companion Device Data Book Revision 1.1 Reset Value = 0000h ...

Page 86

... Secondary Hard Disk Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the secondary hard disk No Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling Index 83h[6]. 86 Power Management Reset Value = 00h Reset Value = 00h AMD Geode™ CS5530A Companion Device Data Book ...

Page 87

... This register provides status on several miscellaneous power management events that generate SMIs, as well as the status of the Lid Switch. Reading this register clears the SMI status bits. A read-only (mirror) version of this register exists at F0 Index 87h. AMD Geode™ CS5530A Companion Device Data Book Revision 1.1 Reset Value = 00h ...

Page 88

... N/A 8Dh[7:0] A8h[15:0] 8Ch[7:0] N/A AMD Geode™ CS5530A Companion Device Data Book Power Management Second Level SMI Status/With Clear N/A F5h[3] F5h[2] F5h[1] F5h[7] F1BAR+Memory Offset 02h[6] ...

Page 89

... Memory Space: Allow the CS5530A to respond to memory cycles from the PCI bus Disable Enable (Default). 0 I/O Space: Allow the CS5530A to respond to I/O cycles from the PCI bus Disable Enable (Default). F0 Index 41h 2:1 Subtractive Decode: These bits determine the point at which the CS5530A accepts cycles that are not claimed by another device ...

Page 90

... Figure 4-8. Non-Posted PCI-to-ISA Access 90 PC/AT Compatibility Logic SA[23:0] are a concatenation of ISA LA[23:17] and SA[19:0] and perform equivalent functionality at a reduced pin count. Figure 4-8 shows the relationship between a PCI cycle and the corresponding ISA cycle generated. AMD Geode™ CS5530A Companion Device Data Book ...

Page 91

... BALE ISA IOR Delay 2 - IDE bus master - starts and completes 3 - End of ISA cycle Figure 4-9. PCI to ISA Cycles with Delayed Transaction Enabled AMD Geode™ CS5530A Companion Device Data Book Revision 1.1 See Section 4.2.6 "Delayed Transactions" on page 54 for additional information ...

Page 92

... SA[23:20], are multiplexed on GPIO[7:4]. The second mode of the ISA interface supports ISA bus masters, as shown in Figure 4-11. When the CS5530A is placed in the ISA Master mode, a large number of pins are redefined as shown in Table 4-37. In this mode of operation, the CS5530A cannot support TFT flat panels or TV controllers, since most of the signals used to support these functions have been redefined ...

Page 93

... When strapped for ISA Master mode, GPIO[7:4]/SA[23:20] are set to SA[23:20] and the settings in F0 Index 43h[2] are invalid. 2. These signals are: MEMW#, MEMR#, IOR#, IOW#, TC, AEN, DREQ[7:5, 3:0], DACK[7:5, 3:0]#, MEMCS16#, ZEROWS#, SBHE#, IOCS16#, IOCHRDY, ISACLK. 3. This resistor is used at boot time to determine the mode of the ISA bus. AMD Geode™ CS5530A Companion Device Data Book 2 ISA Control D ...

Page 94

... I/O data bus. Either the PCI bus master or the DMA controllers can become the bus owner. When the PCI bus master is the bus owner, the CS5530A data steering logic provides data conversion necessary for 8/16/32-bit transfers to and from 8/16-bit devices on either the ISA bus or the 8-bit registers on the on-chip I/O data bus ...

Page 95

... Revision 1.1 PCI arbiter. After the PCI bus has been granted, the respective DACK# is driven active. The CS5530A generates PCI memory read or write cycles in response to a DMA cycle. Figures 4-12 and 4-13 are examples of DMA memory read and memory write cycles. ...

Page 96

... The CS5530A positively decodes memory addresses 000F0000h-000FFFFFh (64 KB) FFFFFFFFh (256 KB) at reset. These memory cycles cause the CS5530A to claim the cycle, and generate an ISA bus memory cycle with KBROMCS# asserted. The CS5530A can also be configured to respond to memory addresses FF000000h-FFFFFFFFh 000E0000h-000FFFFFh (128 KB). ...

Page 97

... In this mode, the DMA controller continues to exe- cute transfer cycles until the I/O device drops DRQ to indi- cate its inability to continue providing data. For this case, the PCI bus is held by the CS5530A until a break in the transfers occurs. In cascade mode, the channel is connected to another DMA controller ISA bus master, rather than device ...

Page 98

... DRQ signal active high and the DACK# signal active low. DMA Shadow Registers The CS5530A contains a shadow register located at F0 Index B8h (Table 4-40) for reading the configuration of the DMA controllers. This read-only register can sequence to read through all of the DMA registers ...

Page 99

... F0 Index 50h[5] I/O Port 061h[0] A[1:0] XD[7:0] IOW# IOR# AMD Geode™ CS5530A Companion Device Data Book 4.5.4.2 Programmable Interval Timer The CS5530A contains an 8254-equivalent Programmable Interval Timer (PIT) configured as shown in Figure 4-14. The PIT has three timers/counters, each with an input fre- quency of 1 ...

Page 100

... Bits [7:6] of the command words are not used. 100 8254 Timer 0 RTC_IRQ# Coprocessor Figure 4-15. PIC Interrupt Controllers Table 4-42. PIT Shadow Register PIT Shadow Register (RO) AMD Geode™ CS5530A Companion Device Data Book PC/AT Compatibility Logic IRQ0 IR0 IRQ1 IR1 IRQ2 IR2 ...

Page 101

... Bit Description F0 Index 40h 7 PCI Interrupt Acknowledge Cycle Response: Allow the CS5530A responds to PCI interrupt acknowledge cycles Disable Enable. AMD Geode™ CS5530A Companion Device Data Book CPU. The interrupt controller then responds to the interrupt acknowledge (INTA) cycles from the CPU. On the first INTA ...

Page 102

... A write to this register resets the read sequence to the first register. The read sequence for the shadow register is listed in F0 Index B9h (Table 4-45). Table 4-45. PIC Shadow Register PIC Shadow Register (RO) AMD Geode™ CS5530A Companion Device Data Book PC/AT Compatibility Logic Reset Value = xxh ...

Page 103

... PC/AT Compatibility Logic 4.5.4.4 PCI Compatible Interrupts The CS5530A allows the PCI interrupt signals INTA#, INTB#, INTC#, and INTD# (also known in industry terms as PIRQx mapped internally to any IRQ signal with the PCI Interrupt Steering Registers 1 and 2, F0 Index 5Ch and 5Dh (Table 4-46). This reassignment does not disable the corresponding IRQ pin ...

Page 104

... Notes ICW1 - bit 3 in the PIC is set as level, it overrides this setting. 2. This bit is provided to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared). 104 Interrupt Edge/Level Select Register 1 (R/W) Interrupt Edge/Level Select Register 2 (R/W) AMD Geode™ CS5530A Companion Device Data Book PC/AT Compatibility Logic Reset Value = 00h Reset Value = 00h ...

Page 105

... This bit can only be set if ERR_EN (bit 2) is set 0. This bit is set 0 after a write to ERR_EN with after reset. 6 IOCHK# Status (Read Only I/O device reporting an error to the CS5530A No Yes. This bit can only be set if IOCHK_EN (bit 3) is set 0. This bit is set 0 after a write to IOCHK_EN with after reset. ...

Page 106

... The assertion of a fast keyboard reset (WM_RST SMI) is controlled by bit 0 in I/O Port 092h or by monitoring for the keyboard command sequence. If bit 0 is changed from the CS5530A generates a reset to the processor by generating a WM_RST SMI. When the WM_RST SMI occurs, the BIOS jumps to the Warm Reset vector. This bit Table 4-49 ...

Page 107

... Keyboard Controller Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 060h and 064h (and 062h/066h if enabled Subtractive Positive. Note: Positive decoding by the CS5530A speeds up the I/O cycle time. These I/O Ports do not exist in the CS5530A assumed that if positive decode is enabled, the port exists on the ISA bus. ...

Page 108

... The fast keyboard A20M# and CPU reset can be disabled through F0 Index 52h[7]. By default, bit 7 is cleared, and the fast keyboard A20M# and CPU reset monitor logic is active. If bit 7 is clear, the CS5530A forwards the com- mands to the keyboard controller. By default, the CS5530A forces the deassertion of A20M# during a warm reset ...

Page 109

... RTC Register Index: A write of this register sends the data out on the ISA bus and also causes RTCALE to be triggered. Note: This register is shadowed within the CS5530A and is read through the RTC Shadow Register (F0 Index BBh). I/O Port 071h (R/W) A read of this register returns the value of the register indexed by the RTC Address Register plus initiates a RTCCS#. ...

Page 110

... Description F0 Index 44h 3 IDE Controller Reset: Reset both of the CS5530A IDE controllers’ internal state machines Run Reset. This bit is level-sensitive and must be explicitly cleared remove the reset. 2 IDE Reset: Reset IDE bus Deassert IDE bus reset signal Assert IDE bus reset signal. ...

Page 111

... Bus Mastering IDE Base Address 6:0 Address Range (Read Only) AMD Geode™ CS5530A Companion Device Data Book IDE_ADDR[2:0] and IDE_CS# lines with respect to the read and write strobes (IDE_IOR# and IDE_IOW#). The PIO portion of the IDE registers is enabled through: • ...

Page 112

... Table 4-56. PIO Programming Registers Channel 0 Drive 0 PIO Register (R/W) Channel 0 Drive 1 PIO Register (R/W) Channel 1 Drive 0 PIO Register (R/W) Channel 1 Drive 1 PIO Register (R/W) AMD Geode™ CS5530A Companion Device Data Book IDE Controller Reset Value = 0000E132h (Note) Reset Value = 0000E132h Reset Value = 0000E132h ...

Page 113

... Bus Master Mode Two IDE bus masters are provided to perform the data transfers for the primary and secondary channels. The CS5530A off-loads the CPU and improves system perfor- mance in multitasking environments. The bus master mode programming interface is an exten- sion of the standard IDE programming model. This means ...

Page 114

... Bus Master Error: Has the bus master detected an error during data transfer No Yes. Write 1 to clear. 0 Bus Master Active (Read Only): Is the bus master active No Yes. 114 Reset Value = 00h Reset Value = 00h Reset Value = 00000000h Reset Value = 00h Reset Value = 00h AMD Geode™ CS5530A Companion Device Data Book IDE Controller ...

Page 115

... Memory Region Physical Base Address [31:4] (IDE Data Buffer Reserved O T AMD Geode™ CS5530A Companion Device Data Book 3) Software must fill the buffers pointed to by the PRDs with IDE data. 4) Write 1 to the Bus Master Interrupt bit and Bus Master Error (Status Register bits 2 and 1) to clear the bits ...

Page 116

... CS5530A drives the result of the CRC calcula- tion onto IDE_DATA[15:0] which is then strobed by the deassertion of IDE_DACK#. The IDE device compares the CRC result of the CS5530A to its own and reports an error if there is a mismatch. The timings for Ultra DMA/33 are programmed into the DMA control registers: • ...

Page 117

... Channel 1 Drive 1 MDMA/UDMA Control Register: Refer to F2BAR+I/O Offset 24h for bit descriptions. Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only. AMD Geode™ CS5530A Companion Device Data Book Channel 0 Drive 0 DMA Control Register (R/W) ...

Page 118

... The CS5530A audio hardware includes six PCI bus mas- ters (three for input and three for output) for transferring digitized audio between memory and the external codec. With these bus master engines, the CS5530A off-loads the CPU and improves system performance. The programming interface defines a simple scatter/gather mechanism allowing large transfer blocks to be scattered to or gathered from memory ...

Page 119

... PRD by adding 08h. When read, this register points to the next PRD. 1:0 Reserved: Set to 0. AMD Geode™ CS5530A Companion Device Data Book • Audio Bus Master 4 — Output to codec — PCI read — ...

Page 120

... Reserved PRD Table Address (R/W) Command Register (R/W) SMI Status Register (RC) Reserved PRD Table Address (R/W) AMD Geode™ CS5530A Companion Device Data Book XpressAUDIO™ Subsystem Reset Value = 00h Reset Value = 00h Reset Value = xxh Reset Value = 00000000h Reset Value = 00h ...

Page 121

... AMD Geode™ CS5530A Companion Device Data Book • EOT bit - If set in a PRD, this bit indicates the last entry in the PRD table (bit 31). The last entry in a PRD table must have either the EOT bit or the JMP bit set. A PRD can not have both the JMP and EOT bits set. • ...

Page 122

... Audio Buffer_1 to a specific slot(s) in the AC97 interface. Address_1 PRD_1 Size_1 PRD_2 Size_2 Address_2 PRD_3 Don’t Care Figure 4-20. PRD Table Example AMD Geode™ CS5530A Companion Device Data Book XpressAUDIO™ Subsystem Audio Size_1 Buffer_1 Audio Size_2 Buffer_2 ...

Page 123

... The CS5530A provides an AC97 Specification Revision 1.3, 2.0, and 2.1 compatible interface. Any AC97 codec that supports sample rate conversion (SRC) can be used with the CS5530A. This type of codec allows for a design which meets the requirements for PC97 and PC98-compli- ant audio as defined by Microsoft Corporation. ...

Page 124

... Codec Command Address: Address of the codec control register for which the command is being sent. This address goes in slot 1 bits [19:12] on SDATA_OUT. 23:22 CS5530A Codec Communication: Selects which codec to communicate with Primary codec 01 = Secondary codec Note: 00 and 01 are the only valid settings for these bits. ...

Page 125

... SMI stored in F3BAR+Memory Offset 14h[15]. The second access causes an SMI, and the data and address are captured normal trapped I/O. In Fast Path Write, the CS5530A responds to writes to the following addresses: 388h, 38Ah, and 38Bh registers ...

Page 126

... Bit 1 Source of SER_INTR_SMI SMI is I/O Trap Bit 0 I/O_TRAP_SMI Second Level Figure 4-22. Audio SMI Tree Example AMD Geode™ CS5530A Companion Device Data Book XpressAUDIO™ Subsystem Call internal SMI handler to take appropriate action F3BAR+Memory Offset 14h Read to Clear to determine third-level ...

Page 127

... SMI generation is enabled when Audio Bus Master 5 is enabled (F3BAR+Memory Offset 48h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 49h[0] = 1). AMD Geode™ CS5530A Companion Device Data Book Second Level Audio SMI Status Register (RC) Revision 1 ...

Page 128

... This is the second level of SMI status reporting. The next level (third level) of SMI status reporting is at F3BAR+Memory Offset 14h. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. Note: Reading this register does not clear the status bits. See F3BAR+Memory Offset 10h. 128 XpressAUDIO™ Subsystem AMD Geode™ CS5530A Companion Device Data Book ...

Page 129

... Note: For the four SMI status bits (bits [13:10]), if the activity was a fast write to an even address, no SMI is generated regardless of the DMA, MPU, or sound card status. If the activity was a fast write to an odd address, an SMI is generated but bit 13 is set AMD Geode™ CS5530A Companion Device Data Book Revision 1.1 ...

Page 130

... Fast Path Write Enable: Fast Path Write (an SMI is not generated on certain writes to specified addresses Disable Enable. In Fast Path Write, the CS5530A responds to writes to the following addresses: 388h, 38Ah and 38Bh; 2x0h, 2x2h, and 2x8h. 10:9 Fast Read: These two bits hold part of the response that the CS5530A returns for reads to several I/O locations. ...

Page 131

... XpressAUDIO™ Subsystem 4.7.2.3 IRQ Configuration Registers The CS5530A provides the ability to set and clear IRQs internally through software control. If the IRQs are config- ured for software control, they will not respond to external hardware. There are three registers provided for this fea- ture: • ...

Page 132

... Reserved: Set Mask Internal IRQ5 Disable Enable. 4 Mask Internal IRQ4 Disable Enable. 3 Mask Internal IRQ3 Disable Enable. 2:0 Reserved: Set to 0. 132 Internal IRQ Mask Register (Write Only) AMD Geode™ CS5530A Companion Device Data Book XpressAUDIO™ Subsystem Reset Value = xxxxh ...

Page 133

... Display Subsystem Extensions 4.8 Display Subsystem Extensions The CS5530A incorporates extensions to the GX1 proces- sor’s’ display subsystem. These include: • Video Interface Configuration Registers — Line Buffers — Video Port Protocol — Video Format — X and Y Scaler / Filter — Color-Space-Converter • ...

Page 134

... VID_RDY to indicate that a line buffer is free to accept the next line. When both VID_VAL advances. The VID_RDY signal is driven by the CS5530A one clock early to the processor while the VID_VAL signal is driven by the processor coincident with valid data on VID_DATA. A sample timing diagram is shown in Figure 4-24. ...

Page 135

... Video Register Update: Allow video position and scale registers to be updated simultaneously on next occurrence of vertical sync Disable Enable. 0 Video Enable: Video acceleration hardware Disable Enable. AMD Geode™ CS5530A Companion Device Data Book [3:2] in the Video Configuration Register (F4BAR+Memory Offset 00h[3:2]). The decode for these bits is shown in Table 4-72. ...

Page 136

... Revision 1.1 4.8.2.4 X and Y Scaler / Filter The CS5530A supports horizontal and vertical scaling of the video stream up to eight times the source resolution. The scaler uses a Digital-Differential-Analyzer (DDA) based upon the values programmed in the Video Scale Register (F4BAR+Memory Offset 10h, see Table 4-73) ...

Page 137

... The CS5530A is capable of displaying graphics reso- lutions up to 1600x1200 at color depths bits per pixel (bpp) while simultaneously overlaying a video window. However, system maximum resolution is not determined by the CS5530A since it is not the source of the graphics data and timings. Video X Register (R/W) Video Y Register (R/W) Table 4-75 ...

Page 138

... Configuration for this feature and the display interface are through the Display Configuration Register (F4BAR+Mem- ory Offset 04h). Table 4-76 shows the bit formats for this register. Display Configuration Register (R/W) AMD Geode™ CS5530A Companion Device Data Book Display Subsystem Extensions Reset Value = 00000000h ...

Page 139

... Flat Panel Support The CS5530A also interfaces directly to industry standard 18-bit Active Matrix Thin-Film-Transistor (TFT) flat panels. The CS5530A includes 24-bit to 18-bit dithering logic to increase the apparent number of colors displayed on 18-bit flat panels. In addition, the CS5530A incorporates power sequencing logic to simplify the design of a portable system. ...

Page 140

... If HOLD_REQ# is high, it uses pin AD27 as its IDSEL input, appearing as Device #11h in a Geode system. The USB core is also affected by some bits in registers belonging to the other (Chipset) device of the CS5530A. In particular, the USB device can be disabled through the Chipset device, F0 Index 43h[0], and its IDSEL can be ...

Page 141

... USB clock generators is also used to wake the 48 MHz clock source. Currently, the RemoteWakeupConnected and RemoteWakeupEnable bits in the HcControl register are not implemented. AMD Geode™ CS5530A Companion Device Data Book Revision 1.1 Table 4-78. USB Controller Registers USB BAR+ Memory ...

Page 142

... Revision 1.1 142 Universal Serial Bus Support AMD Geode™ CS5530A Companion Device Data Book ...

Page 143

... Register Descriptions The Geode CS5530A is a multi-function device. Its register space can be broadly divided into four categories in which specific types of registers are located: 1) Chipset Register Space (F0-F4) 2) USB Controller Register Space (PCIUSB) 3) ISA Legacy I/O Register Space (I/O Port) 4) V-ACPI I/O Register Space (I/O Port) ...

Page 144

... Configuration Data Register. To access PCI configuration space, write the Configuration Address (0CF8h) Register with data that specifies the CS5530A as the device on PCI being accessed, along with the configuration register offset. On the following cycle, a Table 5-1. PCI Configuration Address Register (0CF8h) 31 ...

Page 145

... Register Summary The tables in this subsection summarize all the registers of the CS5530A. Included in the tables are the register’s reset val- ues and page references where the bit formats are found. Table 5-2. Function 0: PCI Header and Bridge Configuration Registers Summary ...

Page 146

... AMD Geode™ CS5530A Companion Device Data Book Reference (Table 5-15) Page 169 Page 169 Page 169 Page 169 Page 170 Page 170 Page 170 Page 171 Page 171 ...

Page 147

... Note: The registers located at F1BAR+Memory Offset 50h-FFh can also be accessed at F0 Index 50h-FFh. The pre- ferred method is to program these registers through the F0 Register Space. Refer to Table 5-2 "Function 0: PCI Header and Bridge Configuration Registers Summary" on page 145 for summary information. AMD Geode™ CS5530A Companion Device Data Book Revision 1.1 Reference ...

Page 148

... AMD Geode™ CS5530A Companion Device Data Book Reference (Table 5-18) Page 184 Page 184 Page 184 Page 184 Page 184 Page 184 Page 184 Page 184 Page 184 ...

Page 149

... RC Audio Bus Master 3 SMI Status Register 3Ah-3Bh -- -- Reserved 3Ch-3Fh 32 R/W Audio Bus Master 3 PRD Table Address AMD Geode™ CS5530A Companion Device Data Book Revision 1.1 Reset Reference Value (Table 5-20) 1078h Page 188 0103h Page 188 0000h Page 188 ...

Page 150

... AMD Geode™ CS5530A Companion Device Data Book Reference (Table 5-21) Page 196 Page 196 Page 196 Page 197 Page 197 Page 197 Page 197 Page 197 Page 197 ...

Page 151

... RO HcFmNumber 40h-43h 32 R/W HcPeriodicStart 44h-47h 32 R/W HcLSThreshold 48h-4Bh 32 R/W HcRhDescriptorA AMD Geode™ CS5530A Companion Device Data Book Revision 1.1 Reference Reset Value (Table 5-25) 0E11h Page 205 A0F8h Page 205 0000h Page 205 0280h Page 205 06h Page 206 ...

Page 152

... Reset Value 00000000h 00000000h 00000628h 01000002h 00000000h xxh 00000000h 000000xxh 000000xxh 00000000h AMD Geode™ CS5530A Companion Device Data Book Reference (Table 5-26) Page 211 Page 211 Page 212 Page 213 Page 213 Page 213 Page 214 Page 214 Page 214 ...

Page 153

... R/W External Keyboard Controller Command Register 066h R/W External Keyboard Controller Mailbox Register 092h R/W Port A Control Register AMD Geode™ CS5530A Companion Device Data Book Revision 1.1 Reference Page 217 Page 217 Page 217 Page 218 Page 218 Page 218 ...

Page 154

... GPE0_STS: General Purpose Event 0 Status Register GPE0_EN: General Purpose Event 0 Enable Register SETUP_DATA: Setup Data Register (V-ACPI internal data register) Reserved: For Future V-ACPI Implementations AMD Geode™ CS5530A Companion Device Data Book Register Summary Reference Page 222 Page 222 Page 223 ...

Page 155

... Wait Cycle Control (Read Only): This function is not supported in the CS5530A always disabled (always reads 0). 6 Parity Error: Allow the CS5530A to check for parity errors on PCI cycles for which target, and to assert PERR# when a parity error is detected Disable (Default Enable. 5 VGA Palette Snoop Enable (Read Only): This function is not supported in the CS5530A always disabled (always reads 0) ...

Page 156

... DEVSEL# timing Fast Medium Slow Reserved 8 Data Parity Detected: This bit is set when: 1) The CS5530A asserted PERR# or observed PERR# asserted. 2) The CS5530A is the master for the cycle in which a parity error occurred and the Parity Error bit is set (F0 Index 04h[6] = 1). Write 1 to clear. 7 Fast Back-to-Back Capable (Read Only target, the CS5530A is capable of accepting fast back-to-back transactions Disable ...

Page 157

... Note: Bits 6 and 5 emulate the behavior of first generation SIO devices developed for PCI. They should normally remain cleared. Index 41h 7 Burst to Beat: If this bit is set to 1, the CS5530A performs a single access from the PCI bus. If set to 0, burst accesses are enabled IDE Configuration Trap Disable ...

Page 158

... If F0 Index 43h bit 6 or bit 2 is set to 1, then pin AD22 = SA20. 1 PCI Retry Cycles: When the CS5530A is a PCI target and the PCI buffer is not empty, allow the PCI bus to retry cycles Disable Enable. This bit works in conjunction with PCI bus delayed transactions bit. F0 Index 42h[5] must = 1 for this bit to be valid. ...

Page 159

... Note: The RTC Index Shadow Register (F0 Index BBh) is independent of the setting of this bit. 1 Reserved: Set to 1 after register reset. Failure to do this leaves IRQ13 in an unsupported mode. AMD Geode™ CS5530A Companion Device Data Book 100 = Divide by five 101 = Divide by six ...

Page 160

... Real Time Clock Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 070h-7Fh Subtractive Positive. Note: Positive decoding by the CS5530A speeds up the I/O cycle time. These I/O Ports do not exist in the CS5530A assumed that if positive decode is enabled, the port exists on the ISA bus. ...

Page 161

... The duration of the speedup is configured in the Video Speedup Timer Count Register (F0 Index 8Dh). Detection of an external VGA access (3Bxh, 3Cxh, 3Dxh and A000h-B7FFh) on the PCI bus is also supported. This configuration is non- standard, but it does allow the power management routines to support an external VGA chip. AMD Geode™ CS5530A Companion Device Data Book 0100 = IRQ4 1000 = RSVD ...

Page 162

... COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1: this range is included) Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[3]. 162 Power Management Enable Register 2 (R/W) AMD Geode™ CS5530A Companion Device Data Book Register Descriptions Reset Value = 00h ...

Page 163

... COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1: this range is included) Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[3]. AMD Geode™ CS5530A Companion Device Data Book Power Management Enable Register 3 (R/W) Revision 1.1 ...

Page 164

... This idle timer is reloaded from the assertion of GPIO7 (if programmed to do so). GP Timer 2 programming Index 8Ah and 8Bh[5,3,2]. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[1]. 164 Power Management Enable Register 4 (R/W) AMD Geode™ CS5530A Companion Device Data Book Register Descriptions Reset Value = 00h ...

Page 165

... Keyboard/Mouse Idle Timer SMI Status (Read Only): SMI was caused by expiration of the Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh No Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling Index 81h[3]. AMD Geode™ CS5530A Companion Device Data Book Revision 1.1 Reset Value = 00h Reset Value = 00h ...

Page 166

... GPIO2 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO2 pin No Yes. This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling Index 92h[2]. 166 Register Descriptions Reset Value = 00h Reset Value = 00h AMD Geode™ CS5530A Companion Device Data Book ...

Page 167

... Keyboard Controller: I/O Ports 060h/064h COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1: this range is included) COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1: this range is included) AMD Geode™ CS5530A Companion Device Data Book General Purpose Timer 1 Count Register (R/W) Revision 1.1 ...

Page 168

... This speedup mechanism allows instantaneous response to system interrupts for full-speed interrupt processing. A typical value here would ms. 168 General Purpose Timer 2 Count Register (R/W) IRQ Speedup Timer Count Register (R/W) AMD Geode™ CS5530A Companion Device Data Book Register Descriptions Reset Value = 00h Reset Value = 00h Reset Value = 00h ...

Page 169

... GPIO2 Edge Sense for SMI: Selects which edge transition of the GPIO2 pin generates an SMI Rising Falling. Bit 2 must be set to enable this bit. AMD Geode™ CS5530A Companion Device Data Book Video Speedup Timer Count Register (R/W) VGA Timer Count Register (R/W) ...

Page 170

... This timer is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video speedups. 170 Miscellaneous Device Control Register (R/W) Suspend Modulation OFF Count Register (R/W) Suspend Modulation ON Count Register (R/W) AMD Geode™ CS5530A Companion Device Data Book Register Descriptions Reset Value = 00h Reset Value = 00h Reset Value = 00h ...

Page 171

... SMI handler reads the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The latter is the preferred method. The IRQ speedup method is provided for software compatibility with earlier revisions of the CS5530A. This bit has no effect if the Suspend Modulation feature is disabled (bit 0 = 0). ...

Page 172

... Second level SMI status is reported at F0 Index 85h/F5h[5]. 172 Floppy Disk Idle Timer Count Register (R/W) Parallel / Serial Idle Timer Count Register (R/W) AMD Geode™ CS5530A Companion Device Data Book Register Descriptions Reset Value = 0000h Reset Value = 0000h Reset Value = 0000h ...

Page 173

... IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external SMI source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530A pins can be used to wake- up the system from Suspend when the clocks are stopped. As long as the 32 KHz clock remains active, internal SMI events are also Resume events. AMD Geode™ ...

Page 174

... IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external SMI source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530A pins can be used to wake- up the system from Suspend when the clocks are stopped. ...

Page 175

... The four-bit field allows values from ms. 0000 = 0 ms 0001 = 1 ms 0010 = 2 ms 0011 = 3 ms 3:1 Reserved: Set to 0. AMD Geode™ CS5530A Companion Device Data Book PIC Shadow Register (RO) PIT Shadow Register (RO) RTC Index Shadow Register (RO) Clock Stop Control Register (R/W) 0100 = 4 ms 1000 = 8 ms ...

Page 176

... CPU Clock Stop Normal SUSP#/ SUSPA# handshake Full system Suspend. Note: This register configures the CS5530A to support a 3 Volt Suspend. Setting bit 0 causes the SUSP_3V pin to assert after the appropriate conditions, stopping the system clocks. A delay programmable (bits 7:4) to allow for a delay for the clock chip and CPU PLL to stabilize when an event Resumes the system ...

Page 177

... User Defined Device 3 (UDEF3) Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the UDEF3 Idle Timer Count Register (F0 Index A4h No Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling Index 81h[6]. AMD Geode™ CS5530A Companion Device Data Book Reserved Software SMI Register (WO) Reserved ...

Page 178

... Floppy Disk Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the floppy disk No Yes. This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0]. SMI generation enabling Index 82h[1]. 178 Register Descriptions Reset Value = 00h AMD Geode™ CS5530A Companion Device Data Book ...

Page 179

... This register provides status on several miscellaneous power management events that generate SMIs, as well as the status of the Lid Switch. Reading this register clears the SMI status bits. A read-only (mirror) version of this register exists at F0 Index 87h. Index F8h-FFh AMD Geode™ CS5530A Companion Device Data Book Revision 1.1 Reserved Reset Value = 00h ...

Page 180

... Index 00h-01h Index 02h-03h Index 04h-05h 15:2 Reserved (Read Only) 1 Memory Space: Allow CS5530A to respond to memory cycles from the PCI bus Disable Enable. This bit must be enabled to access memory offsets through F1BAR (F1 Index 10h). 0 Reserved (Read Only) Index 06h-07h Index 08h ...

Page 181

... A20M# SMI No Yes. This method of controlling the internal A20M# in the GX1 processor is used instead of a pin. SMI generation enabling Index 53h[0]. AMD Geode™ CS5530A Companion Device Data Book Top Level SMI Status Mirror Register (RO) Top Level SMI Status Register (RC) Revision 1 ...

Page 182

... Note: Reading this register does not clear the status bits. See F1BAR+Memory Offset 06h. Offset 06h-07h Second Level General Traps & Timers SMI Status Register (RC) 15:6 Reserved (Read to Clear) 182 Register Descriptions Reset Value = 0000h Reset Value = 0000h AMD Geode™ CS5530A Companion Device Data Book ...

Page 183

... The preferred method is to program these register through the F0 register space. Refer to Table 5-15 "F0 Index xxh: PCI Header and Bridge Configuration Registers" on page 155 for bit information regarding these registers. AMD Geode™ CS5530A Companion Device Data Book Reserved ACPI Timer Count Register (RO) Reserved Revision 1 ...

Page 184

... Reserved (Read Only) 2 Reserved 1 Reserved (Read Only) 0 I/O Space: Allow CS5530A to respond to I/O cycles from the PCI bus Disable Enable. This bit must be enabled to access I/O offsets through F2BAR (F2 Index 20h). Index 06h-07h Index 08h Index 09h-0Bh Index 0Ch Index 0Dh ...

Page 185

... Bus Master Interrupt: Has the bus master detected an interrupt No Yes. Write 1 to clear. 1 Bus Master Error: Has the bus master detected an error during data transfer No Yes. Write 1 to clear. AMD Geode™ CS5530A Companion Device Data Book Revision 1.1 Reserved Reserved Reserved ...

Page 186

... Note: The reset value of this register is not a valid PIO Mode. 186 Reserved Reserved Channel 0 Drive 0 PIO Register (R/W) AMD Geode™ CS5530A Companion Device Data Book Register Descriptions Reset Value = xxh Reset Value = 00000000h Reset Value = xxh Reset Value = 0000E132h (Note) ...

Page 187

... Channel 1 Drive 1 MDMA/UDMA Control Register: Refer to F2BAR+I/O Offset 24h for bit descriptions. Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only. Offset 40h-FFh AMD Geode™ CS5530A Companion Device Data Book Channel 0 Drive 0 DMA Control Register (R/W) Channel 0 Drive 1 PIO Register (R/W) ...

Page 188

... Index 04h-05h 15:3 Reserved (Read Only) 2 Reserved (Read/Write) 1 Memory Space: Allow CS5530A to respond to memory cycles from the PCI bus Disable Enable. This bit must be enabled to access memory offsets through F3BAR (F3 Index 10h). 0 Reserved (Read Only) Index 06h-07h Index 08h Index 09h-0Bh ...

Page 189

... Codec Command Address: Address of the codec control register for which the command is being sent. This address goes in slot 1 bits [19:12] on SDATA_OUT. 23:22 CS5530A Codec Communication: Selects which codec to communicate with Primary codec 01 = Secondary codec Note: 00 and 01 are the only valid settings for these bits. ...

Page 190

... SMI generation is enabled when Audio Bus Master 3 is enabled (F3BAR+Memory Offset 38h[0] = 1). An SMI is then generated when the End of Page bit is set in the SMI Status Register (F3BAR+Memory Offset 39h[0] = 1). 190 Register Descriptions Reset Value = 0000h AMD Geode™ CS5530A Companion Device Data Book ...

Page 191

... This is the third level of SMI status reporting. The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0]. The top level is reported at F1BAR+Memory Offset 00h/02h[1]. SMI generation enabling is at F3BAR+Memory Offset 18h[6:5]. AMD Geode™ CS5530A Companion Device Data Book Revision 1.1 Reset Value = 00000000h 191 ...

Page 192

... Fast Path Write Enable: Fast Path Write (an SMI is not generated on certain writes to specified addresses Disable Enable. In Fast Path Write, the CS5530A responds to writes to the following addresses: 388h, 38Ah and 38Bh; 2x0h, 2x2h, and 2x8h. 10:9 Fast Read: These two bits hold part of the response that the CS5530A returns for reads to several I/O locations. ...

Page 193

... Mask Internal IRQ4 Disable Enable. 3 Mask Internal IRQ3 Disable Enable. 2:0 Reserved: Set to 0. AMD Geode™ CS5530A Companion Device Data Book Internal IRQ Enable Register (R/W) Internal IRQ Control Register (R/W) Internal IRQ Mask Register (Write Only) Revision 1.1 Reset Value = 0000h ...

Page 194

... Audio Bus Master 0 SMI Status Register (RC) Reserved Audio Bus Master 0 PRD Table Address (R/W) Audio Bus Master 1 Command Register (R/W) Audio Bus Master 1 SMI Status Register (RC) AMD Geode™ CS5530A Companion Device Data Book Register Descriptions Reset Value = 00h Reset Value = 00h Reset Value = xxh ...

Page 195

... This bit must be set to 1 (write) and should not be changed when the bus master is active. 2:1 Reserved: Set to 0. Must return 0 on reads. AMD Geode™ CS5530A Companion Device Data Book Reserved Audio Bus Master 1 PRD Table Address (R/W) Audio Bus Master 2 Command Register (R/W) ...

Page 196

... Reserved Audio Bus Master 3 PRD Table Address (R/W) Audio Bus Master 4 Command Register (R/W) Audio Bus Master 4 SMI Status Register (RC) Reserved AMD Geode™ CS5530A Companion Device Data Book Register Descriptions Reset Value = 00h Reset Value = xxh Reset Value = 00000000h Reset Value = 00h ...

Page 197

... When read, this register points to the next PRD. 1:0 Reserved: Set to 0. Offset 50h-FFh AMD Geode™ CS5530A Companion Device Data Book Audio Bus Master 4 PRD Table Address (R/W) Audio Bus Master 5 Command Register (R/W) Audio Bus Master 5 SMI Status Register (RC) ...

Page 198

... Index 00h-01h Index 02h-03h Index 04h-05h 15:2 Reserved (Read Only) 1 Memory Space: Allow CS5530A to respond to memory cycles from the PCI bus Disable Enable. This bit must be enabled to access memory offsets through F4BAR (F4 Index 10h). 0 Reserved (Read Only) Index 06h-07h Index 08h ...

Page 199

... Video Register Update: Allow video position and scale registers to be updated simultaneously on next occurrence of vertical sync Disable Enable. 0 Video Enable: Video acceleration hardware Disable Enable. AMD Geode™ CS5530A Companion Device Data Book Video Configuration Register (R/W) 16-Bit Mode (Value Byte Order [0:3 (also used for RGB 5:6:5 input) ...

Page 200

... Display Enable: Enables the graphics display pipeline used as a reset for the display control logic Reset display control logic Enable display control logic. 200 Display Configuration Register (R/W) AMD Geode™ CS5530A Companion Device Data Book Register Descriptions Reset Value = 00000000h ...

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