HD6433643P HITACHI, HD6433643P Datasheet
HD6433643P
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HD6433643P Summary of contents
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... HD6473644, HD6433644 H8/3644F-ZTAT™ H8/3643F-ZTAT™ H8/3642AF-ZTAT™ ADE-602-087C Rev. 4.0 08/08/98 Hitachi, Ltd. MC-Setsu H8/3644 Series H8/3644 H8/3643 HD6433643 H8/3642 HD6433642 H8/3641 HD6433641 H8/3640 HD6433640 HD64F3644 HD64F3643 HD64F3642A Hardware Manual ...
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... Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document ...
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The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core, with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is compatible with the H8/300 CPU. The H8/3644 Series has a system-on-a-chip architecture that includes ...
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Section 1 Overview ........................................................................................................... 1.1 Overview............................................................................................................................ 1.2 Internal Block Diagram ..................................................................................................... 1.3 Pin Arrangement and Functions ........................................................................................ 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions........................................................................................................ Section 2 CPU ..................................................................................................................... 2.1 Overview............................................................................................................................ 15 2.1.1 Features ................................................................................................................ 15 2.1.2 Address Space ...................................................................................................... 16 ...
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Memory Map ..................................................................................................................... 2.9 Application Notes.............................................................................................................. 50 2.9.1 Notes on Data Access........................................................................................... 2.9.2 Notes on Bit Manipulation ................................................................................... 2.9.3 Notes on Use of the EEPMOV Instruction .......................................................... 58 Section 3 Exception Handling 3.1 Overview............................................................................................................................ 59 3.2 Reset .................................................................................................................................. 59 ...
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Watch Mode ...................................................................................................................... 99 5.4.1 Transition to Watch Mode.................................................................................... 99 5.4.2 Clearing Watch Mode .......................................................................................... 99 5.4.3 Oscillator Settling Time after Watch Mode is Cleared ........................................ 99 5.5 Subsleep Mode .................................................................................................................. 100 5.5.1 Transition to Subsleep Mode................................................................................ 100 5.5.2 ...
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Program-Verify Mode .......................................................................................... 131 6.7.3 Programming Flowchart and Sample Program .................................................... 132 6.7.4 Erase Mode........................................................................................................... 135 6.7.5 Erase-Verify Mode ............................................................................................... 135 6.7.6 Erase Flowcharts and Sample Programs .............................................................. 136 6.7.7 Prewrite-Verify Mode .......................................................................................... 149 6.7.8 Protect Modes....................................................................................................... 149 6.7.9 ...
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Port 6.................................................................................................................................. 192 8.6.1 Overview .............................................................................................................. 192 8.6.2 Register Configuration and Description............................................................... 192 8.6.3 Pin Functions........................................................................................................ 193 8.6.4 Pin States .............................................................................................................. 194 8.7 Port 7.................................................................................................................................. 195 8.7.1 Overview .............................................................................................................. 195 8.7.2 Register Configuration and Description............................................................... 195 8.7.3 Pin Functions........................................................................................................ ...
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Interrupt Sources .................................................................................................. 233 9.4.6 Application Examples .......................................................................................... 234 9.4.7 Application Notes................................................................................................. 236 9.5 Timer X.............................................................................................................................. 242 9.5.1 Overview .............................................................................................................. 242 9.5.2 Register Descriptions............................................................................................ 246 9.5.3 CPU Interface ....................................................................................................... 257 9.5.4 Timer Operation ................................................................................................... 260 9.5.5 Timer X Operation ...
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PWM Control Register (PWCR).......................................................................... 348 11.2.2 PWM Data Registers U and L (PWDRU, PWDRL)............................................ 349 11.3 Operation ........................................................................................................................... 350 Section 12 A/D Converter 12.1 Overview............................................................................................................................ 351 12.1.1 Features ................................................................................................................ 351 12.1.2 Block Diagram...................................................................................................... 352 12.1.3 Pin Configuration ................................................................................................. 353 ...
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A.3 Number of Execution States.............................................................................................. 413 Appendix B Internal I/O Registers B.1 Addresses........................................................................................................................... 420 B.2 Functions............................................................................................................................ 424 Appendix C I/O Port Block Diagrams C.1 Block Diagrams of Port 1 .................................................................................................. 471 C.2 Block Diagrams of Port 2 .................................................................................................. 475 C.3 ...
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... In addition to the mask ROM version, the H8/3644 is also available ZTAT™* version with on-chip user-programmable PROM, and an F-ZTAT™* chip flash memory that can be programmed on-board. Table 1 summarizes the features of the H8/3644 Series. Notes: 1. ZTAT is a trademark of Hitachi, Ltd. 2. F-ZTAT is a registered trademark of Hitachi, Ltd. Section 1 Overview 2 version with on- 1 ...
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Table 1.1 Features Item Description CPU High-speed H8/300L CPU General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) Operating speed Max. operation speed: 5 MHz (mask ROM and ZTAT versions) Add/subtract: 0.4 s (operating at ...
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Table 1.1 Features (cont) Item Description Memory Large on-chip memory H8/3644: 32-kbyte ROM, 1-kbyte RAM H8/3643: 24-kbyte ROM, 1-kbyte RAM H8/3642: 16-kbyte ROM, 512 byte RAM (1-kbyte RAM F-ZTAT version) H8/3641: 12-kbyte ROM, 512 byte RAM H8/3640: 8-kbyte ROM, 512 ...
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... Successive approximations using a resistance ladder 8-channel analog input pins Conversion time: 31/ø or 62/ø per channel Product lineup Mask ROM Version HD6433644H HD6433644P HD6433644W HD6473644W HD64F3644W HD6433643H HD6433643P HD6433643W — HD6433642H HD6433642P HD6433642W — HD6433641H HD6433641P HD6433641W — HD6433640H HD6433640P HD6433640W — ...
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Internal Block Diagram Figure 1.1 shows a block diagram of the H8/3644 Series. P1 /TMOW 0 P1 /PWM 4 P1 /IRQ /IRQ /IRQ /TRGV /SCK /RXD 1 ...
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Pin Arrangement and Functions 1.3.1 Pin Arrangement The H8/3644 Series pin arrangement is shown in figures 1.2 (FP-64A), 1.3 (DP-64S), and 1.4 (TFP-80C TEST 4 X ...
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P1 /IRQ /TRGV / / / / / / ...
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/ / TEST SS1 OSC 9 1 OSC SS2 RES 12 P9 /FV 13 ...
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Pin Functions Table 1.2 outlines the pin functions of the H8/3644 Series. Table 1.2 Pin Functions Type Symbol FP-64A Power source pins Clock pins OSC 8 1 ...
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Table 1.2 Pin Functions (cont) Type Symbol FP-64A IRQ Interrupt 16 0 IRQ pins 55 1 IRQ 56 2 IRQ 57 3 INT INT 0 Timer pins TMOW 53 TMIB 31 TMOV 37 TMCIV 36 ...
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Table 1.2 Pin Functions (cont) Type Symbol FP-64A Timer pins FTIA 42 FTIB 43 FTIC 44 FTID 45 14-bit PWM 54 PWM pin I/O ports 64 ...
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Table 1.2 Pin Functions (cont) Type Symbol FP-64A I/O ports Serial com munication ...
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Table 1.2 Pin Functions (cont) Type Symbol FP-64A Flash memory Other NC — Pin No. DP-64S TFP-80C I Input — 1, 16, — 20, 21, 30, 39, 40, 41, 48, 53 62, 79, ...
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Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. General-register architecture ...
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Address Space The H8/300L CPU supports an address space kbytes for storing program code and data. See 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2.1 shows the register structure ...
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Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H ...
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Condition Code Register (CCR): This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written by software (using ...
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Initial Register Values In reset exception handling, the program counter (PC) is initialized by a vector address (H'0000) load, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are ...
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Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2.3. Data Type Register No. 7 1-bit data RnH 7 1-bit data RnL 7 Byte data RnH MSB ...
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Memory Data Formats Figure 2.4 indicates the data formats in memory. For access by the H8/300L CPU, word data stored in memory must always begin at an even address. When word data beginning at an odd address is accessed, ...
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Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes. Table 2.1 Addressing Modes No. Address Modes 1 Register direct 2 Register indirect ...
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Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn: • Register indirect with post-increment—@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the ...
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Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. This specifies an operand in memory, and a branch is performed with the contents ...
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Table 2.2 Effective Address Calculation Addressing Mode and No. Instruction Format 1 Register indirect Register indirect, @ Register indirect with displacement, @(d:16, Rn) ...
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Table 2.2 Effective Address Calculation (cont) Addressing Mode and No. Instruction Format 5 Absolute address @aa abs @aa: abs 6 Immediate #xx IMM #xx: IMM 7 Program-counter relative ...
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Table 2.2 Effective Address Calculation (cont) Addressing Mode and No. Instruction Format 8 Memory indirect, @@aa abs Legend: rm, rn: Register field op: Operation field disp: Displacement IMM: Immediate data abs: Absolute address Effective Address Calculation ...
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Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3. Table 2.3 Instruction Set Function Data transfer Arithmetic operations Logic operations Shift Bit manipulation Branch System control Block data ...
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Notation Rd General register (destination) Rs General register (source) Rn General register (EAd), <Ead> Destination operand (EAs), <Eas> Source operand CCR Condition code register N N (negative) flag of CCR Z Z (zero) flag of CCR V V (overflow) flag ...
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Data Transfer Instructions Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Data Transfer Instructions Instruction Size* MOV B/W POP W PUSH W Notes: * Size: Operand size B: Byte W: Word ...
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Legend: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2.5 Data Transfer ...
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Arithmetic Operations Table 2.5 describes the arithmetic instructions. Table 2.5 Arithmetic Instructions Instruction Size* ADD B/W SUB ADDX B SUBX INC B DEC ADDS W SUBS DAA B DAS MULXU B DIVXU B CMP B/W NEG B Notes: * ...
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Logic Operations Table 2.6 describes the four instructions that perform logic operations. Table 2.6 Logic Operation Instructions Instruction Size* AND XOR B NOT B Notes: * Size: Operand size B: Byte 2.5.4 Shift Operations Table 2.7 ...
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Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions Legend: op: Operation field rm, rn: Register field IMM: Immediate data ...
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Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Bit-Manipulation Instructions Instruction Size* BSET B BCLR B BNOT B BTST B BAND B BIAND B BOR B BIOR B Notes: * ...
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Table 2.8 Bit-Manipulation Instructions (cont) Instruction Size* BXOR B BIXOR B BLD B BILD B BST B BIST B Notes: * Size: Operand size B: Byte Certain precautions are required in bit manipulation. See 2.9.2, Notes on Bit Manipulation, for ...
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Legend: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 ...
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Legend: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes (cont IMM ...
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Branching Instructions Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Branching Instructions Instruction Size* Bcc — JMP — BSR — JSR — RTS — Function Branches to the designated address if condition ...
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Legend: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address Figure 2.8 Branching Instruction Codes disp ...
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System Control Instructions Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions Instruction Size* RTE — SLEEP — LDC B STC B ANDC B ORC B XORC B NOP ...
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Legend: op: Operation field rn: Register field IMM: Immediate data Figure 2.9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format. ...
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Legend: op: Operation field Figure 2.10 Block Data Transfer Instruction Code ...
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Basic Operational Timing CPU operation is synchronized by a system clock (ø subclock (ø clock signals see section 4, Clock Pulse Generators. The period from a rising edge of ø or ø the next rising edge is ...
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Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions ...
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Three-State Access to On-Chip Peripheral Modules: Figure 2.13 shows the operation timing in the case of three-state access to an on-chip peripheral module. ø or ø SUB Internal address bus Internal read signal Internal data bus (read access) Internal write ...
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CPU state Reset state The CPU is initialized execution state Program halt state A state in which some or all of the chip functions are stopped to conserve power Exception- handling state A transient state in which the CPU changes ...
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Reset state Reset occurs Program halt state 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one ...
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Memory Map Figure 2.16 shows a memory map of the H8/3644 Series. H'0000 Interrupt vectors H'002F H'0030 H'1FFF H'2FFF H'3FFF On-chip ROM H'5FFF H'7FFF Reserved H'F770 Internal I/O registers (16 bytes) H'F77F Reserved H'FB80 On-chip RAM H'FD7F H'FD80 H'FF7F ...
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Application Notes 2.9.1 Notes on Data Access 1. Access to empty areas The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas ...
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H'0000 Interrupt vector area (48 bytes) H'002F H'0030 On-chip ROM H'7FFF Reserved H'F770 Internal I/O registers (16 bytes) H'F77F Reserved H'FB80 On-chip RAM H'FF7F H'FF80 Reserved H'FF9F H'FFA0 Internal I/O registers (96 bytes) H'FFFF Notes: The H8/3644 is shown as ...
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Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers ...
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Example 2: BSET instruction executed designating port 3 P3 and P3 are designated as input pins, with a low-level signal input signal The remaining pins example, the BSET instruction is used ...
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To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR3. [A: Prior to executing BSET] MOV. ...
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Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 3 control register PCR3 As in the examples above, P3 high-level signal The remaining pins signals. In this example, ...
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To avoid this problem, store a copy of the PCR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PCR3. [A: Prior to executing BCLR] MOV. ...
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Table 2.12 lists the pairs of registers that share identical addresses. Table 2.13 lists the registers that contain write-only bits. Table 2.12 Registers with Shared Addresses Register Name Output compare register AH and output compare register BH (timer X) OCRAH/OCRBH ...
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Notes on Use of the EEPMOV Instruction The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified the address specified by R6 ...
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Section 3 Exception Handling 3.1 Overview Exception handling is performed in the H8/3644 Series when a reset or interrupt occurs. Table 3.1 shows the priorities of these two types of exception handling. Table 3.1 Exception Handling Types and Priorities Priority ...
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When system power is turned on or off, the RES pin should be held low. Figure 3.1 shows the reset sequence starting from RES input. RES ø Internal address bus Internal read signal Internal write signal Internal data bus (16-bit) ...
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Interrupt Immediately after Reset After a reset interrupt were to be accepted before the stack pointer (SP: R7) was initialized, PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To prevent ...
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Table 3.2 Interrupt Sources and Their Priorities Interrupt Source Interrupt RES Reset IRQ IRQ 0 0 IRQ IRQ 1 1 IRQ IRQ 2 2 IRQ IRQ 3 3 INT INT 0 0 INT INT 1 1 INT INT 2 2 ...
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Interrupt Control Registers Table 3.3 lists the registers that control interrupts. Table 3.3 Interrupt Control Registers Name Interrupt edge select register 1 Interrupt edge select register 2 Interrupt enable register 1 Interrupt enable register 2 Interrupt enable register 3 ...
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Edge Select (IEG2): Bit 2 selects the input sensing of pin IRQ Bit 2—IRQ 2 Bit 2: IEG2 Description Falling edge of IRQ 0 Rising edge of IRQ 1 Edge Select (IEG1): Bit 1 selects the input sensing of pin ...
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Interrupt Edge Select Register 2 (IEGR2) Bit 7 INTEG7 INTEG6 INTEG5 INTEG4 INTEG3 INTEG2 INTEG1 INTEG0 Initial value 0 Read/Write R/W IEGR2 is an 8-bit read/write register, used to designate whether pins INT TMIB are set to rising edge sensing ...
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Interrupt Enable Register 1 (IENR1) Bit 7 IENTB1 Initial value 0 Read/Write R/W IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Upon reset, IENR1 is initialized to H'10. Bit 7—Timer B1 Interrupt Enable (IENTB1): Bit 7 ...
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Interrupt Enable Register 2 (IENR2) Bit 7 IENDT Initial value 0 Read/Write R/W IENR2 is an 8-bit read/write register that enables or disables interrupt requests. Upon reset, IENR2 is initialized to H'00. Bit 7—Direct Transfer Interrupt Enable (IENDT): Bit 7 ...
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Interrupt Enable Register 3 (IENR3) Bit 7 INTEN7 INTEN6 INTEN5 INTEN4 INTEN3 INTEN2 INTEN1 INTEN0 Initial value 0 Read/Write R/W IENR3 is an 8-bit read/write register that enables or disables INT reset, IENR3 is initialized to H'00. Bits 7 to ...
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Interrupt Request Register 1 (IRR1) Bit 7 IRRTB1 Initial value 0 Read/Write R/W* Note: * Only a write of 0 for flag clearing is possible. IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 ...
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Interrupt Request Register 2 (IRR2) Bit 7 IRRDT Initial value 0 Read/Write R/W* Note: * Only a write of 0 for flag clearing is possible. IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 ...
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Interrupt Request Register 3 (IRR3) Bit 7 INTF7 Initial value 0 Read/Write R/W* Note: * Only a write of 0 for flag clearing is possible. IRR3 is an 8-bit read/write register, in which a corresponding flag is set to 1 ...
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External Interrupts There are 12 external interrupts: IRQ Interrupts IRQ to IRQ : Interrupts IRQ 3 0 IRQ . These interrupts are detected by either rising edge sensing or falling edge sensing, 0 depending on the settings of bits ...
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Interrupt Operations Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance. External or internal interrupts External interrupts or internal interrupt enable signals ...
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The I bit of CCR is set to 1, masking further interrupts. The vector address corresponding to the accepted interrupt is generated, and the interrupt handling routine located at the address indicated by the contents of the vector address is ...
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Program execution state No IRRIO = 1 Yes No IENO = 1 Yes Yes PC contents saved CCR contents saved I 1 Branch to interrupt handling routine Legend: PC: Program counter CCR: Condition code register I: ...
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SP – – – – (R7) Stack area Prior to start of interrupt exception handling Legend Upper 8 bits of program counter (PC Lower 8 bits of ...
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Interrupt is accepted Interrupt level decision and wait for Instruction end of instruction prefetch Interrupt request signal ø Internal (1) address bus Internal read signal Internal write signal Internal data bus (2) (4) (16 bits) (1) Instruction prefetch address (Instruction ...
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Interrupt Response Time Table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3.4 Interrupt Wait States Item Waiting time for completion of ...
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Application Notes 3.4.1 Notes on Stack Area Use When word data is accessed in the H8/3644 Series, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so ...
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Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. When an external interrupt pin function is switched by rewriting the port ...
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CCR I bit 1 Set port mode register bit Execute NOP instruction Clear interrupt request flag to 0 CCR I bit 0 Figure 3.7 Port Mode Register Setting and Interrupt Request Flag Interrupts masked. (Another possibility is to disable the ...
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Section 4 Clock Pulse Generators 4.1 Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator ...
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System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator providing external clock input. Connecting a Crystal Oscillator: Figure 4.2 shows a typical method of connecting ...
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Connecting a Ceramic Oscillator: Figure 4.4 shows a typical method of connecting a ceramic oscillator. OSC 1 OSC 2 Figure 4.4 Typical Connection to Ceramic Oscillator Notes on Board Design: When generating clock pulses by connecting a crystal or ceramic ...
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External Clock Input Method: Connect an external clock signal to pin OSC OSC open. Figure 4.6 shows a typical connection. 2 OSC 1 OSC 2 Figure 4.6 External Clock Input (Example) Frequency Duty cycle 86 Open Oscillator Clock (ø ) ...
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Subclock Generator Connecting a 32.768-kHz Crystal Oscillator: Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal oscillator, as shown in figure 4.7. Follow the same precautions as noted under 4.2 Notes on Board Design. ...
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Prescalers The H8/3644 Series is equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler 13-bit counter using the system clock (ø) as its input clock. Its prescaled outputs provide internal ...
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Section 5 Power-Down Modes 5.1 Overview The H8/3644 Series has eight modes of operation after a reset. These include seven power-down modes, in which power dissipation is significantly reduced. Table 5.1 gives a summary of the eight operating modes. Table ...
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Reset state Program halt state Standby mode *1 instruction Watch mode Mode Transition Conditions (1) LSON MSON SSBY ...
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Table 5.2 Internal State in Each Operating Mode Active Mode High- Function Speed System clock oscillator Functions Subclock oscillator Functions CPU Instructions Functions operations Registers RAM I/O ports External IRQ Functions 0 interrupts IRQ 1 IRQ 2 IRQ 3 INT ...
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Table 5.3 System Control Registers Name System control register 1 System control register 2 System Control Register 1 (SYSCR1) Bit 7 SSBY Initial value 0 Read/Write R/W SYSCR1 is an 8-bit read/write register for control of the power-down modes. Upon ...
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Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to ...
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System Control Register 2 (SYSCR2) Bit 7 — Initial value 1 Read/Write — SYSCR2 is an 8-bit read/write register for power-down mode control. Upon reset, SYSCR2 is initialized to H'E0. Bits 7 to 5—Reserved Bits: These bits are reserved; they ...
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Bit 3: DTON Description 0 When a SLEEP instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode When a SLEEP instruction is executed in subactive mode, a transition is made to ...
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Sleep Mode 5.2.1 Transition to Sleep Mode Transition to Sleep (High-Speed) Mode: The system goes from active mode to sleep (high- speed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in SYSCR1 and the ...
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Standby Mode 5.3.1 Transition to Standby Mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared ...
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Oscillator Settling Time after Standby Mode is Cleared Bits STS2 to STS0 in SYSCR1 should be set as follows. When a crystal oscillator is used The table 5.4 gives settings for various operating frequencies. Set bits STS2 to STS0 ...
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Watch Mode 5.4.1 Transition to Watch Mode The system goes from active or subactive mode to watch mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA ...
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Subsleep Mode 5.5.1 Transition to Subsleep Mode The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to ...
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Subactive Mode 5.6.1 Transition to Subactive Mode Subactive mode is entered from watch mode if a timer A or IRQ LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A, ...
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Active (Medium-Speed) Mode 5.7.1 Transition to Active (Medium-Speed) Mode If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared transition to active (medium-speed) mode results from IRQ IRQ ...
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Direct Transfer The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution. A direct transfer can ...
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Direct transfer from subactive mode to active (medium-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit ...
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Overview The H8/3644 has 32 kbytes of on-chip mask ROM, PROM or flash memory. The H8/3643 has 24 kbytes of mask ROM or flash memory. The H8/3642 has 16 kbytes of mask ROM or flash memory. The H8/3641 has ...
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PROM Mode 6.2.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the standard HN27C256 ...
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H8/3644 Pin # FP-64A DP-64S ...
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Address in MCU mode Figure 6.3 H8/3644 Memory Map in PROM Mode When programming with a PROM programmer, be sure to specify addresses from H'0000 to H'7FFF. 6.3 Programming The H8/3644 write, verify, and other modes are selected as shown ...
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Writing and Verifying An efficient, high-speed, high-reliability method is available for writing and verifying the PROM data. This method achieves high speed without voltage stress on the device and without lowering the reliability of written data. Data in unused ...
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Table 6.4 and table 6.5 give the electrical characteristics in programming mode. Table 6.4 DC Characteristics (Conditions 6 Item Input high OE, CE level voltage Input ...
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Table 6.5 AC Characteristics (Conditions 6 Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time V setup time PP Programming pulse width ...
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... Use the specified programming voltage and timing. The programming voltage in PROM mode (V permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Hitachi specifications for the HN27C256 will result in correct Make sure the index marks on the PROM programmer socket, socket adapter, and chip are properly aligned ...
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... If a series of programming errors occurs while the same PROM programmer is in use, stop programming and check the PROM programmer and socket adapter for defects, using a microcomputer with on-chip EPROM in a windowed package, etc. Please inform Hitachi of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking ...
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After erasure, the threshold voltage drops. A memory cell is read like an EPROM cell, by driving the gate to a high level and detecting the drain current, which depends on the threshold voltage. Erasing ...
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Features The features of the flash memory are summarized below. Five flash memory operating modes There are five flash memory operating modes: program mode, program-verify mode, erase mode, erase-verify mode, and prewrite-verify mode. Erase block specification Blocks to be ...
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Block Diagram Figure 6.7 shows a block diagram of the flash memory FLMCR EBR1 EBR2 Legend: FLMCR: Flash memory control register EBR1: Erase block register 1 EBR2: Erase block register 2 Figure 6.7 Block Diagram of Flash ...
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Pin Configuration The flash memory is controlled by means of the pins shown in table 6.7. Table 6.7 Flash Memory Pins Pin Name Abbreviation Programming power FV Mode pin TEST Transmit data TXD Receive data RXD The transmit data ...
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Flash Memory Register Descriptions 6.5.1 Flash Memory Control Register (FLMCR) FLMCR is an 8-bit register used for flash memory operating mode control. Transitions to program mode, erase mode, program-verify mode, and erase-verify mode are made by setting bits in ...
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Bit 2—Program-Verify Mode (PV)* mode. Bit 2: PV Description 0 Exit from program-verify mode 1 Transition to program-verify mode 1 2 Bit 1—Erase Mode (E)* * Bit 1: E Description 0 Exit from erase mode 1 Transition to erase mode ...
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Erase Block Register 1 (EBR1) EBR1 is an 8-bit register that specifies large flash-memory blocks for programming or erasure. EBR1 is initialized to H'F0 upon reset, in sleep mode, subsleep mode, watch mode, and standby mode, and when 12 ...
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Erase Block Register 2 (EBR2) EBR2 is an 8-bit register that specifies small flash-memory blocks for programming or erasure. EBR2 is initialized to H'00 upon reset, in sleep mode, subsleep mode, watch mode, and standby mode, and when 12 ...
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Small block area (4 kbytes) Large block area (H8/3644F: 28 kbytes) (H8/3643F: 20 kbytes) Table 6.9 Correspondence between Erase Blocks and EBR1/EBR2 Bits Register Bit EBR1 Register Bit EBR2 ...
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On-Board Programming Modes When an on-board programming mode is selected, on-chip flash memory programming, erasing, and verifying can be carried out. There are two on-board programming modes—boot mode and user program mode—set by the mode pin (TEST) and the ...
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Boot Mode Execution Procedure: The boot mode execution procedure is shown below. Start Set pins to boot mode for chip 1 and execute reset-start Host transmits H'00 data continuously 2 at prescribed bit rate Chip measures low period of H'00 ...
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Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8/3644F, H8/3643F, or H8/3642AF measures the low period of the asynchronous SCI communication data transmitted continuously from the host (figure 6.11). The data format should be set as 8-bit ...
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Table 6.11 System Clock Oscillation Frequencies Permitting Automatic Adjustment of Chip (H8/3644F, H8/3643F, H8/3642AF) Bit Rate System Clock Oscillation Frequencies (f Host Bit Rate* Adjustment of Chip (H8/3644F, H8/3643F, H8/3642AF) Bit Rate 9600 bps 8 MHz to 16 MHz 4800 ...
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Notes on Use of Boot Mode: 1. When the chip (H8/3644F, H8/3643F, or H8/3642AF) comes out of reset in boot mode, it measures the low period of the input at the SCI3’s RXD pin. The reset should end with RXD ...
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Also, do not release or cut V flash memory*. Boot mode can be exited by driving the reset pin low, then releasing 12 V application to the TEST pin and FV pin at least 10 system clock cycles later, and ...
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User Program Mode Execution Procedure* RAM is shown below. 1 Reset-start (TEST = V Branch to flash memory on-board 2 reprogramming program Transfer flash memory 3 reprogramming routine to RAM Branch to flash memory 4 reprogramming routine in RAM area ...
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Programming and Erasing Flash Memory The on-chip flash memory of the H8/3644F, H8/3643F, and H8/3642AF is programmed and erased by software, using the CPU. There are five flash memory operating modes: program mode, erase mode, program-verify mode, erase-verify mode, ...
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Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of the programming time, exit programming mode (clear the P bit ...
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Programming Flowchart and Sample Program Flowchart for Programming One Byte Start Set erase block register (set bit for block to be programmed to 1) Write data to flash memory (flash memory latches write address *1 and data ...
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Sample Program for Programming One Byte This program uses the following registers: R0H: Used for erase block specification. R1H: Stores programming data. R1L: Stores read data. R3: Stores the programming address. Valid address specifications are H'0000 to H'EF7F. R4: Used ...
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LOOP2: DEC R4H BNE LOOP2 MOV.B @R3, CMP.B R1H, BEQ PVOK BCLR #2, CMP.B #H'06, BEQ NGEND ADD.W R5, BRA PRGMS PVOK: BCLR #2, MOV.B #H'00, MOV.B R6L, One byte programmed NGEND: Programming error 134 ; ; Wait loop R1L ...
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Erase Mode To erase the flash memory, follow the erasing algorithm shown in figure 6.15. This erasing algorithm enables data to be erased without subjecting the device to voltage stress or impairing the reliability of the programmed data. To ...
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Erase Flowcharts and Sample Programs Flowchart for Erasing One Block Start Set erase block register (set bit for block to be erased to 1) Write 0 data in all addresses to be erased (prewrite Enable watchdog ...
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Prewrite Flowchart Start Set erase block register (set bit for block to be programmed Set start address Write H'00 to flash memory (flash memory latches programmed address *1 and data) Enable watchdog timer *2 ...
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Sample Program for Erasing One Block This program uses the following registers: R0: Used for erase block specification. Also stores address used in prewrite and erase-verify. R1H: Stores read data. Also used in dummy write. R2: Stores last address of ...
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MOV.B R4L, MOV.W R5, BSET #0, LOOPR1: SUBS #1, MOV.W R4, BNE LOOPR1 BCLR #0, MOV.B #H'50, MOV.B R4L, MOV.B #H'c, LOOPR2: DEC R4H BNE LOOPR2 MOV.B @R3, BEQ PWVFOK CMP.B #H'06, BEQ ABEND1 ADD.W R5, BRA PREWRS ABEND1: Write ...
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LOOPEV: DEC R4H BNE LOOPEV EVR2: MOV.B #H'FF, MOV.B R1H, MOV.B #H'c, LOOPDW: DEC R4H BNE LOOPDW MOV.B @R3+, CMP.B #H'FF, BNE RERASE CMP.W R2, BNE EVR2 BRA OKEND RERASE: BCLR #3, SUBS #1, MOV.W #H'0004, CMP.W R4, BPL BRER ...
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Flowchart for Erasing Multiple Blocks Set erase block register (set bit for block to be erased to 1) Write 0 data in all addresses to be erased (prewrite) Enable watchdog timer Select erase mode (E bit = 1 in FLMCR) ...
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Sample Program for Erasing Multiple Blocks This program uses the following registers: R0: Used for erase block specification (set as explained below). Also stores address used in prewrite and erase-verify. R1H: Used to test bits R0. ...
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Notes this sample program, the stack pointer (SP) is set to address H'FF80. On-chip RAM addresses H'FF7E and H'FF7F are used as a stack area. Therefore addresses H'FF7E and H'FF7F should not be used when this program is ...
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Execute prewrite PREWRT: MOV.W @R2+, PREW: MOV.B #H'00, MOV.W #H'a, PREWRS: INC R6L MOV.B #H'00 MOV.B R1H, MOV.W #H'FE5A, MOV.B R4L, MOV.B R4H, MOV.B #H'36, MOV.B R4L, MOV.W R5, BSET #0, LOOPR1: SUBS #1, MOV.W R4, BNE LOOPR1 BCLR ...
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BSET #1, LOOPE: NOP NOP NOP NOP SUBS #1, MOV.W R4, BNE LOOPE BCLR #1, MOV.B #H'50, MOV.B R4L, ; Execute erase-verify EVR: MOV.W #RAMSTR, R2 MOV.W #ERVADR, R3 ADD.W R3, MOV.W #START, SUB.W R3, MOV.B #H'00, MOV.B #H'b, BSET ...
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CMP.W R4, BNE EVR2 CMP.B #H'08, BMI SBCLR MOV.B R1L, SUBX #H'08, BCLR R1H, BRA BLKAD SBCLR: BCLR R1L, BLKAD: INC R1L BRA EBRTST HANTEI: BCLR #3, MOV.B R0H, MOV.B R0L, MOV.W R0, BEQ EOWARI MOV.W #H'0004, CMP.W R4, BPL ...
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Loop Counter and Watchdog Timer Overflow Interval Settings in Programs: The settings of #a, #b, #c, #d, and #e in the program examples depend on the clock frequency. Sample loop counter settings for typical operating frequencies are shown in table ...
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Formula operating frequency other than those shown in table 6.12 is used, the values can be calculated using the formula shown below. The calculation is based on an operating frequency (ø MHz. For a (ø) and ...
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Prewrite-Verify Mode Prewrite-verify mode is a verify mode used to all bits to equalize their threshold voltages before erasure. To program all bits, write H'00 in accordance with the prewrite algorithm shown in figure 6.16. Use this procedure to ...
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Hardware Protection: Hardware protection refers to a state in which programming/erasing of flash memory is forcibly suspended or disabled. At this time, the flash memory control register (FLMCR) and erase block register (EBR1 and EBR2) settings are cleared. Details of ...
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Flash Memory PROM Mode (H8/3644F, H8/3643F, and H8/3642AF) 6.8.1 PROM Mode Setting The H8/3644F, H8/3643F, and H8/3642AF, in which the on-chip ROM is flash memory, have a PROM mode as well as the on-board programming modes for programming and ...
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MPU mode H'0000 H'7FFF* Note: * This example applies to the H8/3644F. This address is H'5FFF in the H8/3643F, and H'3FFF in the H8/3642AF. Figure 6.18 Memory Map in PROM Mode 152 H8/3644F PROM mode H'0000 On-chip ROM area H'7FFF* ...
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H8/3644F, H8/3643F, H8/3642AF Pin # TFP-80C FP-64A DP-64S ...
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Operation in PROM Mode The program/erase/verify specifications in PROM mode are the same as for the standard HN28F101 flash memory. The H8/3644F, H8/3643F, and H8/3642AF do not have a device recognition code, so the programmer cannot read the device ...
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Table 6.16 PROM Mode Commands Command Cycles Memory read 1 Erase setup/erase 2 Erase-verify 2 Auto-erase setup/ 2 auto-erase Program setup/ 2 program Program-verify 2 Reset 2 PA: Program address EA: Erase-verify address RA: Read address PD: Program data PVD: ...
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High-Speed, High-Reliability Programming: Unused areas of the flash memory in the H8/3644F, H8/3643F, or H8/3642AF contain H'FF data (initial value). The flash memory uses a high-speed, high-reliability programming procedure. This procedure provides higher programming speed without subjecting the device to ...
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High-Speed, High-Reliability Erasing: The flash memory in the H8/3644F, H8/3643F, and H8/3642AF uses a high-speed, high-reliability erasing procedure. This procedure provides higher erasing speed without subjecting the device to voltage stress and without sacrificing the reliability of data reliability. Figure ...
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Table 6.17 DC Characteristics in PROM Mode (Conditions 5 Item Input high OE, CE, WE voltage Input low ...
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Table 6.18 AC Characteristics in PROM Mode (Conditions 5 Item Command write cycle Address setup time Address hold time Data setup time Data hold time CE setup time CE hold time V setup time ...
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VPS 5.0 V Address CE t CES WEP OEWS I/O7 I/O0 to I/O6 160 Auto-erase setup t CEH t t CWC OEPS t CES t ...
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Program setup 5 5 VPS Address CE t CES t OE CWC t WEP t t CEH OEWS t WE WEH Command I/O7 input Command I/O0 to ...
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Erase setup 5 VPS 5.0 V Address OEWS t t WEP CES WE t CEH I/O0 to I/O7 Command input Note: Erase -verify data output ...
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... Program with the specified voltages and timing. The rated programming voltage (V If the PROM programmer is set to Hitachi HN28F101 specifications, V Applied voltages in excess of the rating can permanently damage the device. In particular, insure that the peak overshoot of the PROM programmer does not exceed the maximum rating ...
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Oscillation must have stabilized (following the elapse of the oscillation settling time stopped. When the V CC oscillation settling time* — The MCU must be in the reset state state in which reset has ...
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OSC1 ø 3 (boot mode (user program mode) RES Period ...
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Design a current margin into the programming voltage (V Insure that V remains within the range 12.0 V 0.6 V (11 12.6 V) during PP programming and erasing. Programming and erasing may become impossible outside this range. ...
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To check for 12 V application/non-application in user mode When address H'FF80 is accessed in user mode being applied read/written to, and its initial value after reset is H'80. When 12 V ...
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Table 6.20 Flash Memory AC Characteristics 12 – +75 C (regular specifications), T ...
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Overview The H8/3644 Series has 1 kbyte and 512 byte of high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.1 ...
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Overview The H8/3644 Series is provided with three 8-bit I/O ports, three 5-bit I/O ports, two 3-bit I/O ports, and one 8-bit input-only port. Table 8.1 indicates the functions of each port. Each port has of a port control ...
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Table 8.1 Port Functions (cont) Port Description Port 6 8-bit I/O port High-current port Port 7 5-bit I/O port Port 8 8-bit I/O port Port 9 5-bit I/O port Port B 8-bit input port Note: * There ...
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Port 1 8.2.1 Overview Port 5-bit I/O port. Figure 8.1 shows its pin configuration. 8.2.2 Register Configuration and Description Table 8.2 shows the port 1 register configuration. Table 8.2 Port 1 Registers Name Port data register ...
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Port Data Register 1 (PDR1) Bit Initial value 0 Read/Write R/W Note: * Bits are reserved; they are always read as 0 and cannot be modified. PDR1 is an 8-bit register that stores data ...
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PUCR1 controls whether the MOS pull-up of each of the port 1 pins P1 or off. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS pull-up for the corresponding pin, ...
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Bit 5—P1 /IRQ Pin Function Switch (IRQ1): This bit selects whether pin IRQ Bit 5: IRQ1 Description 0 Functions as P1 Functions as IRQ 1 Note: Rising or falling edge sensing ...
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Pin Functions Table 8.3 shows the port 1 pin functions. Table 8.3 Port 1 Pin Functions Pin Pin Functions and Selection Method P1 /IRQ /TRGV The pin function depends on bit IRQ3 in PMR1 and bit PCR1 7 3 ...
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Pin States Table 8.4 shows the port 1 pin states in each operating mode. Table 8.4 Port 1 Pin States Pins Reset P1 /IRQ /TRGV High impedance P1 /IRQ /IRQ /PWM ...
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Port 2 8.3.1 Overview Port 3-bit I/O port, configured as shown in figure 8.2. 8.3.2 Register Configuration and Description Table 8.5 shows the port 2 register configuration. Table 8.5 Port 2 Registers Name Port data register ...
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Port Control Register 2 (PCR2) Bit 7 — Initial value 0 Read/Write — PCR2 is an 8-bit register for controlling whether each of the port 1 pins P2 input pin or output pin. Setting a PCR2 bit to 1 makes ...
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Pin Functions Table 8.6 shows the port 2 pin functions. Table 8.6 Port 2 Pin Functions Pin Pin Functions and Selection Method P2 /TXD The pin function depends on bit TXD in PMR7 and bit PCR2 2 TXD PCR2 ...
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Port 3 8.4.1 Overview Port 8-bit I/O port, configured as shown in figure 8.3. 8.4.2 Register Configuration and Description Table 8.8 shows the port 3 register configuration. Table 8.8 Port 3 Registers Name Port data register ...
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PDR3 is an 8-bit register that stores data for port 3 pins P3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are ...
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Port Mode Register 3 (PMR3) Bit 7 — Initial value 0 Read/Write — PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. Upon reset, PMR3 is initialized to H'00. Bits 7 to 3—Reserved ...
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Port Mode Register 7 (PMR7) Bit 7 — Initial value 0 Read/Write — PMR7 is an 8-bit read/write register that turns the PMOS transistors of pins and P3 off. Upon reset, PMR7 is initialized to H'F8. Bits 7 to 3—Reserved ...
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Pin Functions Table 8.9 shows the port 3 pin functions. Table 8.9 Port 3 Pin Functions Pin Pin Functions and Selection Method P3 /SO The pin function depends on bit SO1 in PMR3 and bit PCR3 2 1 SO1 ...
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Pin States Table 8.10 shows the port 3 pin states in each operating mode. Table 8.10 Port 3 Pin States Pins Reset Sleep P3 /SO High- Retains 2 1 impedance previous P3 / state P3 /SCK 0 ...
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Port 5 8.5.1 Overview Port 8-bit I/O port, configured as shown in figure 8.4. 8.5.2 Register Configuration and Description Table 8.11 shows the port 5 register configuration. Table 8.11 Port 5 Registers Name Port data register ...
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Port Data Register 5 (PDR5) Bit Initial value 0 Read/Write R/W PDR5 is an 8-bit register that stores data for port 5 pins P5 bits are set to 1, the values stored in PDR5 are read, regardless ...
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Pin Functions Table 8.12 shows the port 5 pin functions. Table 8.12 Port 5 Pin Functions Pin Pin Functions and Selection Method P5 /INT The pin function depends on bit PCR5 7 7 PCR5 7 Pin function P5 /INT ...
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Pin States Table 8.13 shows the port 5 pin states in each operating mode. Table 8.13 Port 5 Pin States Pins Reset Sleep P5 /INT to High- Retains /INT impedance previous 0 0 state Note: * ...
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Port 6 8.6.1 Overview Port 8-bit large-current I/O port, with a maximum sink current of 10 mA. The port 6 pin configuration is shown in figure 8.5. 8.6.2 Register Configuration and Description Table 8.14 shows the ...