MACH210-12JC Lattice Semiconductor Corp., MACH210-12JC Datasheet
MACH210-12JC
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MACH210-12JC Summary of contents
Page 1
... PAL blocks. This allows designs to be placed and routed efficiently. The MACH210 has two kinds of macrocell: output and buried. The MACH210 output macrocell provides regis- COM’L: -7/10/12/15/20, Q-12/15/20 Peripheral Component Interconnect (PCI) ...
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... Macrocells Macrocells 8 8 I/O Cells 8 I/O –I I/O –I I/O Cells 8 8 Macrocells AND Logic Array and Logic Allocator 22 Switch Matrix AND Logic Array and Logic Allocator OE Macrocells I/O Cells 8 I/O –I MACH210-7/10/12/15/20, Q-12/15/20 I – – Macrocells Macrocells 8 CLK / CLK / 14128I-1 ...
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... CONNECTION DIAGRAM Top View I/O 5 I GND CLK I/O 8 I/O 9 I/O 10 I/O 11 Note: Pin-compatible with MACH110, MACH111, MACH211, and MACH215. PLCC MACH210-7/10/12/15/20, Q-12/15/ I CLK GND 14128I-2 3 ...
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... I/O5 I/O6 I/ GND CLK0/I2 I/O8 I/O9 I/O10 I/O11 Note: Pin-compatible with MACH111 and MACH211. PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V = Supply Voltage CC 4 TQFP MACH210-7/10/12/15/20, Q-12/15/20 I/O27 I/O26 I/O25 I/O24 CLK1/I5 GND I4 I3 I/O23 I/O22 I/O21 14128I-3 ...
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... The Valid Combinations table lists configurations planned to be supported in volume for this device. Con- sult your local sales office to confirm availability of specific valid combinations or to check on newly re- leased combinations. MACH210-7/10/12/15/20, Q-12/15/20 (Com’l) C OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS C = Commercial ( +70 C) ...
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... The Valid Combinations table lists configurations planned to be supported in volume for this device. Con- sult your local sales office to confirm availability of specific valid combinations or to check on newly re- leased combinations. MACH210-12/14/18/24 (Ind) OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS I = Industrial (– +85 C) ...
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... The Logic Allocator The logic allocator in the MACH210 takes the 64 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven product terms. The design software automatically configures the logic allocator when fitting the design into the device ...
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... The I/O Cell The I/O cell in the MACH210 consists of a three-state output buffer. The three-state buffer can be configured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to all I/O cells in a PAL block ...
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... Switch Matrix Figure 1. MACH210 PAL Block MACH210-7/10/12/15/20, Q-12/15/20 Output Enable Output Enable Asynchronous Reset Asynchronous Preset I/O Cell Output M Macro 0 cell 2 Buried Macro M cell 1 2 I/O Cell Output M Macro 2 cell 2 Buried M Macro 3 cell 2 C I/O 0 Cell Output C M Macro 1 4 cell ...
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... Max (Note 5. Max OUT (Note Max OUT (Note 0 Max (Note 3) OUT Outputs Open ( 5 MHz (Note 4) and I (or I and OZL IH OZH MACH210A-7 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 = 0 mA) 130 OUT Unit ...
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... Setup Time from Input, I/O, or Feedback Through SLL Transparent Input Latch to Output Latch Gate Test Conditions MHz OUT D-Type T-Type LOW HIGH D-Type T-Type D-Type ) CNT T-Type D-Type T-Type LOW HIGH MACH210A-7 (Com’l) Typ Unit = Min Max Unit 7.5 ns 5 100 ...
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... APR t Input, I/O, or Feedback to Output Enable EA t Input, I/O, or Feedback to Output Disable ER Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 12 MACH210A-7 (Com’l) -7 Min Max Unit 11.5 ns ...
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... Max (Note Max (Note 5. Max OUT (Note Max OUT (Note 0 Max (Note 3) OUT 5V MHz CC A (Note 4) and I (or I and OZL IH OZH MACH210A-10/12 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 135 Unit ...
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... Input Latch Gate to Output Latch Setup IGS 14 Test Conditions MHz OUT D-Type T-Type LOW HIGH D-Type 1/( T-Type D-Type ) CNT T-Type 1/( D-Type T-Type LOW HIGH 1/( WICL WICH MACH210A-10/12 (Com’l) Typ Unit = -10 -12 Min Max Min Max Unit 6 7 66.7 MHz 74 62.5 MHz 100 83.3 ...
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... Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. MACH210A-10/12 (Com’l) -10 -12 Min Max Min ...
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... Max (Note Max (Note 5. Max OUT (Note Max OUT (Note 0 Max (Note 3) OUT 5V MHz CC A (Note 4) and I (or I and OZL IH OZH MACH210A-12/14 (Ind) ) Operating – + with +4 +5.5 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 135 Unit ...
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... Input Latch Gate to Output Latch Setup IGS Test Conditions MHz OUT D-Type T-Type LOW HIGH D-Type 1/( T-Type D-Type ) CNT T-Type 1/( D-Type T-Type LOW HIGH 1/( WICL WICH MACH210A-12/14 (Ind) Typ Unit = -12 -14 Min Max Min Max Unit MHz 59 50 MHz 80 61 ...
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... Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. 18 MACH210A-12/14 (Ind) -12 -14 Min Max Min Max ...
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... Max (Note Max (Note 5. Max OUT (Note Max OUT (Note 0 Max (Note 3) OUT 5V MHz CC A (Note 4) and I (or I and OZL IH OZH MACH210-12/15/20 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –10 10 –10 –30 –160 120 Unit ...
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... LOW 6 HIGH 6 D-type 66.7 1/( T-type 62.5 D-type 83.3 ) CNT T-type 76.9 1/( 83 D-type 12 T-type 13 LOW 6 HIGH 6 1/( 83.3 WICL WICH MACH210-12/15/20 (Com’l) Typ Unit = -15 -20 Min Max Min Max Unit MHz 47.6 38.5 MHz 66.6 50 MHz 62.5 47.6 MHz 83 ...
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... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. -12 Min Max MACH210-12/15/20 (Com’l) -15 -20 Min Max Min Max Unit ...
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... Voltage for all Inputs (Note 1) VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VCC = MHz (Note 4) MACH210-14/18/24 (Ind – +5.5 V ...
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... D-type 53 1/(tS + tCO) T-type 50 D-type 61.5 T-type 57 1/(tWL + tWH) 66.5 8 7 14.5 D-type 16 T-type LOW 7.5 HIGH 7.5 1/(tWICL + tWICH ) 66.5 2 7.5 19.5 MACH210-14/18/24 (Ind) Typ Unit -18 -24 Min Max Min Max Unit 13 14 MHz 38 30 ...
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... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. 24 -14 Min Max 19.5 14.5 10 19.5 14.5 10 14.5 14.5 MACH210-14/18/24 (Ind) -18 -24 Min Max Min Max Unit ...
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... Voltage for all Inputs (Note 5. Max (Note Max (Note 5. Max OUT (Note Max OUT (Note 0 Max (Note 3) OUT MHz CC A (Note 4) and I (or I and OZL IH OZH MACH210AQ-12 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 45 Unit ...
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... Transparent Input Latch to Output Latch Gate t Input Latch Gate to Output Latch Setup IGS 26 Test Conditions MHz OUT D-type T-type LOW HIGH D-type T-type D-type ) CNT T-type D-type T-type LOW HIGH MACH210AQ-12 (Com’l) Typ Unit = -12 Min Max Unit 55.6 MHz 52.6 MHz 83.3 MHz 76 ...
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... Input, I/O, or Feedback to Output Disable ER Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. MACH210AQ-12 (Com’l) -12 Min Max Unit 6 ns ...
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... Voltage for all Inputs (Note 5. Max (Note Max (Note 5. Max OUT (Note Max OUT (Note 0 Max (Note 3) OUT 5V MHz CC A (Note 4) and I (or I and OZL IH OZH MACH210AQ-15/20 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 45 Unit ...
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... Input Latch Gate to Output Latch Setup IGS Test Conditions MHz OUT D-type T-type LOW HIGH D-type 1/( T-type D-type ) CNT T-type D-type 1/( T-type D-type T-type LOW HIGH 1/( WICL WICH MACH210AQ-15/20 (Com’l) Typ Unit = -15 -20 Min Max Min Max Unit MHz 47.6 38.4 MHz 58.8 45 ...
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... Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. 30 MACH210AQ-15/20 (Com’l) -15 -20 Min Max Min ...
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... Voltage for all Inputs (Note 1) VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VCC = MHz (Note 4) MACH210AQ-18/24 (Ind – +5.5 V ...
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... Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 32 Test Conditions VIN = 2.0 V VCC = 5 VOUT = 2 MHz D-type T-type LOW HIGH D-type 1/(tS + tCO) T-type D-type T-type D-type 1/(tS + tH) T-type D-type T-type LOW HIGH 1/(tWICL + tWICH ) MACH210AQ-18/24 (Ind) Typ Unit -18 -24 Min Max Min Max Unit 20 ...
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... Input, I/O, or Feedback to Output Disable (Note 3) Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. MACH210AQ-18/24 (Ind) -18 -24 Min Max Min ...
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... CC A –1.0 34 (mA –0.8 –0.6 –0.4 –0 –20 –40 –60 –80 Output, LOW I (mA –3 –2 –1 –25 –50 –75 –100 –125 –150 Output, HIGH I (mA –2 – –20 –40 –60 –80 –100 Input MACH210-7/10/12/15/20, Q-12/15/ 1.0 14128I (V) OH 14128I 14128I-7 ...
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... The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register. MACH210AQ Frequency (MHz) MACH210-7/10/12/15/20, Q-12/15/20 MACH210A MACH210 80 90 100 14128I-8 35 ...
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... Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 36 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air MACH210-7/10/12/15/20, Q-12/15/20 Typ TQFP PLCC Unit 11.3 15 ...
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... V T Out 14128I-10 Gate t WL 14128I- Registered Input t HIR Input V T Register Clock t ICO V T Output Register Clock 14128I-14 MACH210-7/10/12/15/20, Q-12/15/ 14128I PDL Latched Output (MACH 2, 3, and GWS Gate Width (MACH 2, 3, and ICS V T Input Register to Output Register Setup ...
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... Latch Gate t IGS Output Latch Gate Notes 1 Input pulse amplitude 3 Input rise and fall times 2 ns–4 ns typical SIL HIL Latched Input (MACH 2 and 4) t IGOL Latched Input and Output (MACH 2, 3, and 4) MACH210-7/10/12/15/20, Q-12/15/ IGO V T 14128I-16 t PDLL SLL V T 14128I-17 ...
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... Input rise and fall times 2 ns–4 ns typical. Input V Latch T Gate t WICL 14128I-18 Input, I/ Feedback Registered V T Output t ARR Clock V T 14128I- Outputs + V OL Output Disable/Enable MACH210-7/10/12/15/20, Q-12/15/20 t WIGL Input Latch Gate Width (MACH 2 and 4) t APW Asynchronous Preset 0. 0.5V 14128I- 14128I- APR V T 14128I-21 39 ...
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... Don’t Care, Any Change Permitted Does Not Apply Output Commercial 300 390 5 pF MACH210-7/10/12/15/20, Q-12/15/20 OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “Off” State KS000010-PAL Test Point 14128I-23 Measured R Output Value 2 1 ...
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... All frequencies except f MAX other measured AC parameters. f ured directly. ” (SECOND CHIP MACH210-7/10/12/15/20, Q-12/15/ type is the mini- MAX + t ). Usually, this minimum feedback.” MAX . Because this involves no MAXIR + the sum of SIR HIR + t ). The clock widths are nor- WICL ...
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... Min Pattern Data Retention Time Max Reprogramming Cycles 42 bipolar parts result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Min 10 20 100 MACH210-7/10/12/15/20, Q-12/15/20 Units Test Conditions Years Max Storage Temperature Years Max Operating Temperature Cycles Normal Programming Conditions ...
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... INPUT/OUTPUT EQUIVALENT SCHEMATICS ESD Protection 1 k Input 100 k Preload Feedback Circuitry Input I/O MACH210-7/10/12/15/20, Q-12/15/ 100 14128I-25 43 ...
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... Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met Power-Up Reset Waveform MACH210-7/10/12/15/20, Q-12/15/20 can rise to its steady state, two CC rise must be monotonic. Max 10 See Switching Characteristics V CC 14128I-26 ...
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... All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support. On Preload Off Mode Figure 2. Preload/Reset Conflict Set Reset MACH210-7/10/12/15/20, Q-12/15/20 Preloaded HIGH Preloaded HIGH Figure 3. Combinatorial Latch 14128I-27 ...
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... Pin 1 I.D. .685 .695 .650 .656 .026 .050 REF .032 TOP VIEW 50 .062 .083 .042 .056 .009 .015 .165 .180 MACH210-7/10/12/15/20, Q-12/15/20 .500 .590 REF .630 .013 .021 .090 .120 SEATING PLANE 16-038-SQ PL 044 DA78 SIDE VIEW 6-28-94 ae ...
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... Thin Quad Flat Pack (measured in millimeters 0.95 1.05 0.30 0.45 1.00 REF. *For reference only. BSC is an ANSI standard for Basic Space Centering. 9.80 10.20 9.80 10.20 11.80 12.20 11 – 13 1.20 MAX 11 – 13 0.80 BSC MACH210-7/10/12/15/20, Q-12/15/20 11.80 12.20 16-038-PQT-2_AH PQT 44 5-4- ...