DS1202 Dallas Semiconductor, DS1202 Datasheet
DS1202
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DS1202 Summary of contents
Page 1
... RST (Reset), (2) I/O (Data line), and (3) SCLK (Serial clock). Data can be transferred to and from the clock/ RAM one byte at a time burst bytes. The DS1202 is designed to operate on very low power and retain data and clock information on less than 1 mi- crowatt. DS1202, DS1202S ...
Page 2
... After the first eight clock cycles have occurred which load the command word into the shift register, additional clocks will output data for a read or input data for a write. DS1202 BLOCK DIAGRAM Figure 1 I/O INPUT SHIFT REGISTERS ...
Page 3
... Bit 7 of the seconds register is defined as the clock halt flag. When this bit is set to logic 1, the clock oscillator is stopped and the DS1202 is placed into a low–power standby mode with a current drain of not more than 100 nanoamps. When this bit is written to logic 0, the clock will start. AM– ...
Page 4
... A register data format summary is shown in Figure 4. CRYSTAL SELECTION A 32.768 KHz crystal, can be directly connected to the DS1202 via pins 2 and 3 (X1, X2). The crystal selected for use should have a specified load capacitance (CL pF. The crystal is connected directly to the X1 and X2 DATA TRANSFER SUMMARY Figure 3 ...
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... RAM RAM BURST REGISTER DEFINITION 00– 00– 01– 00–23 W 01–28/29 RD 01– 01– 01– 01– 0– RAM DATA RAM DATA DS1202, DS1202S CH 10 SEC SEC 0 10 MIN MIN DATE DATE MONTH DAY 10 YEAR YEAR WP FORCED TO ZERO 032697 5/11 ...
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... DS1202, DS1202S ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability ...
Page 7
... CDD V = =2V 1000 =5V 250 CC V =2V 1000 =5V 250 CLK CLK =2V 1000 CCH CCH V =5V 250 CWH CWH CDZ CDZ V =5V CC DS1202, DS1202S ( 2.0 to 5.5V*) CC TYP MAX UNITS NOTES 800 200 0.5 MHz MHz 2.0 2000 ns ns 500 280 032697 7/ ...
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... DS1202, DS1202S TIMING DIAGRAM: READ DATA TRANSFER Figure 5 RESET CLOCK t DC DATA INPUT/ OUTPUT TIMING DIAGRAM: WRITE DATA TRANSFER Figure 6 RESET CLOCK DATA INPUT/ OUTPUT NOTES: 1. All voltages are referenced to ground. 2. Logic one voltages are specified at a source current capacitive loads. ...
Page 9
... RST, I/O, and SCLK open. The clock halt flag must be set to logic one (oscillator disabled). CC2 11. At power–up, RST must logic 0 until logic one state. 12 exceeds 100 ms with RST in a logic one state, then I CH DS1202 SERIAL TIMEKEEPER 8–PIN DIP ...
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... DS1202, DS1202S DS1202S SERIAL TIMEKEEPER 16–PIN SOIC 032697 10/11 phi PKG DIM A IN IN. E IN. F IN. G IN. H IN. J IN 16–PIN MIN MAX 0.500 0.511 MM 12.70 12.99 0.290 0.300 MM 7.37 7.65 0.089 0.095 MM 2.26 2.41 0.004 0.012 MM 0.102 0.30 0.094 ...
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... DS1202S8 8–PIN SOIC 200 MIL 0–8 deg. typ. C DS1202, DS1202S PKG 8–PIN DIM MIN MAX A IN. 0.203 0.213 MM 5.16 5.41 B IN. 0.203 0.213 MM 5.16 5.41 C IN. 0.070 0.074 MM 1.78 1.88 E IN. 0.004 0.010 MM 0.102 0.390 F IN. 0.074 0.84 MM 1.88 2.13 G IN. ...