AM28F020A-90JC Advanced Micro Devices, AM28F020A-90JC Datasheet

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AM28F020A-90JC

Manufacturer Part Number
AM28F020A-90JC
Description
2 megabit CMOS 12.0 volt, bulk erase flash memory with embedded algorithms
Manufacturer
Advanced Micro Devices
Datasheet

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Am28F020A
2 Megabit (256 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The Am28F020A is a 2 Megabit Flash memory orga-
nized as 256 Kbytes of 8 bits each. AMD’s Flash mem-
ories offer the most cost-effective and reliable read/
write non-volatile random access memor y. The
Am28F020A is packaged in 32-pin PDIP, PLCC, and
TSOP versions. It is designed to be reprogrammed and
erased in-system or in standard EPROM programmers.
The Am28F020A is erased when shipped from
the factory.
The standard Am28F020A offers access times of as
fast as 70 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus conten-
tion, the device has separate chip enable (CE
output enable (OE
AMD’s Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F020A uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining
maximum EPROM compatibility.
T he A m2 8F0 20A i s c omp ati bl e w i th th e AM D
Am28F256A, Am28F512A, and Am28F010A Flash
memories. All devices in the Am28Fxxx family follow
the JEDEC 32-pin pinout standard. In addition, all
Publication# 17502
Issue Date: January 1998
High performance
— Access times as fast as 70 ns
CMOS low power consumption
— 30 mA maximum active current
— 100 µA maximum standby current
— No data retention power consumption
Compatible with JEDEC-standard byte-wide
32-pin EPROM pinouts
— 32-pin PDIP
— 32-pin PLCC
— 32-pin TSOP
100,000 write/erase cycles minimum
Write and erase voltage 12.0 V 5%
FINAL
Rev: D Amendment/+1
#
) controls.
#
) and
devices within this family that offer Embedded Algo-
rithms use the same command set. This offers
designers the flexibility to retain the same device foot-
print and command set, at any density between
256 Kbits and 2 Mbits.
AMD’s Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles.
The AMD cell is designed to optimize the erase and
programming mechanisms. In addition, the combina-
tion of advanced tunnel oxide processing and low
internal electric fields for erase and programming oper-
ations produces reliable cycling. The Am28F020A uses
a 12.0 5% V
programming functions.
The highest degree of latch-up protection is achieved
with AMD’s proprietary non-epi process. Latch-up pro-
tection is provided for stresses up to 100 mA on
address and data pins from –1 V to V
AMD’s Flash technology combines years of EPROM
and EEPROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The
Am28F020A electrically erases all bits simultaneously
using Fowler-Nordheim tunneling. The bytes are
programmed one byte at a time using the EPROM
programming mechanism of hot electron injection.
Latch-up protected to 100 mA from
–1 V to V
Embedded Erase Electrical Bulk Chip Erase
— Five seconds typical chip erase, including
Embedded Program
— 14 µs typical byte program, including time-out
— 4 seconds typical chip program
Command register architecture for
microprocessor/microcontroller compatible
write interface
On-chip address and data latches
Advanced CMOS flash memory technology
— Low cost single transistor memory cell
Embedded algorithms for completely self-timed
write/erase operations
pre-programming
CC
PP
+1 V
supply input to perform the erase and
CC
+1 V.

Related parts for AM28F020A-90JC

AM28F020A-90JC Summary of contents

Page 1

... TSOP 100,000 write/erase cycles minimum Write and erase voltage 12 GENERAL DESCRIPTION The Am28F020A Megabit Flash memory orga- nized as 256 Kbytes of 8 bits each. AMD’s Flash mem- ories offer the most cost-effective and reliable read/ write non-volatile random access memor y. The Am28F020A is packaged in 32-pin PDIP, PLCC, and TSOP versions ...

Page 2

... Embedded Program The Am28F020A is byte programmable using the Embedded Program algorithm, which does not require the system to time-out or verify the data programmed. The typical room temperature programming time of this device is four seconds. Comparing Embedded Algorithms with Flasherase and Flashrite Algorithms Embedded Algorithms Embedded AMD’ ...

Page 3

... Erase Voltage Switch To Array Program Voltage Switch Chip Enable Output Enable Logic Embedded Algorithms Program/Erase Pulse Timer Am28F020A Am28F020A -120 -150 -200 120 150 200 120 150 200 DQ0–DQ7 Input/Output Buffers Data Latch Y-Decoder Y-Gating X-Decoder 2,097,152 Bit Cell Matrix ...

Page 4

... DQ1 19 14 DQ2 Note: Pin 1 is marked for orientation WE# (W#) A17 A7 5 A14 A6 6 A13 A11 A2 10 OE# (G A10 A0 12 DQ0 13 CE# (E#) DQ7 DQ6 DQ5 DQ4 DQ3 17502D-2 Am28F020A PLCC A14 29 A13 A11 25 OE# (G#) 24 A10 23 22 CE# (E#) DQ7 17502D-3 ...

Page 5

... A14 5 6 A17 7 WE A16 10 A15 11 12 A12 OE# 1 A10 2 CE LOGIC SYMBOL 32-Pin TSOP—Standard Pinout 32-Pin TSOP—Reverse Pinout 18 A0–A17 DQ0–DQ7 CE# (E#) OE# (G#) WE# (W#) Am28F020A 32 OE# 31 A10 30 CE A11 A13 28 A14 27 A17 26 WE A16 22 A15 21 A12 17502D-4 ...

Page 6

... AM28F020A -70 J DEVICE NUMBER/DESCRIPTION Am28F020A 2 Megabit (256 K x 8-Bit) CMOS Flash Memory with Embedded Algorithms Valid Combinations AM28F020A-70 AM28F020A-90 AM28F020A-120 AM28F020A-150 AM28F020A-200 OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In Contact an AMD representative for more information. TEMPERATURE RANGE C = Commercial (0° ...

Page 7

... The tar- get address is latched on the falling edge of the Write Enable pulse and the appropriate data is latched on the rising edge of the pulse. Write Enable high inhibits writ- ing to the device. Am28F020A must be at high voltage 10%) 7 ...

Page 8

... WE# must be a logical zero while OE logical one. Power-Up Write Inhibit Power-up of the device with WE will not accept commands on the rising IH edge of WE#. The internal state machine is automati- cally reset to the read mode on power-up. Am28F020A CC power- The user must ensure LKO , IL and ...

Page 9

... All inputs are Don’t Care unless otherwise stated, where Don’t Care is either V addresses except A and A must be held 1.0 Volt, the voltage difference between V CC rise time and fall time specification of 500 ns minimum. Am28F020A Device Bus Operations (Notes 7 and 8) CE# OE# (E#) (G ...

Page 10

... For the device the two bytes are given in the table 2 of the device data sheet. All identifiers for manufac- turer and device codes will exhibit odd parity with the MSB (DQ7) defined as the parity bit. Table 2. (Am28F020A Auto Select Code Am28F020A (11 13 address A9. Two ...

Page 11

... In order to write, OE# must and CE# and WE# IH must any pin is not in the correct state a write IL command will not be executed. Table 3. Am28F020A Command Definitions Operation Command (Note 1) Read Memory (Note 4) Write Read Auto select Write Embedded Erase Set-up/ ...

Page 12

... Ramp Data = 30h Data = 30h # Data Polling to Verify Erasure Compare Output to FFh Available for Read Operations parameters. The V power supply can be hard-wired to the device may be ground, no connect with a resistor tied to ground, or less than V Am28F020A 17502D-6 Comments (see Note) PPH + 2.0 V. Refer CC ...

Page 13

... Wait for V Ramp Data = 10h or 50h Valid Address/Data # Data Polling to Verify Completion Available for Read Operations parameters. The V power supply can be hard-wired to the device may be ground, no connect with a resistor tied to ground, or less than V Am28F020A 17502D-7 Comments (see Note) PPH + 2.0 V. Refer CC 13 ...

Page 14

... Toggle Bit. START Read Byte (DQ0–DQ7) Addr = VA Yes DQ7 = Data ? No No DQ5 = 1 ? Yes Read Byte (DQ0–DQ7) Addr = VA Yes DQ7 = Data ? No Fail Pass Figure 3. Data # Polling Algorithm Am28F020A VA = Byte address for programming = XXXXh during chip erase 17502D-8 ...

Page 15

... CH CE# OE# t OEH WE# DQ7 DQ0–DQ6 *DQ7 = Valid Data (The device has completed the Embedded operation.) Figure 4. AC Waveforms for Data DQ7# Valid Data t WHWH DQ0–DQ6 = Invalid Polling during Embedded Algorithm Operations # Am28F020A High Z DQ7 = DQ0–DQ7 Valid Data 17502D-9 15 ...

Page 16

... See Figures 5 and 6 for the Toggle Bit timing specifica- tions and diagrams. START VA = Byte address for programming Read Byte (DQ0–DQ7) Addr = VA No DQ6 = Toggle ? Yes No DQ5 = 1 ? Yes Read Byte (DQ0–DQ7) Addr = VA No DQ6 = Toggle ? Yes Fail Pass Figure 5. Toggle Bit Algorithm Am28F020A = XXXXh during chip erase 17502D-10 ...

Page 17

... The second Reset command safely aborts the programming operation and resets the device to the Read mode. Memory contents are not altered in any case. Am28F020A DQ6 DQ0–DQ7 Stop Toggling Valid ...

Page 18

... A read cycle from address 0001h returns the device code (see the Auto Select Code table of the corresponding device data sheet). To terminate the op- eration necessary to write another valid command, such as Reset (00h or FFh), into the register. Am28F020A ...

Page 19

... V to +5. Voltages PP to Read . . . . . . . . . . . . . . . . . . . . . . . . –0 +12 Program, Erase, and Verify . . . . . . +11 +12.6 V +2.0 V for periods Operating ranges define those limits between which the CC functionality of the device is guaranteed. is –0 may overshoot PP Am28F020A ). . . . . . . . . . . .0°C to +70° .–40°C to +85° .–55°C to +125° ...

Page 20

... MAXIMUM OVERSHOOT Maximum Negative Input Overshoot +0.8 V –0.5 V –2.0 V Maximum Positive Input Overshoot 2.0 V Maximum V Overshoot PP 14 Am28F020A 17502D-12 17502D-13 17502D-14 ...

Page 21

... PP Operations V Low V Lock-out Voltage LKO CC Notes: 1. Caution: the Am28F020A must not be removed from (or inserted into) a socket when V Volt, the voltage difference between V and fall time specification of 500 ns minimum tested with simulate open outputs. CC1 IH 3. Maximum active power usage is the sum ...

Page 22

... PP Operations V Low V Lock-out Voltage LKO CC Notes: 1. Caution: the Am28F020A must not be removed from (or inserted into) a socket when V Volt, the voltage difference between V and fall time specification of 500 ns minimum tested with simulate open outputs. CC1 IH 3. Maximum active power usage is the sum ...

Page 23

... I Active Figure 7. Am28F020A - Average I TEST CONDITIONS Device Under Test C L 6.2 k Note: Diodes are IN3064 or equivalent Figure 8. Test Setup Frequency in MHz Active vs. Frequency 5.5 V, Addressing Pattern = Minmax CC Data Pattern = Checkerboard 5.0 V Test Condition Output Load 2.7 k Output Load Capacitance, C (including jig capacitance) ...

Page 24

... V for a logic “0”. Input pulse rise and fall times are 10 ns. -70 Min 70 Max 70 Max 70 Max 35 Min 0 Max 20 Min 0 Max 20 Min 0 Min 50 Am28F020A Test Points 1.5 V Input Output 17502D-17 Am28F020A Speed Options -90 -120 -150 -200 90 120 150 200 90 120 150 200 90 120 150 200 ...

Page 25

... Embedded Erase operation of 5 sec consists of 4 sec array pre-programming time and one sec array erase time. This is a typical time for one embedded erase operation. 4. Not 100% tested. Am28F020A Speed Options -70 Min 70 ...

Page 26

... Changing from Does Not Apply Center Line is High Impedance State (High Z) Device and Outputs Data Enabled Valid Addresses Stable AVAV GLQV ELQV GLQX OLZ ELQX LZ Output Valid AVQV ACC Am28F020A OUTPUTS Changing, State Unknown Standby, Power-down t EHQZ ( GHQZ ( AXQX OH High Z 17502D-18 ...

Page 27

... Addresses t WC CE# t GHWL OE WE# t CSE Data 30h t VCS VPEL Note: DQ7 # is the complement of the data written to the device. Figure 10. AC Waveforms for Embedded Erase Operation Embedded Data# Polling Erase Erase WHWH3 WPH t DH 30h DQ7# Am28F020A Read Standby DQ7 17502D-19 27 ...

Page 28

... Data 50h t VCS VPEL Notes data input to the device DQ7 # is the complement of the data written to the device the data written to the device. OUT Figure 11. AC Waveforms for Embedded Programming Operation 28 Embedded Program Data# Polling WHWH3 DQ7# DQ7# IN Am28F020A Read OUT 17502D-20 ...

Page 29

... Embedded erase operation of 5 sec consists of 4 sec array pre-programming time and one sec array erase time. This is a typical time for one embedded erase operation. 4. Not 100% tested. Am28F020A Speed Options -70 Min 70 ...

Page 30

... IN 2. DQ7 # is the complement of the data written to the device the data written to the device. OUT Figure 12. AC Waveforms for Embedded Programming Operation Using CE 30 Embedded Program CPH t t EHEH3 50h Am28F020A Data# Polling PA D DQ7# DQ7# OUT 17502D-21 Controlled Writes # ...

Page 31

... Excludes 00h programming prior to erasure 4 25 sec Excludes system-level overhead Cycles 14 µ (Note 5.0 V, one pin at a time. CC Test Conditions OUT 25° 1.0 MHz. A Test Conditions 150 C 125 C Am28F020A Comments Min Max ) –1.0 V 13.5 V –1 1 –100 mA +100 mA Typ Max Unit Min Unit 10 Years ...

Page 32

... SEATING PLANE .015 .016 .060 .022 .009 .015 .125 .140 .080 .095 SEATING PLANE .013 .021 .050 REF. Am28F020A .600 .625 .009 .015 .630 .700 0 10 16-038-S_AG PD 032 EC75 5-28-97 lv .042 .056 .400 REF. .490 .530 16-038FPO-5 PL 032 ...

Page 33

... PHYSICAL DIMENSIONS TS032—32-Pin Standard Thin Small Outline Package (measured in millimeters) Pin 1 I.D. 1 1.20 MAX 18.30 18.50 19.80 20. Am28F020A 0.95 1.05 7.90 8.10 0.50 BSC 0.05 0.15 0.08 16-038-TSOP-2 0.20 TS 032 DA95 0.10 3-25-97 lv 0.21 0.50 0.70 33 ...

Page 34

... PHYSICAL DIMENSIONS TSR032—32-Pin Reversed Thin Small Outline Package (measured in millimeters) Pin 1 I.D. 1 1.20 MAX 34 18.30 18.50 19.80 20. 0.50 0.70 Am28F020A 0.95 1.05 7.90 8.10 0.50 BSC 0.05 0.15 16-038-TSOP-2 0.08 TSR032 0.20 DA95 0.10 3-25-97 lv 0.21 ...

Page 35

... Matched formatting to other current data sheets. Revision D+1 Programming In A PROM Programmer: Deleted the paragraph “(Refer to the AUTO SELECT paragraph in the ERASE, PROGRAM, and READ = 12.0 V 5%”. PP MODE section for programming the Flash memory de- vice in-system).” Am28F020A Con ...

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