GM16C550 Hynix Semiconductor, GM16C550 Datasheet
GM16C550
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GM16C550 Summary of contents
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... GM16C450, and addition-ally incorporates a 16byte FIFOs are available on both the transmitter and receiver, and can be activated by placing the device in the FIFO mode. After a reset, the registers of the GM16C550 are identical to those of the GM16C450. The UART performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to- serial conversion on data characters received from the CPU ...
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... Note 100 ns 100 pF loading, Note Note Note 100 pF loading, Note 3 125 ns 100 pF loading, ns Note 1 ns Note External Clock (8.0 MHz Max.) ns Exrternal Clock (8.9 MHz Max.) ns Note 175 ns 100 pF load 175 ns 100 pF load MHz MHz X GM16C550 , +2, 100 pF load , +2, 100 pF load ...
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... V/3.3V CC Max Units Conditions s 100 pF load s RCLK Note 2 Cycles 175 ns 100 pF load 250 ns 100 pF load Baudout 24 Cycles Baudout 24 Note 5 Cycles Baudout 8 Note 5 Cycles Baudout 8 100 pF load Cycles 195 ns 100 pF load 200 ns 100 pF load 250 ns 100 pF load 250 ns 100 pF load GM16C550 tion ...
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... Note 2: The 2.2V and 0.8V levels are the voltages at which the timing tests are made. XIN t BHD t BLD BAUD OUT ( ) 1 BAUD OUT ( ) 2 BAUD OUT ( ) 3 BAUD OUT ( 2.2V 0.8V BAUDOUT Timing BHD t t BLD BHD BLD t BHD t BLD 6 AT Test Points 2.4V (Note 1) 0. XIN t =2 XIN CTLES LW GM16C550 2.2V (Note 2) 0.8V CYCLES ...
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... Write Cycle tAH tCH tSCW* tAW* tWR ACTIVE tDS tDH VALID DATA Read Cycle tAS tAH VALID tCS tCH VALID tCSR* tAR* tRD ACTIVE tRDD tRVD VALID DATA 7 tWA* tCSW* WC tWC ACTIVE OR ACTIVE tRA* tRCS* RC tRC ACTIVE OR ACTIVE tRDD tHZ GM16C550 ...
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... MSR) RI Note 1: See Write Cycle Timing Note 2: See Read Cycle Timing 8 CLKS START DATA BITS(5-8) PARITY START DATA(5- STOP(1 PARITY tiRS tHR tMR tSI tMDO tSIM tSIM tRIM 8 GM16C550 tSCD STOP tSINT tRIN ACTIVE START tSTI tIR tMDO tRIM tSIM ...
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... TOP BYTE OF FIFO tSINT tRINT ACTIVE ACTIVE PREVIOUS BYTE READ FROM FIFO SIN STOP tSINT NOTE FIFO OR ABOVE TRIGGER LEVEL FIFO BELOW TRIGGER LEVEL tRINT tRINT ACTIVE FIFO AT OR ABOVE TRIGGER LEVEL (FIFO BELOW tRINT TRIGGER LEVEL) ACTIVE ACTIVE NOTE 1 tRINT GM16C550 ...
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... RCVR FIFO Byte Other Than First Byte (RDR is Already Set) WR, WR (WRTHR) SOUT TXRDY Transmitter Ready (pin 24) FCRO = 1 and FCR = 1 (Mode (WRTHR) SOUT TXRDY SIN STOP tSINT NOTE 2 BYTE 1 DATA PARITY tWXI BYTE 16 PARITY DATA STOP FIFO FULL tWXI 10 ACTIVE NOTE 1 tRINT START STOP tSXA START tSXA GM16C550 ...
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... REGISER FIFO CONTROL REGISTER 11 RECEIVER SHIFT REGISTER RECEIVER TIMING & CONTROL BAUD GENERATOR RECEIVER TIMING & CONTROL FIFO TRANSTMTTER HOLDING REGISTER MONDEM CONTROL LOGIC INTERRUPT CONTROL LOGIC GM16C550 (10) SIN (9) RCLK (15) BAUDIUT (11) SOUT (32) RTS (36) CTS (33) DTR (37) DSR (38) DCD (39) R1 (34) OUT1 (31) OUT2 (30) INTR ...
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... MODEM Status Interrupt is enabled. whose condition can be tested by the CPU reading bit the MODEM Status Register. Bit 6is the complement of the RI signal. Bit 2 (TERI) of the MODEM 12 GM16C550 Register Receiver Buffer (read) Transmitter Holding Register (Write) Interrupt Enable ...
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... UART and the CPU, Data, control words. And status information are transferred via the D7-D0 Data Bus. External Clock Input/Output (XIN, XOUT), Pins 16 and 17: These two pins connect the main timing reference (crystal or signal clock) to the UART. 13 GM16C550 ...
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... Read LSR/MR Read RBR/MR Read IIR/Write THR/MR Read MSR/MR Master Reset Master Reset Master Reset Master Reset MR/RCR1-FCR0/ FCR0 MR/RCR1-FCR0/ FCR0 14 GM16C550 Reset State 0000 0000 (Note 1) 0000 0001 0000 0000 0000 0000 0000 0000 0110 0000 xxxx 0000 (Note 2) High Low ...
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... GM16C550 ...
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... Baud Generator during a Read or Write operation. It must be set low (logic 0) to access the Receiver Buffer, the Transmitter Holding Register, or the Interrupt Enable Register. OSC CLOCK TO BAUD GEN. LOGIC 16 GM16C550 a computer communications system. If the following sequence is followed. no erroneous or extraneous characters will be transmitted because of the break. VCC XIN ...
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... 1.5k 10-30pF 1.5k 10-30pF Decimal Divisor Used to Generate 16 Clock 2304 1536 1047 857 768 384 192 GM16C550 40-60pF 40-60pF Percent Error Difference Between Desired and Actual - - 0.026 0.058 – – – – 0. 2.86 ...
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... Decimal Divisor Used to Generate 16 Clock 10000 6667 4545 3717 3333 1667 833 417 277 250 208 139 104 GM16C550 Percent Error Difference Between Desired and Actual - - 0.026 0.034 - - - - 0.312 - - 0.628 - 1. Percent Error Difference Between Desired and Actual - 0.005 0.010 0.013 ...
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... GM16C550 ...
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... FIFO CONTROL REGISTER This is a write only register at the same location as the IIR (the IIR is a read only register). This register is used to enable the FIFOs, set the RCVR FIFO trigger level, and select the type of DMA signaling. 20 GM16C550 ...
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... Serial output (SOUT) is set to the Marking (logic 1) State; the receiver Serial Input (SIN) is disconnected; the output of the Transmitter Shift 21 an EIA inverting line driver (such as the GD751- 88) to obtain the proper polarity input at the succ- eeding MODEM or data set. GM16C550 to that ...
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... FIFO the most recent serial character received was longer than 4 continuous character times ago (if 2 stop bits are programmed the second one is included in this time delay). The most recent CPU read if the FIFO was longer than 4continuous character times age. GM16C550 ...
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... XMIT FIFOs still fully capable of holding characters. XTAL1 A –A LATCH 0 2 ADDRESS XTAL2 CS2 DECODER + 5 CS1 CS0 RCLK MR SOUT GM16C550 SIN RST D – –D DTR 0 7 DSR DCD CTS DISTR RI DOSTR INTRPT DISTR TXRDY DOSTR DDIS ADS RXRDY GM16C550 EIA RS-232-C D DRIVERS INTERFACE ...