CY7C4291-25JC Cypress Semiconductor Corporation., CY7C4291-25JC Datasheet

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CY7C4291-25JC

Manufacturer Part Number
CY7C4291-25JC
Description
64K / 128K x 9 Deep Sync FIFOs
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Cypress Semiconductor Corporation
Document #: 38-06007 Rev. *C
Features
Logic Block Diagram
• High-speed, low-power, first-in first-out (FIFO)
• 64K × 9 (CY7C4281)
• 128K × 9 (CY7C4291)
• 0.5-micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
• Low power
• Fully asynchronous and simultaneous read and write
• Empty, Full, and programmable Almost Empty and
• TTL compatible
• Output Enable (OE) pin
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Pin-compatible density upgrade to CY7C42X1
• Pin-compatible density upgrade to
RS
memories
times)
— I
— I
operation
Almost Full status flags
family
IDT72201/11/21/31/41/51
CC
SB
WCLK
= 40 mA
= 2 mA
CONTROL
POINTER
WEN1
WRITE
WRITE
RESET
LOGIC
WEN2/LD
OUTPUT REGISTER
THREE-STATE
RAMARRAY
REGISTER
128K x 9
Dual Port
64K x 9
INPUT
Q
D
0–8
0–8
OE
3901 North First Street
RCLK
PROGRAM
REGISTER
CONTROL
POINTER
FLAG
LOGIC
FLAG
READ
READ
REN1 REN2
64K/128K x 9 Deep Sync FIFOs
Functional Description
The
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4281/91 are pin-compatible to the
CY7C42X1
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor inter-
faces, and communications buffering.
These FIFOs have nine-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running read clock (RCLK) and two
read
CY7C4281/91 has an output enable pin (OE). The read
(RCLK) and write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock
frequencies up to 100 MHz are achievable. Depth expansion
is possible using one enable input for system control, while the
other enable is controlled by expansion logic to direct the flow
of data.
• Pb-Free Packages Available
EF
PAE
PAF
FF
CY7C4281/91
CY7C4281 CY7C429164K/128K x 9 Deep Sync FIFOs
enable
Pin Configuration
REN1
RCLK
REN2
Synchronous
GND
PAE
PAF
San Jose
OE
D
D
pins
1
0
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
4 3 2 1
(REN1,
are
CY7C4281
CY7C4291
,
Top View
CA 95134
PLCC
high-speed,
FIFO
32
REN2).
31 30
29
28
27
26
25
24
23
22
21
Revised August 2, 2005
family.
RS
WEN1
WCLK
WEN2/LD
V
Q
Q
Q
Q
CC
8
7
6
5
In
low-power
CY7C4281
CY7C4291
408-943-2600
Programmable
addition,
FIFO
the

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CY7C4291-25JC Summary of contents

Page 1

... LOGIC THREE-STATE OUTPUT REGISTER Q 0–8 Cypress Semiconductor Corporation Document #: 38-06007 Rev. *C CY7C4281 CY7C429164K/128K x 9 Deep Sync FIFOs 64K/128K x 9 Deep Sync FIFOs • Pb-Free Packages Available Functional Description The CY7C4281/91 memories with clocked read and write interfaces. All are nine bits wide ...

Page 2

... I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected HIGH, the FIFO’s outputs are in High Z (high-impedance) state. CY7C4291 128k x 9 32-pin PLCC 7C4281/91-10 100 0.5 8 Commercial 40 Industrial 45 CY7C4281 CY7C4291 Description 7C4281/91-15 7C4281/91-25 66 Page ...

Page 3

... Default Value = 000h Figure 1. Offset Register Location and Default Values CY7C4281 CY7C4291 64K × 9 128K× Empty Offset (LSB) Reg. Empty Offset (LSB) Reg. Default Value = 007h Default Value = 007h 0 8 (MSB) Default Value = 000h ...

Page 4

... Empty Offset ( default value Full Offset ( default value). Document #: 38-06007 Rev. *C and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4281 (64K-m) and CY7C4291 (128K-m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m. ...

Page 5

... Figure 2. Block Diagram of 64k x 9/128k x 9 Deep Sync FIFO Memory Used in a Width Expansion Configuration Document #: 38-06007 Rev. *C RESET (RS) 9 CY7C4281/ Read Enable 2 (REN2) CY7C4281 CY7C4291 READ CLOCK (RCLK) READ ENABLE 1 (REN1) OUTPUT ENABLE (OE) PROGRAMMABLE(PAE) EMPTY FLAG (EF) #1 EMPTY FLAG (EF DATA OUT (Q) 9 ...

Page 6

... V = Max < V < Com’l Ind Com’l Ind Description Test Conditions MHz 5.0V CC [9, 10] 3.0V R2 GND 680: 1.91V . OHZ CY7C4281 CY7C4291 [4] Ambient Temperature + [ + 40 7C42X110 7C42X115 7C42X125 Min. Max. Min. Max. Min. 2.4 2.4 2.4 0.4 0.4 2.0 V 2 0.8 ...

Page 7

... Almost-Empty Flag and Almost-Full Flag Notes: 11. Pulse widths less than minimum values are not allowed. 12. Values guaranteed by design, not currently tested. Document #: 38-06007 Rev. *C 7C42X1-10 Description Min. 4.5 4.5 0.5 0.5 [12] [12] CY7C4281 CY7C4291 7C42X1-15 7C42X1-25 Max. Min. Max. Min. 100 66 ...

Page 8

... CLKL t ENH NO OPERATION t REF [14] t SKEW1 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4281 CY7C4291 ENH NO OPERATION NO OPERATION t WFF t REF VALID DATA t OHZ Page ...

Page 9

... Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers. Document #: 38-06007 Rev RSS t RSS t RSS t RSF t RSF t RSF CY7C4281 CY7C4291 t RSR t RSR t RSR [16 Page ...

Page 10

... The Latency Timing applies only at the Empty Boundary (EF = LOW). SKEW1 19. The first word is available the cycle after EF goes HIGH, always. Document #: 38-06007 Rev [18] t FRL t SKEW1 t REF t OLZ t OE (maximum When t < minimum specification, t CLK SKEW2 SKEW1 CY7C4281 CY7C4291 [19 (maximum) = either 2 FRL CLK Page SKEW1 CLK ...

Page 11

... ENS ENH WEN2 (if applicable) t FRL RCLK t SKEW1 EF REN1, REN2 LOW OE DATA IN OUTPUT REGISTER Q – Document #: 38-06007 Rev. *C [18 REF REF t A CY7C4281 CY7C4291 t DS DATA WRITE 2 t ENH t ENS t t ENH ENS [18] t FRL t t SKEW2 DATA READ REF Page ...

Page 12

... A DATA READ t CLKL t t ENS ENH t t ENS ENH Note 21 [20] t PAE , then PAE may not change state until the next RCLK. CY7C4281 CY7C4291 NO WRITE [13] t SKEW1 t t WFF WFF t ENH t ENS t A NEXT DATA READ WORDS Note 22 IN FIFO ...

Page 13

... PAF ENS ENH IN FIFO t CLKL t ENH PAE OFFSET PAE OFFSET LSB MSB , then PAF may not change state until the next WCLK. SKEW2 CY7C4281 CY7C4291 (FULL M) WORDS [25] IN FIFO [26 PAF SKEW2 ENS ENS ENH PAF OFFSET PAF OFFSET LSB MSB Page ...

Page 14

... CY7C4281-10JI 15 CY7C4281-15JC 25 CY7C4281-25JC 128K x 9 Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4291-10JC CY7C4291-10JXC CY7C4291-10JI 15 CY7C4291-15JC CY7C4291-15JXC 25 CY7C4291-25JC Document #: 38-06007 Rev CLKL t ENH t A UNKNOWN PAE OFFSET LSB Package Package Name Type J65 32-Lead Plastic Leaded Chip Carrier J65 32-Lead Plastic Leaded Chip Carrier ...

Page 15

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 32-Lead Plastic Leaded Chip Carrier J65 CY7C4281 CY7C4291 51-85002-*B Page ...

Page 16

... Document History Page Document Title: CY7C4281, CY7C4291 64K/128K X 9 Deep Sync FIFOs Document Number: 38-06007 REV. ECN NO. Issue Date ** 106468 07/12/01 *A 122259 12/26/02 *B 127854 08/22/03 *C 386004 See ECN Document #: 38-06007 Rev. *C Orig. of Change SZV Change from Spec number: 38-00587 to 38-06007 RBI ...

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