MT9042CP Zarlink Semiconductor, MT9042CP Datasheet
MT9042CP
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MT9042CP Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. Multitrunk System Synchronizer MT9042CP MT9042CPR MT9042CP1 MT9042CPR1 28 Pin PLCC* Description The MT9042C contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links ...
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... C16o are at logic high; C16o is at logic low." Change Example time increases from to 0.9 to1.45 seconds. Changed Minimum Schmitt high level input voltage V from 2.3 volts to 3.4 volts. SIH 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Clock 2.048 MHz (CMOS Output). This output is used for ST-BUS operation at 2.048 Mb/s. MT9042C VDD 5 25 RSEL 24 MS1 OSCo 6 OSCi 7 23 MS2 22 F16o LOS1 LOS2 F0o 10 20 F8o GTo GTi 11 19 C1. Figure 2 - Pin Connections Description (see notes nominal Zarlink Semiconductor Inc. Data Sheet ...
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... See AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels for dynamic logic threshold values. 5. Unless otherwise stated, all unused inputs should be connected to logic high or logic low and all unused outputs should be left open circuit. MT9042C Description (see notes The logic level at this input is gated in by the rising 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Programmable Delay Circuit (See Figure 3). The new virtual reference signal is now at the same phase position as the previous reference signal would have been if the reference switch not taken place. The State Machine then returns the device to Normal Mode. MT9042C FS1 Input Frequency 0 Reserved 1 8kHz 0 1.544MHz 1 2.048MHz Table 1 - Input Frequency Selection 5 Zarlink Semiconductor Inc. Data Sheet ...
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... ETS 300 011 and AT&T TR62411 are met. MT9042C TRST Resets Delay Control Control Signal Circuit Delay Value Compare Circuit TIE Corrector Feedback Enable Signal from from Frequency State Machine Select MUX Figure 3 - TIE Corrector Circuit 6 Zarlink Semiconductor Inc. Data Sheet Virtual Reference to DPLL ...
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... Input Impairment Monitor State Select from State Machine Figure 4 - DPLL Block Diagram C1.5o T1 Divider C3o 12MHz Tapped Delay Line C2o Tapped E1 Divider Delay C4o Line C8o 16MHz C16o F0o F8o F16o 7 Zarlink Semiconductor Inc. Data Sheet DPLL Reference to Output Interface Circuit ...
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... All state machine changes occur synchronously on the rising edge of F8o. See the Controls and Modes of Operation section for full details on Automatic Control and Manual Control. MT9042C To To TIE To DPLL Reference Corrector State Select MUX Enable Select Automatic/Manual Control and From State Machine Guard Time MS1 MS2 8 Zarlink Semiconductor Inc. Data Sheet To Circuit ...
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... MT9042C RSEL Input Reference 0 PRI 1 SEC 0 State Machine Control 1 Reserved Table 2 - Input Reference Selection MS1 Control Mode 0 MANUAL NORMAL 1 MANUAL HOLDOVER 0 MANUAL FREERUN 1 AUTO State Machine Control Table 3 - Operating Modes and States 9 Zarlink Semiconductor Inc. Data Sheet ...
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... Which is much greater than the ±0.05 ppm of the MT9042C. The other factor affecting accuracy is large jitter on the reference input prior ( ms) to the mode switch. For instance, jitter of 7 700 Hz may reduce the Holdover Mode accuracy from 0.05 ppm to 0.10 ppm. MT9042C 10 Zarlink Semiconductor Inc. Data Sheet ...
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... Refer to Manual Control State Diagram for state changes to and from Auto-Holdover State MT9042C Normal Normal Freerun (PRI) (SEC MTIE MTIE S2 S2 MTIE / S1H / S2H - S0 Table 4 - Manual Control State Table 11 Zarlink Semiconductor Inc. Data Sheet State Holdover Holdover (PRI) (SEC) S2 S1H S2H S1 S1 MTIE S1 MTIE S1 MTIE - S2 MTIE S2 MTIE / - / S2H / - S0 S0 ...
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... Phase Continuity Maintained (without TIE Corrector Circuit) Phase Continuity Maintained (with TIE Corrector Circuit) Normal Normal Freerun (PRI) (SEC MTIE MTIE S1 S1H S2 S2 MTIE - S1H S2H 12 Zarlink Semiconductor Inc. Data Sheet S2 {A} Normal Secondary (001) State Holdover Holdover (PRI) (SEC) S2 S1H S2H MTIE S1 MTIE S1 MTIE - - S2 MTIE ...
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... S1H Holdover Holdover Primary Secondary (11X) Phase Re-Alignment Phase Continuity Maintained (without TIE Corrector Circuit) Phase Continuity Maintained (with TIE Corrector Circuit) 13 Zarlink Semiconductor Inc. Data Sheet (01X) (01X) (01X) S2A S2 {A} Normal Secondary (11X) (01X) S2H ...
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... For the MT9042C, the Freerun accuracy is equal to the Master Clock (OSCi) accuracy. MT9042C – A ------ 20 ×10 = InputT1 – 18 -------- - 20 × 2.5UI 1UIT1 × --------------------- - = OutputT1 ( ) 1UIE1 ( ) 644ns × ------------------- = OutputT1 = 3.3UI 488ns 14 Zarlink Semiconductor Inc. Data Sheet ...
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... This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal and output signal are not changing in phase with respect to each other (not including jitter). MT9042C TIEmax TIEmin – 15 Zarlink Semiconductor Inc. Data Sheet ...
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... For example, if the master timing source is ±100 ppm, then the capture range will be ±130 ppm. Clock Oscillator - when selecting a Clock Oscillator, numerous parameters must be considered. This includes absolute frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle. See AC Electrical Characteristics. MT9042C 16 Zarlink Semiconductor Inc. Data Sheet ...
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... MT9042C +5V OSCi +5V 20MHz OUT GND 0.1uF OSCo No Connection Figure 9 - Clock Oscillator Circuit OSCi 20 MHz 1 MΩ 3-50 pF OSCo 100 Ω Figure 10 - Crystal Oscillator Circuit 17 Zarlink Semiconductor Inc. Data Sheet ...
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... MT9042C Ω ) GTo R + 150 kΩ GTi kΩ × ---------------------------------------- guard time = RC ln SIH – typ ≈ × guard time RC 0.97 example ≈ × × guard time 150k 10u 0.97 = 1.45s 18 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 13 shows a typical timing example of an unsymmetrical Guard Time Circuit with the MT9042C in Automatic Control. MT9042C GOOD BAD GOOD PRI PRI PRI NORMAL HOLDOVER GTo R C 150 kΩ kΩ GTi kΩ 19 Zarlink Semiconductor Inc. Data Sheet GOOD BAD SEC PRI NORMAL NORMAL + C ...
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... MT9042C from Normal Mode to Holdover Mode • 200 ns is the maximum phase continuity of the MT9042C from Holdover Mode to Normal Mode (with or without TIE Corrector Circuit) MT9042C × Phase hold = 0.05ppm 2s = 100ns Phase state = 50ns + 200ns = 250ns × Phase 250ns + 100ns = 20 Zarlink Semiconductor Inc. Data Sheet 3.5us ...
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... MT9042C F0o PRI C4o SEC C2o LOS1 LOS2 + 5 V FS1 MS1 FS2 MS2 GTo RSEL GTi TRST 1 kΩ OSCi RST + kΩ Zarlink Semiconductor Inc. Data Sheet + 5 V 150 kΩ 1 kΩ 1 kΩ CLOCK Out ± 20 MHz 32 ppm is for protection P ...
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... C4i Figure 16 - Dual E1 Reference Sources with MT9042C in 8 kHz Manual Control MT9042C + kΩ kΩ MT9042C PRI SEC LOS1 LOS2 MS1 MS2 RSEL TRST RST CONTROLLER 22 Zarlink Semiconductor Inc. Data Sheet F0o C4o C1. FS1 FS2 GTi CLOCK OSCi Out ± 20 MHz 32 ppm ...
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... For complete Manual Control state machine details, refer to Table 4 for the State Table, and Figure 7 for the State Diagram. MT9042C C1 0 MT9042C 0.1 uF Figure 17 - Power Supply Decoupling 23 Zarlink Semiconductor Inc. Data Sheet ...
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... IL V 0.7V CIH DD V 0.3V DD CIL V 3.4 SIH V 0.8 SIL V 0.4 HYS I -10 +10 uµ 2. 0. Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0.3 7.0 V -0 °C -55 125 900 mW ) unless otherwise stated Max. Units 5 °C Conditions/Notes mA Outputs unloaded mA Outputs unloaded ...
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... Sym. Schmitt Zarlink Semiconductor Inc. Data Sheet Max. Units Conditions/Notes† +0 ppm 5-8 +32 ppm 5-8 +100 ppm 5-8 ppm 1,2,4,6-8,40 ppm 1,2,4,6-8,40 ppm 1,2,4,6-8,40 +230 ppm 1-3,6-8 +198 ...
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... R8D t R15D t R2D t F0D t F16S t F16H t C15D t C3D t C2D t C4D t C8D t C16D t C15W t C3W t C2W t C4W t C8W t C16WL t F0WL t F8WH t F16WL t ORF Zarlink Semiconductor Inc. Data Sheet ORF Min. Max. Units 100 - 337 363 ns 222 238 ns 110 134 -51 -37 ns -51 - -13 ...
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... F0o F16o t C16WL C16o t C8W C8o t C4W C4o C2o C3o C1.5o MT9042C R15D R2D F0WL t F16S t C8W t C4W t C2W t t C3W C3W t C15W Figure 20 - Output Timing 1 27 Zarlink Semiconductor Inc. Data Sheet t R8D F8WH F0D F16WL F16H t C16D C8D C4D C2D ...
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... Sym. Min. Max. 0.015 0.010 0.010 0.005 Sym. Min. Max. 0.015 0.010 0.010 0.005 28 Zarlink Semiconductor Inc. Data Sheet Units Conditions/Notes† UIpp 1-14,21-24,28 UIpp 1-14,21-24,28 UIpp 1-14,21-24,28 UIpp 1-14,21-24,29 UIpp 1-14,21-24,30 UIpp 1-14,21-24,31 UIpp ...
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... Jitter attenuation for 100 kHz@0.3 UIpp input † See "Notes" following AC Electrical Characteristics tables. MT9042C Sym. Min. Max. Units Sym. Min. Max. Units Zarlink Semiconductor Inc. Data Sheet Conditions/Notes† 1-3,6,9-14,21-22,24,28,35 1-3,6,9-14,21-22,24,28,35 1-3,6,9-14,21-22,24,28,35 1-3,6,9-14,21-22,24,28,35 1-3,6,9-14,21-22,24,28,35 1-3,6,9-14,21-22,24,28,35 Conditions/Notes† 1-3,7,9-14,21-22,24,29,35 1-3,7,9-14,21-22,24,29,35 1-3,7,9-14,21-22,24,29,35 1-3,7,9-14,21-22,24,29,35 1-3,7,9-14,21-22,24,29,35 1-3,7,9-14,21-22,24,29,35 1-3,7,9-14,21-22,24,29,35 ...
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... Units 0.80 UIpp 0.70 UIpp 0.60 UIpp 0.20 UIpp 0.15 UIpp 0.08 UIpp 0.02 UIpp 0.01 UIpp 30 Zarlink Semiconductor Inc. Data Sheet Conditions/Notes† 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 Conditions/Notes† 1-3,6,9-14,21-22,24-26,28 ...
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... Max. Units 150 UIpp 140 UIpp 130 UIpp 50 UIpp 40 UIpp 20 UIpp 5 UIpp 1 UIpp 1 UIpp 31 Zarlink Semiconductor Inc. Data Sheet Conditions/Notes† 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 Conditions/Notes† 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 ...
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... After a RST or TRST. 39. Master clock duty cycle 40% to 60%. 40. Prior to Holdover Mode, device was in Normal Mode and phase locked. MT9042C Sym. Min. Max. Units -0 +0 -32 +32 -100 +100 Zarlink Semiconductor Inc. Data Sheet Conditions/Notes† ppm 15,18 ppm 16,19 ppm 17, ...
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