MT8979AP Zarlink Semiconductor, MT8979AP Datasheet
MT8979AP
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MT8979AP Summary of contents
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... Interface XCtl Control Logic XSt ISO-CMOS ST-BUS FAMILY CEPT PCM 30/CRC-4 Framer & Interface MT8979AE MT8979AP Description The MT8979 is a single chip CEPT digital trunk transceiver that meets the requirements of CCITT Recommendation equipment. The MT8979 is fabricated in Zarlink’s low power ISO-CMOS technology ...
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MT8979 ISO-CMOS 1 TxA 28 2 TxB 27 3 DSTo RxA 24 6 RxB 23 7 RxD CSTi1 ADI 12 17 CSTi0 13 E8Ko ...
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Pin Description (Continued) Pin # Name DIP PLCC 13 20 E8Ko Extracted 8 kHz Clock (Output kHz output generated by dividing the extracted 2048 kHz clock by 256 and aligning it with the received CEPT frame. The ...
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MT8979 ISO-CMOS Functional Description The MT8979 is a CEPT trunk digital link interface conforming to CCITT Recommendation G.704 for PCM 30 and I.431 for ISDN. It includes features such as: insertion and detection of synchronization patterns, optional cyclical redundancy check ...
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CRC multiframe alignment signal and two spare bits (in frames 13 and 15), which are used for CRC error performance reporting (refer to Figure 6). ...
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MT8979 ISO-CMOS Control Input 0 (CSTi0) All the necessary control and signalling information is input through the two control streams. Control ST-BUS input number 0 (CSTi0) contains the control information that is associated with each information channel. Each control channel ...
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CHANNEL CHANNEL 0 31 Most Significant Bit (First) the ERR bit can be used to evaluate the bit error rate of the line according Recommendation G.732 (see section on Frame Alignment Error Counter). Channel 19 contains the Phase Status Word ...
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MT8979 ISO-CMOS 4-94 ...
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Frame Alignment Error Counter The MT8979 provides an indication of the bit error rate found on the link as required by CCITT Recommendation G.703. The ERR bit (Bit 5 of MSW1) is used to count the number of errors found ...
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MT8979 ISO-CMOS The multiframe synchronization dependent upon the state of frame alignment framer. The multiframe framer will not initiate a search for multiframe synchronization until frame sync is achieved. Multiframe synchronization declared on the first occurrence of four consecutive zeros ...
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BIT NAME 7 DATA Data Channel: If ‘1‘, then the controlled timeslot on the CEPT 2048 kbit/s link is treated as a data channel; i.e., no ADI encoding or decoding is performed on transmission or reception, and digital attenuation is ...
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MT8979 ISO-CMOS BIT NAME 7 (N/A) Keep at ‘1‘ for normal operation. 6 (N/A) Keep at ‘0‘ for normal operation. 5 CCS Common Channel Signalling then the MT8979 operates in its common channel signalling mode. Channel 16 on ...
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BIT NAME 7, A(N), Transmit Signalling Bits for Channel N: These bits are transmitted on the CEPT 2048 6, B(N), kbit/s link in bit positions timeslot 16 in frame N, and are the ...
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MT8979 ISO-CMOS BIT NAME 7 IU1 International Use 1: When the CRC is disabled and SiMUX bit in MCW3 is disabled, this bit is transmitted on the CEPT 2048 kbit/s link in bit position 1 of timeslot 0 of non-frame-alignment ...
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BIT NAME 7-4 MA1-4 Receive Multiframe Alignment Bits These are the bits which are received from the CEPT 2048 kbit/s link in bit positions timeslot 16 of frame 0 of the multiframe. They ...
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MT8979 ISO-CMOS BIT NAME 7 IU1 International Use 1: This is the bit which is received from the CEPT 2048 kbit/s link in bit position 1 of timeslot 0 of non-frame-alignment frames . It is reserved for the CRC framing ...
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BIT NAME CERC CRC Error Counter: This byte is the CRC error counter. The counter will wrap around once it reaches FF count. If maintenance option is activated, the counter will reset after a one second interval. ...
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MT8979 ISO-CMOS Receiver The receive line interface circuit shown in Figure 15 will decode the HDB3 line signals into two split phase unipolar steering signals. are used to drive the violation detectors RxA and RxB as well as being NAND‘ed ...
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Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage at Digital Inputs 3 Current at Digital Inputs 4 Voltage at Digital Outputs 5 Current at Digital Outputs 6 Storage Temperature 7 Package Power Dissipation * Exceeding these values may cause ...
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MT8979 ISO-CMOS AC Electrical Characteristics Characteristics 1 C2i Clock Period 2 C2i Clock Width High or Low 3 Frame Pulse Setup Time 4 Frame Pulse Hold Time 5 Frame Pulse Width 6 Serial Output Delay 7 Serial Input Setup Time ...
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AC Electrical Characteristics Characteristics 1 Receive Multiframe Output Delay 2 Transmit Multiframe Setup Time 3 Transmit Multiframe Hold Time 4 Tx Multiframe to C2 Setup Time † Characteristics are for clocked operation over the ranges of recommended operating temperature and ...
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MT8979 ISO-CMOS AC Electrical Characteristics Characteristics 1 External Control Delay 2 External Status Setup Time 3 External Status Hold Time 4 E8Ko Output Delay 5 E8Ko Output Low Width 6 E8Ko Output High Width 7 E8Ko Output Transition Time † ...
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AC Electrical Characteristics Characteristics 1 Transmit Steering Delay* 2 Transmit Steering Transition Time 3 E2i Clock Period 4 E2i Clock Width High or Low 5 Receive Data Setup Time 6 Receive Data Hold Time 7 Receive Steering Setup Time 8 ...
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MT8979 ISO-CMOS Appendix Control and Status Register Summary 7 6 UNUSED LOOP16 1 Enabled Keep Disabled Master Control Word 1 (MCW1) - CSTi0, Channel 15 UNUSED UNUSED CCS 1 Common Channel Keep at 1 Keep at 0 ...
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TFSYN MFSYN ERR Frame 1 Out of Sync 1 Out of Sync Alignment Signal Error 0 In Sync 0 In Sync Count Master Control Word 1 (MSW1) - CSTo, Channel 18 Si2 Si1 Remote SMF2 Remote SMF1 ...
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MT8979 ISO-CMOS Notes: 4-112 ...
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