HDMP-0450 Agilent Technologies, Inc., HDMP-0450 Datasheet

HDMP-0450

Manufacturer Part Number

HDMP-0450

Description

Manufacturer

Agilent Technologies, Inc.

Datasheet

1.HDMP-0450.pdf (10 pages)

Specifications of HDMP-0450

Case

QFP

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Description

The HDMP-0450 is a Quad Port

Bypass Circuit (PBC) which

provides a low-cost, low-power

physical-layer solution for Fibre

Channel Arbitrated Loop (FC-AL)

disk array configurations. By using a

PBC such as the HDMP-0450, hard

disks may be pulled out or swapped

while other disks in the array are

available to the system.

A PBC consists of multiple 2:1

multiplexers daisy chained together.

Each port has two modes of

operation: “disk in loop” and “disk

bypassed.” When the “disk in loop”

mode is selected, the loop goes into

and out of the disk drive at that

port. For example, data goes from

the HDMP-0450’s TO_NODE[n]

differential output pins to the Disk

Drive Transceiver IC’s (e.g., an

HDMP-1636A) Rx differential input

pins. Data from the Disk Drive

Transceiver IC’s Tx differential

outputs goes to the HDMP-0450’s

FM_NODE[n]

CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling

and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic

discharge (ESD).

differential input

Agilent HDMP-0450

Quad Port Bypass Circuit

for Fibre Channel Arbitrated Loops

Data Sheet

pins. Figure 2 shows connection

diagrams for disk drive array

applications. When the “disk

bypassed” mode is selected, the

disk drive is either absent or

nonfunctional and the loop

bypasses the hard disk.

The “disk bypassed” mode is

enabled by pulling the BYPASS[n]-

pin low. Leave BYPASS[n]-

floating to enable the “disk in

loop” mode. HDMP-0450s may be

cascaded with other members of

the HDMP-04XX/HDMP-05XX

family through the appropriate

FM_NODE[n]

TO_NODE[n]

accommodate any number of hard

disks (see Figure 3). The unused

cells in the HDMP-0450 may be

bypassed by using pulldown

resistors on the BYPASS[n]- pins

for these cells.

An HDMP-0450 may also be

configured as five 1:1 buffers, as

two 2:1 multiplexers, or as two

1:2 buffers.

pins to

and

Features

• Supports 1.0625 GBd Fibre Channel

• Supports 1.25 GBd Gigabit Ethernet

• Quad PBC in one package

• Signal detect on FM_NODE[0] input

• Equalizers on all inputs

• High speed LVPECL I/O

• Buffered Line Logic (BLL) outputs

• 0.5 W typical power at V

• 44 Pin, 10 mm, low-cost plastic QFP

Applications

• RAID, JBOD, BTS cabinets

• Two 2:1 muxes

• Two 1:2 buffers

• 1 => N gigabit serial buffer

• N => 1 gigabit serial mux

operation

(GE) operation

(no external bias resistors required)

package

HDMP-0450

= 3.3 V

Related parts for HDMP-0450

HDMP-0450 Summary of contents

Page 1

... FM_NODE[n] and TO_NODE[n] pins to accommodate any number of hard disks (see Figure 3). The unused cells in the HDMP-0450 may be bypassed by using pulldown resistors on the BYPASS[n]- pins for these cells. An HDMP-0450 may also be configured as five 1:1 buffers, as two 2:1 multiplexers two 1:2 buffers ...

Page 2

... Buffered Line Logic (BLL) circuit that has on-chip source termination external bias resistors are required. The BLL outputs on the HDMP-0450 are of equal strength and can drive in lengthy FR-4 PCB trace. Unused outputs should not be left unconnected. Ideally, unused ...

Page 3

... HARD DISK B HARD DISK C SERDES SERDES SERDES EQU TTL EQU TTL EQU TTL BLL BLL BLL Figure 3. Connection diagram for multiple HDMP-0450s. 3 HARD DISK C HARD DISK D SERDES TTL EQU TTL BLL BLL HARD DISK D SERDES EQU TTL EQU TTL EQU TTL ...

Page 4

I/O Type Definitions I/O Type Definition I-LVTTL LVTTL Input O-LVTTL LVTTL Output HS_OUT High Speed Output. LVPECL Compatible HS_IN High Speed Input C External Circuit Note S Power Supply or Ground Pin Definitions Pin Name Pin Pin Type Pin Description ...

Page 5

Pin Definitions, continued GND 01 S Ground: Normally 0 volts. See Figure 9 for Recommended Power Supply Filtering VCCHS[ High Speed Supply: Normally 3.3 volts. Used only for high-speed ...

Page 6

AC Electrical Specifications Symbol Parameter T Total Loop Latency from FM_NODE[0] to TO_NODE[0] LOOP_LAT T Per Cell Latency from FM_NODE[4] to TO_NODE[0] CELL_LAT t Input LVTTL Rise Time Requirement, 0 ...

Page 7

Simplified I/O Cells O_LVTTL V CC ESD PROTECTION GND Figure 5. O-LVTTL and I-LVTTL simplified circuit schematic. HS_OUT 75 ESD PROTECTION NOTE: FM_NODE[n] INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT. Figure 6. ...

Page 8

... TOP VIEW ALL DIMENSIONS ARE IN MILLIMETERS PART NUMBER HDMP-0450 TOLERANCE Figure 7. HDMP-0450 package drawing. 8 for this device is 57 C/W is measured on a standard 3x3” FR4 PCB in a still air environment Details Plastic 85% Tin, 15% Lead 200-800 micro-inches 0.33 mm max. 0.10 mm max ...

Page 9

... Pin Diagram and Recommended Supply Filtering GND FM_NODE [1]– 3 FM_NODE [1 HS[ TO_NODE [1]– 6 TO_NODE [1]+ 7 GND 8 FM_NODE [0]– 9 FM_NODE [0 GND Figure 8. HDMP-0450 package layout and marking, top view GND GND GND Figure 9. Recommended power supply filtering GND TO_NODE[4]+ 30 TO_NODE[4]– Agilent ...

Page 10

... China: 10800 650 0017 Hong Kong: (+65) 6271 2451 India, Australia, New Zealand: (+65) 6271 2394 Japan: (+81 3) 3335-8152(Domestic/Interna- tional), or 0120-61-1280(Domestic Only) Korea: (+65) 6271 2194 Malaysia, Singapore: (+65) 6271 2054 Taiwan: (+65) 6271 2654 Data subject to change. Copyright © 2002 Agilent Technologies, Inc. August 26, 2002 5988-7490EN ...

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