HDMP-0452 Agilent Technologies, Inc., HDMP-0452 Datasheet
HDMP-0452
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HDMP-0452 Summary of contents
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... Description The HDMP-0452 is a Quad Port Bypass Circuit (PBC) with a Clock and Data Recovery (CDR) circuit included. This device minimizes part count, cost and jitter accumula- tion while repeating incoming sig- nals. Port Bypass Circuits are used in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations ...
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... An HDMP-0452 may also be used as five 1:1 buffers, one with a CDR and four without. For ex- ample, an HDMP-0452 may be placed in front of a CMOS ASIC to clean the jitter of the outgoing signal (CDR path) and to better read the incoming signal (non- CDR path). In addition, the ...
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... EQU TTL EQU TTL BLL BLL Figure 1. Block diagram of HDMP-0452. Table 1. Truth Table for CDR at Entry Configuration. TO_LOOP TO_NODE[4] TO_NODE[3] FM_LOOP FM_LOOP FM_LOOP FM_NODE[1] FM_NODE[1] FM_NODE[1] FM_NODE[2] FM_NODE[2] FM_NODE[2] FM_NODE[2] FM_NODE[2] FM_NODE[2] FM_NODE[3] FM_NODE[3] FM_LOOP FM_NODE[3] FM_NODE[3] FM_NODE[1] FM_NODE[3] FM_NODE[3] FM_NODE[2] ...
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... GND nnnn-nnn = WAFER LOT – BUILD NUMBER Rz.zz = DIE REVISION S = SUPPLIER CODE YYWW = DATE CODE ( YY = YEAR WORK WEEK) COUNTRY = COUNTRY OF MANUFACTURE Figure 2. HDMP-0452 package layout and marking, top view. I/O Type Definitions I/O Type Definition I-LVTTL LVTTL Input O-LVTTL LVTTL Output ...
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... Table 3. Pin Definitions for HDMP-0452. Pin Name Pin Pin Type Pin Description TO_NODE[0]+ 24 HS_OUT Serial Data Outputs: High-speed outputs to a hard disk drive cable input. TO_NODE[0]– 25 TO_NODE[1]+ 07 TO_NODE[1]– 06 TO_NODE[2]+ 44 TO_NODE[2]– 43 TO_NODE[3]+ 38 TO_NODE[3]– 37 TO_NODE[4]+ 31 TO_NODE[4]– 30 FM_NODE[0]+ 10 HS_IN Serial Data Inputs: High-speed inputs from a hard disk drive or from a cable output. FM_NODE[0]– ...
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HARD DISK A HARD DISK B SERDES SERDES Figure 3. Connection diagram for CDR at first cell. HARD DISK A SERDES Figure 4. Connection diagram for CDR at ...
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... LVTTL Output Voltage O,LVTTL T Storage Temperature stg T Junction Temperature j HDMP-0452 Guaranteed Operating Rates + 3. 3. Serial Clock Rate FC (MBd) Min. Max. 1040 1080 HDMP-0452 CDR Reference Clock Requirements + 3. 3. Symbol Parameter f Nominal Frequency F Frequency Tolerance tol Symm Symmetry (Duty Cycle) HDMP-0452 DC Electrical Specifications + 3. 3. ...
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... HS_OUT Differential Rise Time, 20%-80% rd,HS_OUT t HS_OUT Differential Fall Time, 20%-80% fd,HS_OUT V HS_IN Input Peak-to-Peak Required Differential Voltage Range IP,HS_IN V HS_OUT Output Pk-Pk Diff. Voltage Range ( Ohm, Fig. 9) OP,HS_OUT HDMP-0452 Power Dissipation and Thermal Resistance + 3. 3. Symbol Parameter P Power Dissipation D Thermal Resistance, Junction to Case ...
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... BIAS TEE BYPASS[1:4]– REFCLK ± TO_NODE[0] 1 106.25 MHz 1/10 CH 1/2 106.25 MHz TRIGGER HP83480A DIGITAL COMMUNICATION ANALYZER DETERMINISTIC JITTER HDMP-0452 2 ± FM_NODE[0] BYPASS[0]– BIAS TEE BYPASS[1:4]– REFCLK ± TO_NODE[0] 1 106.25 MHz 1/10 CH 1/2 TRIGGER 1/2 53.125 MHz HP83480A ...
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O_LVTTL V CC PROTECTION GND Figure 8. O-LVTTL and I-LVTTL simplified circuit schematic. HS_OUT 75 ESD PROTECTION NOTE: FM_NODE[n] INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT. Figure 9. HS_OUT and HS_IN simplified ...
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... Lead Finish Material Lead Finish Thickness Lead Skew Lead Coplanarity (Seating Plane) Mechanical Dimensions PIN #1 HDMP-0452 TOP VIEW ALL DIMENSIONS ARE IN MILLIMETERS PART NUMBER HDMP-0452 TOLERANCE Figure 10. HDMP-0452 package drawing. 11 Details Plastic 85% Tin, 15% Lead 200-800 micro-inches 0.33 mm max. 0.10 mm max SEATING PLANE A1 ...
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... Supply Filtering GND HDMP-0452 6 7 GND GND NOTE: CAPACITORS = 0.1 µF, RESISTORS = 10 Figure 11. Recommended power supply filtering. www.semiconductor.agilent.com Data subject to change. Copyright © 2001 Agilent Technologies, Inc. September 28, 2001 5988-4333EN 33 GND GND ...