HDMP-1637A Agilent Technologies, Inc., HDMP-1637A Datasheet

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HDMP-1637A

Manufacturer Part Number
HDMP-1637A
Description
Manufacturer
Agilent Technologies, Inc.
Datasheet

Specifications of HDMP-1637A

Case
QFP
Features
• IEEE 802.3z Gigabit
• Based on X3T11 “10 Bit
• Low Power Consumption
• 10 mm 64-pin PQFP Package
• Transmitter and Receiver
• 5-Volt Tolerant I/Os
• 10 Bit Wide Parallel TTL
• Single +3.3 V Power Supply
• Differential PECL Clock
• 2 kV Human Body ESD
Applications
• 1250 MBd Gigabit
• High Speed Proprietary
• Backplane Serialization /
Description
The HDMP-1637A transceiver is a
single silicon bipolar integrated
circuit packaged in a plastic QFP
package. It provides a low-cost,
low-power physical layer solution
for 1250 MBd Gigabit Ethernet or
proprietary link interfaces. It
provides complete Serialize/
Deserialize (SerDes) for copper
Gigabit Ethernet SerDes Circuit
with Differential PECL Clock
Inputs
Ethernet Compatible,
Supports 1250 MBd Gigabit
Ethernet
Specification”
Functions Incorporated
onto a Single IC
Compatible I/Os
Inputs
Protection on all Pins
Ethernet Interface
Interface
Bus Extender
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in handling
and assembly of this component to prevent damage and/or degradation which may be induced by
electrostatic discharge (ESD).
transmission, incorporating both
the Gigabit Ethernet transmit and
receive functions into a single
device.
This chip is used to build a high
speed interface (as shown in
Figure 1) while minimizing board
space, power, and cost. It is
compatible with the IEEE 802.3z
specification.
The transmitter section accepts
10-bit wide parallel TTL data and
serializes this data into a high
speed serial data stream. The
parallel data is expected to be
“8B/10B” encoded data, or
equivalent. This parallel data is
latched into the input register of
the transmitter section on the
rising edge of the 125 MHz
reference clock (used as the
transmit byte clock).
The transmitter section’s PLL
locks to this user supplied 125
MHz byte clock. This clock is then
multiplied by 10, to generate the
1250 MHz serial signal clock used
to generate the high speed output.
The high speed outputs are
capable of interfacing directly to
copper cables for electrical
transmission or to a separate fiber
optic module for optical
transmission.
The receiver section accepts a
serial electrical data stream at
1250 MBd and recovers the
HDMP-1637A SerDes
original 10-bit wide parallel data.
The receiver PLL locks onto the
incoming serial signal and
recovers the high speed serial
clock and data. The serial data is
converted back into 10-bit parallel
data, recognizing the 8B/10B
comma character to establish byte
alignment.
The recovered parallel data is
presented to the user at TTL
compatible outputs. The receiver
section also recovers two 62.5
MHz receiver byte clocks which
are 180 degrees out of phase with
each other. The parallel data is
properly aligned with the rising
edge of alternating clocks.
For test purposes, the transceiver
provides for on-chip local loop-
back functionality controlled
through an external input pin.
Additionally, the byte
synchronization feature may be
disabled. This may be useful in
proprietary applications which use
alternative methods to align the
parallel data.

Related parts for HDMP-1637A

HDMP-1637A Summary of contents

Page 1

... Ethernet Interface • High Speed Proprietary Interface • Backplane Serialization / Bus Extender Description The HDMP-1637A transceiver is a single silicon bipolar integrated circuit packaged in a plastic QFP package. It provides a low-cost, low-power physical layer solution for 1250 MBd Gigabit Ethernet or proprietary link interfaces. It ...

Page 2

... PROTOCOL DEVICE RBC0 RBC1 BYTSYNC ± REFCLK ENBYTSYNC Figure 1. Typical Application using the HDMP-1637A. DATA BYTE FRAME TX[0-9] MUX TX TXCAP0 PLL/CLOCK TXCAP1 GENERATOR ± REFCLK RXCAP0 RXCAP1 RBC0 RBC1 FRAME DATA BYTE DEMUX RX[0-9] AND BYTE SYNC BYTSYNC ENBYTSYNC Figure 2. HDMP-1637A Transceiver Block Diagram. ...

Page 3

... Gigabit Ethernet specification, which uses an 8B/10B encoding scheme with special reserve characters for link management purposes. In order to accomplish this task, the HDMP-1637A incorporates the following: • TTL Parallel I/Os • High Speed Phase Locked Loops • Parallel to Serial Converter • ...

Page 4

FRAME DEMUX AND BYTE SYNC The FRAME DEMUX AND BYTE SYNC block is responsible for restoring the 10-bit parallel data from the high speed serial bit stream. This block is also responsible for recognizing the comma character (or a K28.5 ...

Page 5

... HDMP-1637A (Transmitter Section) Timing Characteristics + 3. 3. Symbol Parameter t Setup Time setup t Hold Time hold [1] t_txlat Transmitter Latency Note: 1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by the rising edge of the first bit transmitted) ...

Page 6

... HDMP-1637A (Receiver Section) Timing Characteristics + 3. 3. Symbol f_lock Frequency Lock at Powerup [1,2] b_sync Bit Sync Time t Time Data Valid Before Rising Edge of RBC valid_before t Time Data Valid After Rising Edge of RBC valid_after t RBC Duty Cycle duty A-B [4] t Rising Edge Time Difference between ...

Page 7

... Symbol Parameter f Nominal Frequency (for Gigabit Ethernet Compliance) F Frequency Tolerance tol Symm Symmetry (Duty Cycle) HDMP-1637A (TRx) DC Electrical Specifications + 3. 3. Symbol V TTL Input High Voltage Level, Guaranteed High Signal IH,TTL for All Inputs V TTL Input Low Voltage Level, Guaranteed Low Signal for ...

Page 8

... HDMP-1637A (TRx) PECL DC Electrical Specifications for REFCLK + 3. 3. Symbol Parameter V PECL Input High Voltage Level IH,PECL V PECL Input Low Voltage Level IL,PECL HDMP-1637A (TRx) AC Electrical Specifications + 3. 3. Symbol t +REFCLK/-REFCLK Rise Time, 20% to 80% r,REFCLK t +REFCLK/-REFCLK Fall Time, 80% to 20% f,REFCLK t Output TTL Rise Time, 0.8 to 2.0 volts, 10pF Load ...

Page 9

... B. BLOCK DIAGRAM OF DJ MEASUREMENT METHOD Parameter and subtracting the power dissipated outside the chip at the high speed bias resistors. resistors and receiver TTL outputs driving 10 pF loads. for these devices is 56.1 C/W for the HDMP-1637A where T is the case temperature measured on the top center of the package ...

Page 10

... O-TTL Output TTL HS_OUT High Speed Output, ECL Compatible HS_IN High Speed Input C External Circuit Node S Power Supply or Ground PECL Positive ECL HDMP-1637A (TRx) Pin Input Capacitance Symbol C Input Capacitance on TTL Input Pins INPUT O_TTL V _TTL CC ESD PROTECTION GND_TTL Figure 9. O-TTL and I-TTL Simplified Circuit Schematic. ...

Page 11

... TO CONFORM WITH THE X3T11 "10-BIT SPECIFICATION," AND TO HELP DISSIPATE HEAT. *GND: THIS PIN IS BONDED TO AN ISOLATED PAD AND HAS NO FUNCTIONALITY. HOWEVER RECOMMENDED THAT THIS PIN BE CONNECTED TO GND IN ORDER TO CONFORM WITH THE X3T11 "10-BIT SPECIFICATION," AND TO HELP DISSIPATE HEAT. Figure 11. HDMP-1637A (TRx) Package Layout and Marking, Top View ...

Page 12

TRx I/O Definition Name Pin Type BYTSYNC 47 O-TTL Byte Sync Output: An active high output. Used to indicate detection of a comma character (0011111XXX only active when ENBYTSYNC is enabled. -DIN 52 HS_IN Serial Data Inputs: High ...

Page 13

TRx I/O Definition (cont’d.) Name Pin Type RX[0] 45 O-TTL Data Outputs: One 10 bit data byte. RX[0] is the first bit received. RX[1] 44 RX[0] is the least significant bit. When there is a loss of input signal at ...

Page 14

... SHOULD BE FROM A LOW NOISE CC Transceiver Power Supply Bypass and Loop Filter Capacitors Bypass capacitors should be used and placed as close as possible to the appropriate power supply pins of the HDMP-1637A as shown on the schematic of Figure 12. All bypass chip capacitors are 0.1 F. The V _RXA and V _TXA pins are CC ...

Page 15

... Lead Finish Thickness Lead Coplanarity Mechanical Dimensions PIN # HDMP-1637A TOP VIEW ALL DIMENSIONS ARE IN MILLIMETERS. PART NUMBER A1 A2 HDMP-1637A 10.00 13.20 TOLERANCE ± 0.10 ± 0.25 ± 0.05 BASIC + 0.15/ Figure 13. Mechanical Dimensions of HDMP-1637A. Details Plastic 85% Tin, 15% Lead 300-800 m 0.08 mm max 0.22 0.50 ...

Page 16

... Data subject to change. Copyright © 1999 Agilent Technologies, Inc. 5968-5119E (11/99) ...

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