HDMP-1637A Agilent Technologies, Inc., HDMP-1637A Datasheet
HDMP-1637A
Specifications of HDMP-1637A
Related parts for HDMP-1637A
HDMP-1637A Summary of contents
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... Ethernet Interface • High Speed Proprietary Interface • Backplane Serialization / Bus Extender Description The HDMP-1637A transceiver is a single silicon bipolar integrated circuit packaged in a plastic QFP package. It provides a low-cost, low-power physical layer solution for 1250 MBd Gigabit Ethernet or proprietary link interfaces. It ...
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... PROTOCOL DEVICE RBC0 RBC1 BYTSYNC ± REFCLK ENBYTSYNC Figure 1. Typical Application using the HDMP-1637A. DATA BYTE FRAME TX[0-9] MUX TX TXCAP0 PLL/CLOCK TXCAP1 GENERATOR ± REFCLK RXCAP0 RXCAP1 RBC0 RBC1 FRAME DATA BYTE DEMUX RX[0-9] AND BYTE SYNC BYTSYNC ENBYTSYNC Figure 2. HDMP-1637A Transceiver Block Diagram. ...
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... Gigabit Ethernet specification, which uses an 8B/10B encoding scheme with special reserve characters for link management purposes. In order to accomplish this task, the HDMP-1637A incorporates the following: • TTL Parallel I/Os • High Speed Phase Locked Loops • Parallel to Serial Converter • ...
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FRAME DEMUX AND BYTE SYNC The FRAME DEMUX AND BYTE SYNC block is responsible for restoring the 10-bit parallel data from the high speed serial bit stream. This block is also responsible for recognizing the comma character (or a K28.5 ...
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... HDMP-1637A (Transmitter Section) Timing Characteristics + 3. 3. Symbol Parameter t Setup Time setup t Hold Time hold [1] t_txlat Transmitter Latency Note: 1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by the rising edge of the first bit transmitted) ...
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... HDMP-1637A (Receiver Section) Timing Characteristics + 3. 3. Symbol f_lock Frequency Lock at Powerup [1,2] b_sync Bit Sync Time t Time Data Valid Before Rising Edge of RBC valid_before t Time Data Valid After Rising Edge of RBC valid_after t RBC Duty Cycle duty A-B [4] t Rising Edge Time Difference between ...
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... Symbol Parameter f Nominal Frequency (for Gigabit Ethernet Compliance) F Frequency Tolerance tol Symm Symmetry (Duty Cycle) HDMP-1637A (TRx) DC Electrical Specifications + 3. 3. Symbol V TTL Input High Voltage Level, Guaranteed High Signal IH,TTL for All Inputs V TTL Input Low Voltage Level, Guaranteed Low Signal for ...
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... HDMP-1637A (TRx) PECL DC Electrical Specifications for REFCLK + 3. 3. Symbol Parameter V PECL Input High Voltage Level IH,PECL V PECL Input Low Voltage Level IL,PECL HDMP-1637A (TRx) AC Electrical Specifications + 3. 3. Symbol t +REFCLK/-REFCLK Rise Time, 20% to 80% r,REFCLK t +REFCLK/-REFCLK Fall Time, 80% to 20% f,REFCLK t Output TTL Rise Time, 0.8 to 2.0 volts, 10pF Load ...
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... B. BLOCK DIAGRAM OF DJ MEASUREMENT METHOD Parameter and subtracting the power dissipated outside the chip at the high speed bias resistors. resistors and receiver TTL outputs driving 10 pF loads. for these devices is 56.1 C/W for the HDMP-1637A where T is the case temperature measured on the top center of the package ...
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... O-TTL Output TTL HS_OUT High Speed Output, ECL Compatible HS_IN High Speed Input C External Circuit Node S Power Supply or Ground PECL Positive ECL HDMP-1637A (TRx) Pin Input Capacitance Symbol C Input Capacitance on TTL Input Pins INPUT O_TTL V _TTL CC ESD PROTECTION GND_TTL Figure 9. O-TTL and I-TTL Simplified Circuit Schematic. ...
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... TO CONFORM WITH THE X3T11 "10-BIT SPECIFICATION," AND TO HELP DISSIPATE HEAT. *GND: THIS PIN IS BONDED TO AN ISOLATED PAD AND HAS NO FUNCTIONALITY. HOWEVER RECOMMENDED THAT THIS PIN BE CONNECTED TO GND IN ORDER TO CONFORM WITH THE X3T11 "10-BIT SPECIFICATION," AND TO HELP DISSIPATE HEAT. Figure 11. HDMP-1637A (TRx) Package Layout and Marking, Top View ...
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TRx I/O Definition Name Pin Type BYTSYNC 47 O-TTL Byte Sync Output: An active high output. Used to indicate detection of a comma character (0011111XXX only active when ENBYTSYNC is enabled. -DIN 52 HS_IN Serial Data Inputs: High ...
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TRx I/O Definition (cont’d.) Name Pin Type RX[0] 45 O-TTL Data Outputs: One 10 bit data byte. RX[0] is the first bit received. RX[1] 44 RX[0] is the least significant bit. When there is a loss of input signal at ...
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... SHOULD BE FROM A LOW NOISE CC Transceiver Power Supply Bypass and Loop Filter Capacitors Bypass capacitors should be used and placed as close as possible to the appropriate power supply pins of the HDMP-1637A as shown on the schematic of Figure 12. All bypass chip capacitors are 0.1 F. The V _RXA and V _TXA pins are CC ...
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... Lead Finish Thickness Lead Coplanarity Mechanical Dimensions PIN # HDMP-1637A TOP VIEW ALL DIMENSIONS ARE IN MILLIMETERS. PART NUMBER A1 A2 HDMP-1637A 10.00 13.20 TOLERANCE ± 0.10 ± 0.25 ± 0.05 BASIC + 0.15/ Figure 13. Mechanical Dimensions of HDMP-1637A. Details Plastic 85% Tin, 15% Lead 300-800 m 0.08 mm max 0.22 0.50 ...
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... Data subject to change. Copyright © 1999 Agilent Technologies, Inc. 5968-5119E (11/99) ...