HDMP-2630B Agilent Technologies, Inc., HDMP-2630B Datasheet
HDMP-2630B
Specifications of HDMP-2630B
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HDMP-2630B Summary of contents
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... MHz clock internal to the sender. New data are emitted on both edges of TBC; this is called Double Data Rate (DDR). The HDMP-2630B/ 2631B find a sampling window between the two edges of TBC to latch TX[0:9] data into the input register of the transmitter section when TX_RATE =1 ...
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... Other encoding schemes will also work as long as they provide DC bal- ance and a sufficient number of transitions. The HDMP-2630B/ 2631B incorporate the following: • SSTL_2 or SSTL_3 Parallel I/O • High Speed Phase Locked Loops • Parallel to Serial Converter • ...
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... ASIC REFCLK[0:1] Figure 1. Typical application using HDMP-2630B/2631B. TX[0:9] TBC TX PLL TXCAP0 CLOCK TXCAP1 GENERATOR RXCAP0 RXCAP1 REFCLK[0:1] TX_RATE RX_RATE RBC[0:1] RX[0:9] BYTE SYNC COM_DET Figure 2. Block diagram of HDMP-2630B/2631B. 3 HDMP-2630B/2631B TRANSMITTER SECTION TX_RATE TBC TX[0:9] PLL RBC[0:1] PLL RX[0:9] COM_DET RX_RATE REF_RATE ...
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TX PLL/CLOCK GENERATOR The Transmitter Phase Locked Loop and Clock Generator block is responsible for generating all internal clocks needed by the transmitter section to perform its functions. These clocks are based on the supplied transmit byte clock (TBC). Incoming ...
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... PCB using a resistor divider from VDDQ or V while ignoring the CC VREFR output of the HDMP- 2630B. The HDMP-2630B ex- pects SSTL_2 compatible signals at the TX[0:9] and TBC pins. These pins are unterminated per section 4.1 of the SSTL_2 stan- dard (Figure 11) ...
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... HDMP-2630B/2631B Transmitter Section Timing Characteristics 3. 3. Symbol Parameter t TX[0:9] Input Data and TBC Clock Transition Range (TX_RATE = 1) ps TXCT t TX[0:9] Input Data and TBC Clock Valid Time (TX_RATE = 1) TXCV t TX[0:9] Setup Time to Falling Edge of TBC (TX_RATE = 0) TXSETUP t TX[0:9] Hold Time from Falling Edge of TBC (TX_RATE = 0) ...
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... SO± TX[0..9] 10-BIT CHAR B TBC Figure 4. Transmitter latency. TX[0] is first bit HDMP-2630B/2631B Receiver Section Timing Characteristics 3. 3. Symbol Parameter f_lock Frequency Lock at Powerup with REFCLK Active [1,2] B_sync Bit Sync Time [3] t_rxlat Receiver Latency Notes: 1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3. ...
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... Table 1. HDMP-2630B/2631B RX, RBC[0:1] Timing Dependence on RX_RATE and RBC_SYNC. Input Settings Resulting Behaviors Case RX_RATE RBC_SYNC SI Rate (GBd) RBC Rate (MHz) Timing Diagrams for RBC0, RBC1, RX[0: 1.0625 1.0625 2.125 2.125 DELAY = 0.5 - 2.0 ns SSTL OUTPUT DRIVER Figure 5. Test conditions for SSTL_2 and SSTL_3 output drivers. ...
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RBC0 RBC1 RXS RX[0:9] Figure 5a. Receiver section timing – case A. Case A of Table 1. (RX_RATE = 0, RBC_SYNC = 3. 3. ...
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... RX[0:9] Setup Time to RBC1 or RBC0 (Data Valid Before), HDMP-2630B RXS RX[0:9] Setup Time to RBC1 or RBC0 (Data Valid Before), HDMP-2631B t RX[0:9] Hold Time from RBC1 or RBC0 (Data Valid After), HDMP-2630B RXH RX[0:9] Hold Time from RBC1 or RBC0 (Data Valid After), HDMP-2631B t RBC1 Rising Edge to RBC0 Rising Edge Skew ...
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RBC0 RBC1 RX[0:9] Figure 5d. Receiver section timing – case D. Case D of Table 1. (RX_RATE = 1, RBC_SYNC = 3. 3. ...
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... HDMP-2630B/2631B LVPECL DC Electrical Specifications for REFCLK[ Symbol Parameter V LVPECL Input High Voltage Level IH,PECL V LVPECL Input Low Voltage Level IL,PECL HDMP-2630B/2631B LVTTL DC Electrical Specifications for REFCLK Symbol Parameter V LVTTL Input High Voltage Level IH,LVTTL V LVTTL Input Low Voltage Level IL,LVTTL 12 voltage of 4 ...
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... SSTL_2 I/O Parameters HDMP-2630B Recommended DC Operating Conditions and DC Electrical Characteristics 3. 3.45 V, VDDQ = 2. 2.70 V. VDDQ is the FC-1/MAC device I/O supply voltage SSTL-2 inputs can receive LVTTL signals successfully. SSTL-2 outputs do not output LVTTL compliant levels. Symbol Parameter VREFT SSTL_2 Input Reference Voltage ...
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... HDMP-2630B/2631B Transmitter Section Output Jitter Characteristics 3. 3. Symbol Parameter [1] RJ Random Jitter [2] DJ Deterministic Jitter at SO (peak-to-peak), K28.5+/K28.5– Pattern DJ Deterministic Jitter at SO (peak-to-peak), CRPAT Notes: 1. Defined by Fibre Channel Specification X3.230-1994 FC-PH, Annex A, Section A.4.4 (oscilloscope method) and tested using the setup shown in Figure 8b ...
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... N/C CLOCK CLOCK OUT MODULATION IN 2.125 GHz Tx[0:9] HDMP-2630B TBC HDMP-2631B 2.125 GBd SERDES REFCLK 106.25 MHz for these devices is 38 C/W for the HDMP-2630B and HDMP-2631B 83480A SCOPE SO ± 10 BITS HP 83480A SCOPE STATIC K28.7 0011111000 SO ± Units Typ. C/W 9.3 ...
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... HS_OUT Zo Zo ESD PROTECTION NOTE: HS_IN INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT MAY ALSO BE USED. Figure 10. HS_OUT and HS_IN simplified circuit schematic for HDMP-2630B/1B. 16 (SO+) – (SO–) STEADY-STATE OUTPUT LEVEL 1.11 V STEADY-STATE OUTPUT LEVEL 820 mV 570 mV ...
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... THE CONFIGURATION ABOVE. VREFR SHOULD BE BYPASSED WITH 0.1 µF IN THIS CASE. IF USED SHOULD BE 500-1000 . 1% RESISTORS SHOULD BE USED FOR R1 AND R2. WHEN USING THE CONFIGURATION ABOVE, VREFT TO THE MAC DEVICE SHOULD BE SET TO 1.25 V NOMINAL (HDMP-2630B) AND 1.5 V NOMINAL (HDMP-2631B). USING THESE VALUES CENTERS VREFR RELATIVE TO THE RX[0:9] OUTPUT SWINGS PROVIDED BY THE HDMP-2630B AND HDMP-2631B ...
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... TX_RATE 14 I-SSTL2 Transmit Rate Set: If set to low, the HDMP-2630B/2631B read TX[0:9] data on the falling edge of TBC and serializes it. This corresponds to a 1.0625 GBd serial stream. If set to high, the HDMP-2630B/2631B read TX[0:9] data between both edges of TBC and serializes it ...
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... Table 2. Pin Definitions for HDMP-2630B/2631B, continued Name Pin Type Signal TX[0] 02 I-SSTL2 Data Inputs: One 10-bit, encoded character to the SO serial outputs. TX[0] is the first TX[1] 03 bit transmitted. TX[0] is the least significant bit. TX[2] 04 TX[3] 06 TX[4] 07 TX[5] 08 TX[6] 09 TX[7] 11 TX[8] 12 TX[9] 13 RX[0] ...
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... Table 2. Pin Definitions for HDMP-2630B/2631B, continued Name Pin Type Signal GND_TXA 15 S Analog Ground: Normally 0 volts. Used to provide a clean ground plane for the PLL and high-speed analog cells. GND_RXA 51 S Analog Ground: Normally 0 volts. Used to provide a clean ground plane for the receiver PLL and high-speed analog cells ...
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... TX[6] RBC_SYNC 10 TX[ TX[8] TX[9] 13 TX_RATE 14 GND_TXA 15 TXCAP1 xxxx-x = WAFER LOT NUMBER–BUILD NUMBER Rz.zz = DIE REVISION S = SUPPLIER CODE YYWW = DATE CODE (YY = YEAR WORK WEEK) COUNTRY = COUNTRY OF MANUFACTURE Figure 13. HDMP-2630B/2631B package layout and marking, top view HDMP-2630B/2631B 41 40 xxxx-x Rz. YYWW (MARKED ON BACK OF DEVICE) ...
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... Package Information Item Package Material Lead Finish Material Lead Finish Thickness Lead Skew Lead Coplanarity (Seating Plane Method) Mechanical Dimensions of HDMP-2630B/2631B PIN # TOP VIEW DIMENSIONAL PARAMETER (MILLIMETERS) VALUE TOLERANCE 22 Details Metric Metal QFP 85% Tin, 15% Lead 200-800 micro-inches 0.20 mm max. 0.08 mm max. ...
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... China: 10800 650 0017 Hong Kong: (+65) 271 2451 India, Australia, New Zealand: (+65) 271 2394 Japan: (+81 3) 3335-8152(Domestic/Interna- tional), or 0120-61-1280(Domestic Only) Korea: (+65) 271 2194 Malaysia, Singapore: (+65) 271 2054 Taiwan: (+65) 271 2654 Data subject to change. Copyright © 2002 Agilent Technologies, Inc. January 17, 2002 5988-4935EN ...