PEB24911H Infineon Technologies AG, PEB24911H Datasheet

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DFE ...

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... Edition 2001-07-16 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 7/16/01. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...

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DFE ...

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PEF 24911 Revision History: Previous Version: Page Subjects (major changes since last revision) Page 13 New function: Disable Super Frame Marker introduced on pin 16: DSFM Page 13 Refined description of pin 49: CRCON Page 13, Especially, CRCON = ’1’ ...

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Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 4.3.1 Complete Activation Initiated 4.3.2 Activation ...

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Table of Contents 6.4.2 OPMODE - Operation Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . 121 6.4.3 MFILT - M-Bit Filter ...

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List of Figures Figure 1 DFE-Q/ AFE 2nd Generation Chip Set . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 Logic ...

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List of Figures Figure 42 DFE-Q V2.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Tables Table 1 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Introduction The Quad ISDN 2B1Q Echocanceller Digital Front End (DFE-Q) is the digital part of an optimized two-chip solution featuring 4x ISDN basic rate access and IDSL access at 144 kbit/s. The PEF 24911 is designed to provide in ...

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Quad ISDN 2B1Q Echocanceller Digital Front End DFE-Q V2.1 Version 2.1 1.1 Features U-Interface • Digital part of a two-chip solution featuring full duplex data transmission and reception over two-wire metallic subscriber loops providing 4x ISDN basic rate access or ...

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Others • Software compatible to PEF 24911 V1.3 (Quad IEC DFE-Q) • Inputs and outputs 5 V TTL compatible • DOUT (open drain) accepts pull- • +3.3 V ±0.3 V Power Supply • Advanced ...

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Logic Symbol • Boundary Scan TM S TCK TDI TDO TRST SDX SDR 4 PDM0 .. 3 4 D0A, D0B, D0C, D0D 4 D3A, D3B, D3C, D3D 2 ST00, ST01 2 ST30, ST31 CRCON Figure 2 Logic Symbol Data ...

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System Integration This paragraph shows how the DFE-Q V2.1 may be integrated in systems using other Infineon ISDN devices. The PEF 24911 DFE-Q is optimized for use in the following applications: – Digital Line Cards for Central Office – ...

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Te st Unit Q-IHPC PEB 2426 Figure 4 16-Line Card Application with ELIC Figure 5 shows how an 8 channel line card application is realized by use of two AFE/ DFE-Q chip sets: One AFE-PLL ...

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Hybrid Hybrid 4x U Hybrid Hybrid Hybrid Hybrid 4x U Hybrid Hybrid Figure 5 Connecting Two AFE/DFE-Q Chip Sets The DFE-Q devices are supplied by the first AFE at pin CL15 with the synchronized 15.36 MHz clock. The IOM ...

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Hybrid Hybrid 4x U Hybrid Hybrid Hybrid Hybrid 4x U Hybrid Hybrid Hybrid Hybrid 4x U Hybrid Hybrid Figure 6 Recommended Clocking Scheme for More Than Two DFE-Q/AFE Chip Sets Data Sheet 8/ 2048kHz PTT 15.36MHz Reference Cock XIN ...

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Operational Overview The DFE-Q V2.1 operates always in LT mode. Other operating modes known from former versions of the DFE-Q are not further supported. System Interface Configurations The following parameters of the system interface are configurable: • Open Drain/ ...

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Data Through Mode In test mode ’Data Through’ the U-transceiver is forced to enter the ’Transparent’ state and to issue SL3T (see Table mode is activated by pin DT= set to ’1’. The DT test function can be as well ...

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Pin Descriptions 2.1 Pin Diagram (top view CRCON 50 D2D 51 D3D CLS2 VDD 55 SLOT0 SSP 56 VSS 57 PBX 58 AUTO 59 RES 60 61 CLS3 TRST TCK ...

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Pin Definitions and Functions • Table 1 Pin Definitions and Functions Pin No. Symbol ® IOM -2 Interface 13 FSC 12 DCL 14 DIN 15 DOUT Mode Selection Pins 60 RES 55 SLOT0 45 SLOT1 Data Sheet Input (I) ...

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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol 16 DSFM 32 PUP 49 CRCON 53 LT Data Sheet Input (I) Function Output (O) I Disable Super Frame Marker (PD) ’1’ = Inhibits the evaluation of the super frame ...

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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol 58 PBX 59 AUTO 56 SSP 62 DT Interface to the Analog Front End 4 CL15 11 PDM0 Data Sheet Input (I) Function Output (O) I reserved, clamp to low ...

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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol 10 PDM1 8 PDM2 7 PDM3 5 SDR 17 SDX Data Sheet Input (I) Function Output (O) I Pulse Density Modulated Receive Data of Line Port 1 pulse density modulated ...

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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol Relay Driver/ Status Pins 30, D0A 35, D0B 42, D0C 47 D0D 31, D1A 37, D1B 43, D1C 48 D1D 33, D2A 39, D2B 44, D2C 50 D2D 34, D3A ...

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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol 26, ST10 24 ST11 23, ST20 21 ST21 19, ST30 18 ST31 Test Pins 29 CLS0 20 CLS1 52 CLS2 Data Sheet Input (I) Function Output (O) I Status Pin ...

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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol 61 CLS3 JTAG Boundary Scan 64 TCK 1 TMS 2 TDI 3 TDO 63 TRST Power Supply Pins 6, 22, 38, 54 VDD 9, 25, 41, 57 VSS OD: Open ...

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Pinning Changes from DFE-Q V1.3 to DFE-Q V2.1 • Table 2 Pinning Changes Pin No. V2.1 16 DSFM 32 PUP 36 N.C. 45 SLOT1 49 CRCON SLOT0 56 SSP 58 PBX TRST Data ...

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Functional Description 3.1 Functional Overview A functional overview of the DFE-Q V2.1 is given in processing and frame formatting blocks the PEF 24911 features an on-chip activation/ deactivation controller and programmable general purpose I/O pins for the control of ...

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IOM -2 Interface ® The IOM -2 interface is a four-wire serial interface providing a symmetrical full-duplex communication link to layer-1 and layer-2 backplane devices. It transports user data, control/programming and status information via dedicated time multiplexed channels. ...

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Within one FSC-period, 128 to 512 bit are transmitted, corresponding to DCL- frequencies ranging from 2048 kHz up to 8192 kHz. The following table shows possible operating frequencies of the IOM ® Table 3 IOM -2 Data Rates DCL Frequency ...

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Figure 10 Multiplexed Frame Structure of the IOM 3.2.2 Superframe Marker Function The start of a new superframe is programmed by a FSC high-phase lasting for one single DCL-period. A FSC high-phase of two (or more) DCL-periods is transmitted for ...

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FSC DU/ IOM-2 Frame ( Figure 11 Superframe Marker If no superframe marker used, all FSC high-phases need least two DCL-periods duration. The relationship between the IOM ® IOM -2-superframe on ...

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Besides the known MON-0/2/8 commands a new MON class, MON-12 is introduced in the DFE-Q V2.1: New MON-12 Class By use of MON-12 commands the DFE-Q V2.1 provides the ability to address parts of the device internal register map and ...

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The monitor channel is full duplex and operates on a pseudo-asynchronous base, i.e. while data transfer on the bus takes place synchronized to frame synchronization, the flow of monitor data is controlled by the MR- and MX-bits. Monitor data will ...

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Standard Transmission Procedure 1. The first byte of monitor data is placed by the external controller on the DIN line of the DFE-Q V2.1 and MX is activated (low; frame No. 1). 2. The DFE-Q V2.1 reads the data of ...

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Figure 13 Abortion of Monitor Channel Transmission 3.2.5 MON-12 Protocol MON-12 commands feature direct access to the device internal register map via the Monitor channel. This means, although the DFE-Q V2.1 features no microcontroller interface, internal register functions can be ...

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Byte 1100 w MON-12 • A MON-12 read request command comprises 2 bytes, the first byte contains the MON-12 header, the second byte the register address of the data that is requested. 1. Byte 1100 r=0 ...

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Interface to the Analog Front End The interface to the PEF 24902 AFE V2 6-wire interface (see and SDR transmit and receive data is exchanged as well as control information for the start-up procedure by means of ...

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The status on SDR is synchronized to SDX. Each time-slot on SDR carries the corresponding LD bit during the last 20 bits of the slot. Figure 15 Frame Structure on SDX/SDR The data on SDX is interpreted as follows: NOP: ...

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Table 5 2B1Q Coding Table 2B1Q Data 0 – 3 – The data on SDR is interpreted as follows: LD: The level detect information is communicated to the DFE-Q V2.1 on SDR. If the signal ...

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General Purpose I/Os The DFE-Q V2.1 features 6 general purpose I/O pins per line port. This way transparent control of test relays and power feeding circuits is possible via the IOM channel. Four of the six pins are outputs, ...

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Clock Generation The U-transceiver has to synchronize onto an externally provided PTT-master clock. A phase locked loop (PLL) is integrated in the AFE (PEF 24902) to generate the 15.36 MHz system clock. A synchronized system clock guarantees that U-interface ...

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SW (Inverted) Synch Word 18 Bit (9 Quat) <--- Figure 17 U-Basic Frame Structure Out of the 222 information bits 216 contain data from 12 IOM remaining 6 bits are used to transmit maintenance information. Thus ...

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ISW Inverted Synchronization Word (quad): – SW Synchronization Word (quad): – CRC Cyclic Redundancy Check – EOC Embedded Operation Channel – ACT Activation bit – DEA Deactivation bit – CSO Colt Start Only – UOA U-Only Activation – SAI ...

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U-Frame Structure Super Basic Frame Frame 2,3 ... MON-0/2 Correspondence Super Basic Frame Frame 2,3 ... MON-0 Format 1. Byte M ON-0 ...

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EOC (M1-M3) Filtering The first three M-bits (M1-M3) in each basic U-frame constitute an EOC command/ message. For the different EOC commands and their meaning see the next paragraph. Via register MFILT the following operating modes can be set: • ...

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MON- 2 message. The user has the choice to program one of the following two options for filtering the M5 and M6 bits changes except ...

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M1-3 (EOC) M4 M5, M6 Figure 19 Maintenance Channel Filtering Options Table 7 Overhead Bits Filter Setting by CRCON Pin Pin Towards FSM (“single” M4 bits) Towards System (M4, M5, M6 bits) CRCON = 1 CRC CRCON = 0 TLL ...

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M4 Bit Reporting to State Machine Figure 20 illustrates the point of time when a detected M4 bit change is reported to the system interface and when it is reported to the state machine: • towards the system interface ...

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However, if the same filter is selected towards the state machine as programmed towards the system interface (by Bit5= ’1’ in register MFILT) the user has to be aware that if CRC mode is active the state machine is informed ...

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M4, M5, M6 Bit Control Mechanisms Figure 21 to Figure 22 show the control mechanisms that are provided for M4, M5 and M6 bit data: Via the M4WMASK register the user can selectively program which M4 bits are externally ...

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M4W Register AIB UOA '1' M4WMASK MUX '1'= M4W Reg. '0'= SM/ Pin M56W Register 1 1 Figure 21 M4, M5, M6 Bit Control in Transmit Direction MFILT.M4 M4R Register SAI ACT '1' MUX M4WMASK.Bit6 = MON-8(PACE/ PACA) State Machine ...

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Start of Maintenance Bit Evaluation MON-0/2 messages will be issued only if the receiver is synchronized. This is done to avoid meaningless MON-0/2 messages if data transmission is not synchronized. In other words, MON-0/2 messages will be issued only ...

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Embedded Operations Channel (EOC) The Embedded Operations Channel (EOC) is used to transfer data from the exchange to the terminal side and vice versa without occupying B- or D-channels used to transmit diagnostic functions and signaling information. ...

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Table 8 Supported EOC-Commands EOC The EOC protocol operates in a repetitive command/response mode. Three identical properly-addressed consecutive messages shall be received by the NT before an action is initiated. In order to cause the desired action ...

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EOC command. A MON-0 message is issued if they prove to be equal. For this particular received EOC message the ’different from previous’ rule is NOT applied. This means that a MON-0 message is even issued if the received ...

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MON-0 EOC NT T IOM - Execute IOM - MON-0 EOC A: Auto-Mode T: Transparent-Mode Figure 23 EOC-Procedure in Auto- and Transparent Mode Data Sheet M1,M2,M3, EOC U A Echo M1,M2,M3, EOC 49 PEF 24911 Functional ...

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Cyclic Redundancy Check An error monitoring function is implemented covering the and M4 data transmission of a U-superframe by a Cyclic Redundancy Check (CRC). The computed polynomial is: The check digits (CRC bits CRC1, CRC2, …, ...

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IOM -2 NT ( CRC1... CRC12 No (MON-1) NEBE (MON-8) Counter DU CRC 1... CRC 12 FEBE (MON-8) Counter (MON-1) FEBE Figure 24 CRC-Process Data Sheet U SFR(n) G(u) SFR SFR(n + ...

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Scrambling/ Descrambling The scrambling algorithm ensures that no sequences of permanent binary are transmitted defined in ETSI TS 102 080 and ANSI T1.601. The algorithms used for scrambling and descrambling in LT- and NT-mode ...

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Encoding/ Decoding (2B1Q) The 2B1Q line code is a 4-level pulse amplitude modulation (PAM) code without redundancy. 2B1Q stands for 2 Binary, 1 Quaternary. In transmit direction two-bit binary pairs are converted into quaternary symbols that are called quats. ...

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C/I Codes (2B1Q) The operational status of the DFE-Q V2.1 is controlled by the Control/Indicate channel (C/I-channel). The four C/I channels operate completely independently. Table 10 presents the existing C/I codes. A new command or indication will be recognized ...

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AI Activation Indication AR Activation Request AR0 Activation Request with act bit = 0 ARL Activation Request Local Loop ARM Activation Request Maintenance bits ARX Activation Request without 15 sec limit DR Deactivation Request DEAC Deactivation Accepted DI Deactivation Indication ...

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The following example explains the use of a state diagram by an extract of the LT-state diagram. The state explained is the “Deactivated” state in LT-mode. The state may be entered by either of three methods: – From state “Receive ...

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LT Mode State Diagram Pin-RES or . C/I= 'RES' SL0 Reset DEAC ( AR or AR0 or ARX or UAR ) & /TN Pin-SSP or RES1 C/I= 'SSP C/I='LTD' SP/SL0 Test DEAC . SL0 T9S, T4S Awake ...

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Inputs to the U-Transceiver in LT-Mode The transition criteria are described in the following sections. They are grouped into: – C/I-commands – Pin settings – Events related to the U-interface – Timers C/I-Commands AR Activation Request The U-transceiver is ...

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LT indication ’UAI’ switches to ’AR’. As soon as ’DC’ is applied instead of ’UAR’ on the LT side the line is set transparent, since the UOA bit reflects the polarity of SAI and is thus ...

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DEAC will be issued. The high level needs to be applied continuously for the transmission of single pulses. Pin-DT Data Through The function is identical with the C/I-code DT in all channels. U-Interface Events ACT = 0/1 “ACT” bit ...

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LT waits for a response (no signal level) from the NT-side, i.e. after a deactivation procedure has been started or after loss of framing in the LT occurred. LSUE Loss of Signal Level on the U-interface (error condition) After ...

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Timer Duration (ms) Function 6000 T5 1000 T6 6000 T10 40 3.16.2 Outputs of the U-Transceiver in LT-Mode Signals and indications are issued on the IOM (predefined U-signals). C/I-Indications AI Activation ...

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RSY Re-Synchronization indication after a loss of framing (LOF) For EI3, LSL and RSY indication the LT-side should react by applying the C/I-channel code RES1 to allow the U-transceiver to enter the “Receive reset” state and to reset the receiver ...

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LT-States This section describes the functions of all states defined in LT-mode. Alerting The wake-up signal TL is transmitted for 3 ms (T2) in response to an activation request from the LT side (AR or ARL). In the case ...

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TN detected for 8 periods –> transfer within the “Deactivated” state into power-up – In power-up both differential outputs, AOUTx and BOUTx, are set to the common mode DC level of VDDmin/2 – TN detected for a total of ...

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Loss of Signal The “Loss of Signal” state is entered upon the detection of a failure condition i.e. loss of receive signal (LSUE). The ACT bit is set to “0” and the C/I-channel indication LSL is issued. The U-transceiver waits ...

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S/T Deactivated The state “S/T Deactivated” will be entered if the received ACT- and SAI-bits are set to (0). In this state the signal SL3T, ACT = (0), DEA = (1) and UOA = (0) are transmitted ® downstream. On ...

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Wait for TN In “Wait for TN” the U-transceiver waits for a response (tone TN from the NT or tone TL in case of an analog loop-back) to the transmission of the wake-up signal TL response is received ...

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Operational Description The scope of this section is to describe how the DFE-Q V2.1 works and behaves in the system environment. Activation/ deactivation control procedures are exemplary given for SW programmers reference. 4.1 Reset There are two different ways ...

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Regarding the DFE-Q V2.1 power down mode means that • the DSP clock is turned off • all digital circuits (excluding the IOM • no timing signals are delivered (CLS0, ... , CLS3) • as the internal control logic of ...

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Layer 1 Activation/ Deactivation Procedures This chapter illustrates the interactions during activation and deactivation between the LT and NT station. An activation can be initiated by either of the two stations involved. A deactivation procedure can be initiated only ...

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Signal Synch. Word (SW) SL2 present 2) SL3 present 3) SL3T present signal 1) Note: Alternating 3 symbols at 10 kHz 2) Note: Must be generated by the exchange 3) Note: If state ’Line Active’ is entered ...

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Complete Activation Initiated by LT Figure 28 depicts the procedure if the activation has been initiated by the exchange side. • S/T IOM - 2 INFO 0 DC INFO INFO 2 AR INFO 3 ...

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The activation protocol and the user interactions are summarized below: • ® NT IOM -2 <––––– C/I DC (1111 –––––> C/I DI (1111 <––––– C/I PU (0111 <––––– C/I DC (1111 <––––– C/I AR (1000 –––––> C/I AI (1100 <––––– ...

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S/T IOM - 2 INFO 0 DC INFO INFO 2 AR INFO INFO 4 S-Transceiver NT Figure 29 Activation with ACT-Bit Status Ignored by the Exchange Data Sheet ...

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The activation protocol and the user interaction is summarized below: ® NT IOM -2 <––––– C/I DC (1111 ) B –––––> C/I DI (1111 ) B <––––– C/I PU (0111 ) B <––––– C/I DC (1111 ) B <––––– C/I ...

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Complete Activation Initiated by TE Figure 30 depicts the procedure if the activation has been initiated by the terminal side. • S/T IOM - 2 INFO 0 INFO 0 INFO 1 TIM Figure 30 Complete Activation ...

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NT IOM -2 <––––– C/I DC (1111 –––––> C/I DI (1111 –––––> C/I TIM (0000 <––––– C/I PU (0111 –––––> C/I AR (1000 2) –––––> TIM release <––––– C/I DC (1111 <––––– C/I AR (1000 –––––> C/I AI (1100 ...

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Complete Deactivation • S/T IOM - 2 INFO 4 INFO INFO 0 TIM INFO 0 DC S-Transceiver NT Figure 31 Complete Deactivation Deactivating the U-interface can be initiated only by the exchange. A deactivation can ...

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NT IOM -2 –––––> C/I DI (1111 <––––– C/I DC (1111 4.3.5 Partial Activation (U Only) If the U-transceiver is only partially activated the S-interface remains deactivated. When the partial activation is initiated by the LT-side, the exchange has ...

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S/T IOM - 2 INFO 0 DC INFO S-Transceiver NT Figure 32 U Only Activation Data Sheet Reference Point SL0 SN0 TL TN SN1 SN0 SL1 SL2 act = 0 dea = ...

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Activation Initiated by LT with U Active When U is already active, the S-interface can be activated either by the exchange or by the terminal. The first case is described here, the second in the next section. • S/T ...

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NT IOM -2 <––––– C/I DC (1111 –––––> C/I DI (1111 <––––– C/I AR (1000 –––––> C/I AR (1100 –––––> C/I AI (1100 <––––– C/I AI (1100 Data Sheet ® LT IOM -2 ) C/I UAR [DC] B ...

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Activation Initiated by TE with U Active When the terminal requests to activate the S-interface (U-interface already active) two cases can occur: In the first case the exchange has retained control over the S-interface activation. Then S-activation can proceed ...

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Case 1 (controlled by exchange) ® NT IOM -2 <––––– C/I DC (1111 –––––> C/I DI (1111 –––––> C/I AR (1000 <––––– C/I AR (1000 –––––> C/I AI (1100 <––––– C/I AI (1100 Data Sheet ® LT IOM -2 ) ...

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S/T IOM - 2 INFO 0 DC INFO 0 DI INFO INFO 2 INFO INFO 4 S-Transceiver NT Figure 35 TE-Activation with U Active and no Exchange Control (case 2) Case 2 (no ...

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Deactivating S/T-Interface Only The following shows the procedure for deactivating the S-interface only while leaving the U-interface active. Deactivation of the S-interface only is initiated from the exchange by setting the “UOA” bit = (0). • S/T IOM - ...

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NT IOM -2 –––––> C/I DI (1111 B <––––– C/I DC (1111 B 4.4 Maintenance and Test Functions This chapter summarizes all features provided by the DFE-Q V2.1 to support maintenance functions and system measurements. Three main groups may ...

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Loopbacks #1, #1A and #2 are controlled by the exchange. Loopbacks #1 is closed by the DFE-Q V2.1 itself whereas loopbacks #1A and #2 are remote controlled and closed in the repeater and NT. Loopback #3 is closed and controlled ...

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NT IOM <––––– C/I AR (1000B) C/I AR 4.4.1.2 Loopback No.2 - Overview For loopback #2 several alternatives exist. Both the type of loopback and the location may vary. Three loopback types belong to the loopback #2 category: ...

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Loopback No.2 - Complete Loopback Upon receiving the EOC-command LBBD in EOC automode, the NT U-transceiver does not close the loopback immediately. Because the intention of this loopback is to test the complete NT, the U-transceiver passes the complete ...

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NT IOM -2 <–––– C/I AI (1100 <–––– C/I AIL (1110 <–––– MON-0 (50 H LBBD ––––> MON-8 (F1 LBBD <–––– MON-0 RTN (FF Data Sheet ® LT IOM -2 ) C/I AI (1100 ) ––––> MON-0 ...

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Complete Loopback in EOC Transparent Mode (NT side): ® NT IOM -2 –––> C/I AI (1100 <––– C/I AI (1100 <–––– MON-0 (50 H LBBD –––> MON-0 (50 H LBBD –––> MON-8 (F1 H LBBD <–––– MON-0 RTN (FFH) –––> ...

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Single-Channel Loopback in EOC Automode (NT-side): ® NT IOM -2 –––> C/I AI (1100 <––– C/I AI (1100 <––– MON-0 LB1 (51 H <––– MON-0 LB2 (52 H <––– MON-0 (FF H RTN Single-Channel Loopback in EOC Transparent Mode (NT-side): ...

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Local Loopbacks Featured By Register LOOP Besides the standardized remote loopbacks the DFE-Q V2.1 features additional local loopbacks for enhanced test and debugging facilities. The local loopbacks that are featured by the internal register LOOP are shown in DFE-Q ...

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LOOP.LB1=1 or LOOP.LB2=1 or LOOP.LBBD= 1 LOOP.U/IOM= DFE-Q V2.1 DSP Echo Cance ller PDM + Filter Tim ing Recove ry DFE-Q V2.1 DSP Echo Cance ller PDM + Filter Tim ing Recovery Figure 39 Loopbacks Featured by Register LOOP ...

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Bit Error Rate Counter For bit error rate monitoring the DFE-Q V2.1 features a 16-bit Bit Error Rate counter (BERC) per line. The function is channel selective. The user can direct that the measurement is performed only for the ...

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A far-end block error identifies errors in transmission direction (i.e. FEBE = LT => NT error). FEBE errors are processed in the same manner as NEBE-errors. The FEBE counter is read and reset by the MON-8-command RBEF. Data Sheet Operational ...

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Near-End Errors - Summary: - Definition A near-end block error (NEBE) indicates errors that occurred in the receive direction, i.e. an detected error during transmission from NT to LT. A near-end block error is considered detected when the calculated check-sum ...

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Far End Errors - Summary: - Definition A far-end block error (FEBE) indicates errors that occurred in the transmit direction, i.e. an detected error during transmission from LT to NT. A far-end block error is detected when the U-maintenance bit ...

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MON-0 RCC requests the NT to send corrupt CRCs. Again the CRC will be permanently inverted. After issuing RCC (NT in EOC automode) near-end block errors will be registered on the LT-side. • MON-0 NCC requests the NT to ...

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Figure 40 Block Error Counter Test Data Sheet Operational Description 102 PEF 24911 2001-07-16 ...

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System Measurements The DFE-Q V2.1 features dedicated test modes to enable and ease system measurements on U-interface. How these test modes can be used to conduct the most frequently needed system measurements is described in the following sections. 4.4.4.1 ...

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There are two methods in order to transfer the U-transceiver into the reset mode (See Chapter 7.4.1 for reset timing): – hardware selection: – software selection: Both alternatives are fully compatible besides the fact that the SW selection is channel ...

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Return-Loss Measurement – Return loss is defined in ANSI T1.601 and ETSI TS 102 080 – DFE-Q V2 RESET state (C/I = ’RES’ or Pin RES= ’0’) – Measure complex impedance “Z” from 1 kHz – 200 ...

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Boundary Scan All pins except the power supply pins, the "Not Connected" pins and the pins TDI, TDO, TCK, TMS, and TRST are included in the boundary scan chain. Depending on the pin functionality one, two or three boundary scan ...

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Boundary Scan Pin Number Number TDI ––> 16. 45 17. 44 18. 43 19. 42 20. 40 21. 39 22. 37 23. 35 24. 34 25. 33 26. 32 27. 31 28. 30 29. 29 30. 28 31. 27 32. ...

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Boundary Scan Pin Number Number TDI ––> 46. 10 47. 48. 49. 50. TAP Controller The Test Access Port (TAP) controller implements the state machine defined in the JTAG standard IEEE 1149.1. Transitions on pin TMS cause the TAP controller ...

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TCK. The in/out shifting of the scan vectors is typically done using the instruction SAMPLE/PRELOAD. 0001 (INTEST) is the default value of the instruction register. SAMPLE/PRELOAD provides a snap-shot of the pin level ...

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Monitor Commands The registers of the DFE-Q V2.1 are accessed via the Monitor channel of the IOM interface. This chapter summarizes the available Monitor commands and messages. Please refer to Chapter 3.2.4 procedure. Monitor commands supported by the DFE-Q ...

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Nine MON-0 commands are defined and can be interpreted. MON-0 commands are applied at DIN, MON-0 messages are issued at DOUT for confirmation. MON-0 messages have the highest priority among MON-0,2,8 and are issued first if i.e. a MON- 2 ...

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Table 15 MON-0 Functions (cont’d) Hex- LT Function code i1- RTN Return to normal With this command all previously sent EOC-commands will be released. The EOC-processor is reset to its initial state (FF XX ACK Acknowledge If ...

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The bit positions in the MON-2 message correspond to the following overhead bits: Table 16 MON-2 and Overhead Bits Position MON-2/ U-Frame D11/M41 D10/M51 D9/M61 D8/M42 D7/M52 D6/M62 D5/M43 D4/M44 D3/M45 D2/M46 D1/M47 D0/M48 Control via U-Transceiver – ACT (Activation ...

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Transmission on U-Interface – In transmit direction register M4WMASK decides which M4, M5 and M6 bits are controlled automatically by the internal logic MON-2 message. – The DFE-Q V2.1 transmits a given bit polarity as long as ...

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Table 17 MON-8-Local Function Commands 1.Byte 2.Byte LT 2nd Code D nibble (Bin) 0000 1011 1110 PACE 0000 1011 1111 PACA 0000 1111 0000 CCRC 0000 1111 1111 NORM 0000 1111 1011 RBEN 0000 1111 1010 RBEF 0000 r r ...

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RST 0001 xxxxxxS Notes: r … r result from block error counter x … x don’t care Data Sheet MON-8-Functions Read status pin the logic state of the status pins STx0, STx1 is requested. ...

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Register Description In this section the complete register map is described that is provided with the new MON- 12 protocol. For the protocol details please refer to The register address arrangement is given in provided per line port. By ...

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Register Summary ADR 7 LP_SEL U-Interface Registers OPMODE MFILT 01 M56 FILTER H M4RMASK 07 H M4WMASK 08 H TEST LOOP FEBE 11 H NEBE 12 H ...

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Table 18 Register Map Reference Table Reg Name Access Address WR 08 M4WMASK TEST WR 0F LOOP WR 10 FEBE RD 11 NEBE RD 12 BERC RD 13 Data Sheet Reset Comment Value BC M4 Write Mask Register H H ...

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Reset of U-Transceiver Functions in State ’Deactivated’ The following U-transceiver registers are reset upon the transition to state ’Deactivated’: Register Reset to U-Interface Registers TEST LOOP FEBE 00 H NEBE 00 H BERC 0000 H 6.3 Mode Register Evaluation ...

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Detailed Register Description 6.4.1 LP_SEL - Line Port Selection Register The Line Port Selection register selects the register bank that is associated with the addressed line port. All line port specific register operations - line port specific registers are ...

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FEBE Enable/Disable external write access to FEBE Bit in register M56W 0 = external access to FEBE bit disabled - FEBE bit is set by internal FEBE counter logic 1 = external access to FEBE bit enabled - FEBE bit ...

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MFILT Reset value M56 FILTER M56 controls the validation mode of the spare bits (M51, M52, M61 per bit FILTER base. Approved M5, M6 bit changes are reported to the system interface by a ...

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CRC and TLL coverage of M4 bit data a change in M4 bit data is reported to the system interface if no CRC violation has been detected and if it has been received in three consecutive frames, the ...

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EOC transparent mode without any filtering - every EOC message is passed MON-0 message - suitable mode for Digital Loop Carrier applications - no EOC filtering: every 6ms an EOC messages is forwarded ...

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SAI S-Activity Indicator 0 = S-interface is deactivated 1 = S-interface is activated CSO Cold Start Only capable to perform ...

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M4WMASK - M4 Write Mask Register By means of the M4WMASK register the user can direct on a per bit base which M4 bits are controlled by MON-2 and which are controlled by the state machine. The M4WMASK register ...

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SCO Start-on-Command Only Bit indicates whether the DLC network will deactivate the loop between calls (defined in Bellcore TR-NWT000397 ’Start-on-Command-Only’ mode active, in LULT mode the U-transceiver shall initiate the start-up procedure only upon command from the network ...

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TEST - Test Register The Test register sets the DFE-Q V2.1 in the desired test mode. TEST Reset value BER Bit Error Rate Measurement Function – prerequisite: closed loopback #2 on the NT-side ...

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LOOP - Loop Back Register The Loop register controls local loopbacks within the DFE-Q V2.1. For the loopback configurations that ...

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U/IOM Switch that selects whether looback LB1, LB2 or LBBD is closed towards U ® or IOM - LB1, LB2, LBBD loops are closed towards IOM 1 = LB1, LB2, LBBD loops are closed towards U LBBD ...

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FEBE - Far End Block Error Counter Register The Far End Block Error Counter Register contains the FEBE value. If the register is read out it is automatically reset to ’0’. FEBE Reset value 6.4.9 ...

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Electrical Characteristics 7.1 Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature IC supply voltage Input voltage on Input pins and on high ohmic Output pin with respect to ground Maximum current supplied to any pin for more ...

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DC Characteristics Parameter Input low voltage 1) Input high voltage Output low voltage Output high voltage Input leakage current Output leakage current Input pull down current Input pull up current 1) Apply to all inputs and to DOUT in ...

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V 0.4 V Figure 43 Input/Output Waveform for AC Tests 7.4.1 Reset Timing • Parameter Active Low Period • RES reset intern Figure 44 Reset Timing Data Sheet 2.0 V 2.0 V Test Points 0.8 V 0.8 V ...

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IOM -2 Interface Timing The dynamic characteristics of the IOM period of signals is stated the time reference will all other cases 0.8 V (low) and 2.0 V (high) thresholds are used as ...

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Parameter Superframe FSC pulse width, high DIN setup time DIN hold time ® Table 20 IOM -2 Dynamic Output Characteristics Parameter 1) DCL Data delay clock Pin PUP = ’0’ Pin PUP = ’1’ 1) FSC Data delay frame 1) ...

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Boundary Scan Timing • Figure 46 Boundary Scan Timing • Table 22 Boundary Scan Dynamic Timing Requirements Parameter test clock period test clock period low test clock period high TMS set-up time to TCK TMS hold time from TCK ...

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Capacitances Parameter Input capacitance Output capacitance 7.6 Power Supply 7.6.1 Supply Voltage V to GND = +3.3 V ±0 7.6.2 Power Consumption All measurements with random 2B+D data in active states, 3.3 V (0° 70° ...

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Package Outlines • P-MQFP-64 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet 140 PEF 24911 Package Outlines Dimensions ...

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Appendix A: Standards and Specifications The table below lists the relevant standards concerning transmission performance the DFE-Q V2.1 claims to comply with. Organization ITU International Telecommunication Union ETSI European Telecommunications Standards Institute ANSI American National Standards Institute, Inc. Telcordia ...

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Glossary • A/D Analog to digital ADC Analog to digital converter AGC Automatic gain control AIN Differential U-interface input ANSI American National Standardization Institute AOUT Differential U-interface output B1, B2 64-kbit/s voice and data transmission channel BIN Differential U-interface ...

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INFO U- and S-interface signal elements as specified by ANSI/ ETSI ISDN Integrated services digital network LBBD Loop-back of B- and D-channels LT Line termination MON Monitor channel command MR Monitor read bit MX Monitor transmit bit NEBE Near-end block ...

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A Absolute Maximum Ratings 133 AC Characteristics 134 Activation 71 ANSI 141 B Bellcore 141 Boundary Scan 105 Timing 138 BT 141 C Capacitances 139 Command/ Indicate Channel 24 Controller Characteristics 134 Deactivation 71 E Electrical Characteristics ...

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