S3031B AMCC (Applied Micro Circuits Corp), S3031B Datasheet

S3031B

Manufacturer Part Number

S3031B

Description

E4/STM-1/OC-3 ATM TRANSCEIVER

Manufacturer

AMCC (Applied Micro Circuits Corp)

Datasheet

1.S3031B.pdf (22 pages)

Specifications of S3031B

0003

Case

QFP

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FEATURES

APPLICATIONS

Figure 1. System Block Diagram

April 18, 2000 / Revision E

DEVICE

SPECIFICATION

SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR

BiCMOS LVPECL CLOCK GENERATOR

• Complies with Bellcore and ITU-T

• On-chip high-frequency PLLs for clock

• Supports 155.52 Mbit/s (OC-3) and 622.08

• Selectable reference frequencies of 19.44,

• Interface to both LVPECL and LVTTL logic

• Simple interface with 3.3V or 5V optical modules

• Directly compatible with 3.3V or 5V network

• 8-bit LVTTL data path

• Compact 10 mm 64 PQFP package

• Diagnostic loopback mode

• Low jitter LVPECL serial interface

• Single 3.3 V supply

• SONET/SDH-based transmission systems

• SONET/SDH modules

• SONET/SDH test equipment

• ATM over SONET/SDH

• Section repeaters

• Add Drop Multiplexers (ADM)

• Broad-band cross-connects

• Fiber optic terminators

• Fiber optic test equipment

Processor

specifications

generation and clock recovery

Mbit/s (OC-12)

38.88, 51.84 or 77.76 MHz

interface devices

Interface

Network

SONET/SDH

Transceiver

S3032

OTX

ORX

GENERAL DESCRIPTION

The S3032 SONET/SDH transceiver chip is a fully

integrated serialization/deserialization SONET OC-12

(622.08 Mbit/s) and OC-3 (155.52 Mbit/s) interface de-

vice. The chip performs all necessary serial-to-parallel

and parallel-to-serial functions in conformance with

SONET/SDH transmission standards. The device is

suitable for SONET-based ATM applications. Figure

1 shows a typical network application.

On-chip clock synthesis is performed by the high-

frequency phase-locked loop on the S3032

transceiver chip allowing the use of a slower external

transmit clock reference. Clock recovery is performed

on the device by synchronizing its on-chip VCO directly

to the incoming data stream. The S3032 also per-

forms SONET/SDH frame detection. The chip can be

used with a 19.44, 38.88, 51.84 or 77.76 MHz refer-

ence clock, in support of existing system clocking

schemes.

The low jitter LVPECL interface guarantees compli-

ance with the bit-error rate requirements of the

Bellcore and ITU-T standards. The S3032 is pack-

aged in a 10 mm 64 PQFP, offering designers a small

package outline.

ORX

OTX

SONET/SDH

Transceiver

S3032

Processor

Interface

Network

S3032

Related parts for S3031B

S3031B Summary of contents

Page 1

DEVICE SPECIFICATION SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR BiCMOS LVPECL CLOCK GENERATOR SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER FEATURES • Complies with Bellcore and ITU-T specifications • On-chip high-frequency PLLs for clock generation and clock recovery • Supports 155.52 ...

Page 2

S3032 SONET OVERVIEW Synchronous Optical Network (SONET stan- dard for connecting one fiber system to another at the optical level. SONET, together with the Synchro- nous Digital Hierarchy (SDH) administered by the ITU-T, forms a single international standard ...

Page 3

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR Figure 4. S3032 Transceiver Functional Block Diagram Transmitter 8 PIN[7:0] 8:1 PARALLEL- TO-SERIAL PICLK TIMING GEN LLEB SLPTIME TESTEN CLOCK SYNTHESIZER RSTB CAP1 CAP2 MODE 0 MODE 1 REFCLKP/N TTLREF Receiver SDPECL 1:8 SERIAL- TO-PARALLEL OOF ...

Page 4

S3032 S3032 TRANSCEIVER FUNCTIONAL DESCRIPTION TRANSMITTER OPERATION The S3032 transceiver chip performs the serializing stage in the processing of a transmit SONET STS-3 or STS-12 bit serial data stream. It converts the 8-bit parallel 19.44 or 77.76 Mbps data stream ...

Page 5

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR RECEIVER OPERATION The S3032 transceiver chip provides the first stage of digital processing of a receive SONET STS-3 or STS-12 bit-serial stream. It converts the bit-serial 155.52 or 622.08 Mbit/sec data stream into a 19.44 or ...

Page 6

S3032 Frame and Byte Boundary Detection The frame and byte boundary detection circuitry searches the incoming data for three consecutive A1 bytes followed immediately by three consecutive A2 bytes. Framing pattern detection is enabled and dis- abled by the out-of-frame ...

Page 7

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR OTHER OPERATING MODES Diagnostic Loopback When the Diagnostic Loopback Enable (DLEB) input is active, a loopback from the transmitter to the re- ceiver at the serial data rate can be set up for diagnostic purposes. The ...

Page 8

S3032 Table 4. S3032 Transmitter Pin Assignment and Descriptions (Active High unless otherwise stated ...

Page 9

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR Table 5. S3032 Receiver Pin Assignment and Descriptions (Active High unless otherwise stated ...

Page 10

S3032 Table 6. S3032 Common Pin Assignment and Descriptions (Active High unless otherwise stated ...

Page 11

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR Table 7. S3032 Power and Ground Pin Assignments ...

Page 12

S3032 Figure 6. 64 PQFP Package Thermal Management SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR ˚ ...

Page 13

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR Figure 7. Pinout Assignments PCLKGND TXCOREGND TXCOREVCC TTLREF REFCLKN REFCLKP AVCC1 AGND1 CAP2 CAP1 AGND0 AVCC0 LLEB TXOUTVCC TSDP TSDN April 18, 2000 / Revision S3032 Pinout 7 8 ...

Page 14

S3032 Table 8. Performance Specifications ...

Page 15

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR Table 9. Absolute Maximum Ratings ...

Page 16

S3032 Table 11. LVTTL Input/Output DC Characteristics – ...

Page 17

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR Table 12. LVPECL Input/Output DC Characteristics ...

Page 18

S3032 Table 13. Transmitter AC Timing Characteristics ...

Page 19

SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR Figure 8. Transmitter Output Timing TSCLKP TSD Figure 9. PIN AC Input Timing PCLK PICLK PIN[7:0] 1. When a setup time is specified on LVTTL signals between an input and a clock, the setup time is ...

Page 20

S3032 RECEIVER FRAMING Figure 11 shows a typical reframe sequence in which a byte realignment is made. The frame and byte boundary detection is enabled by the rising edge of OOF and remains enabled while OOF is High. Both boundaries ...

Page 21

APPLICATION NOTE SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR S3032 WITH DATA CLOCK SYNCHRONOUS TO REFERENCE CLOCK In some applications it is necessary to "forward clock" the data in a SONET/SDH system. In this ap- plication the reference clock from which the High ...

Page 22

S3032 Ordering Information – Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) ...

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