FW802 Agere Systems, FW802 Datasheet
FW802
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FW802 Summary of contents
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... FW802A Low-Power PHY IEEE* 1394A-2000 Two-Cable Transceiver/Arbiter Device Distinguishing Features Compliant with IEEE Standard 1394a-2000, IEEE I Standard for a High Performance Serial Bus Amendment 1. Low-power consumption during powerdown or I microlow-power sleep mode. Supports extended BIAS_HANDSHAKE time for I enhanced interoperability with camcorders. While unpowered and connected to the bus, will not ...
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... Table 10. PHY Register Page 0: Port Status Page ............................................................................................. 20 Table 11. PHY Register Port Status Page Fields ................................................................................................ 21 Table 12. PHY Register Page 1: Vendor Identification Page ............................................................................. 22 Table 13. PHY Register Vendor Identification Page Fields ................................................................................. Table of Contents List of Figures List of Tables June 2001 Page Page Page Agere Systems Inc. ...
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... IEEE 1394-1995 Annex J. To operate with bus-keeper isolation, the /ISO pin of the FW802A must be tied high. Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight data lines (D[0:7]), and are latched internally in the PHY in synchronization with the 49 ...
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... For those applications, when FW802A is used with one of the ports not brought out to a connector, those unused ports may be left unconnected without normal termination. When a port ...
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... The SYSCLK output will become active (and the PHY/ link interface will be initialized and become operative) within 3 ms after LPS is asserted high, when the FW802A is in the low-power mode. CPS LPS /ISO CNA ...
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... SS CTL0 3 CTL1 CNA 15 LPS 16 Note: Active-low signals are indicated by “/” at the beginning of signal names, within this document PIN #1 IDENTIFIER AGERE FW802A Figure 2. Pin Assignments June 2001 DDA 42 TPBIAS1 41 TPA1+ 40 TPA1– 39 TPB1+ 38 TPB1– 37 TPBIAS0 36 TPA0+ 35 TPA0– 34 TPB0+ 33 TPB0– ...
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... After hardware reset, this pin is set as an output. If the LPS is inactive, C/LKON indicates one of the following events by asserting a 6.114 MHz signal. 1. FW802A receives a link-on packet addressed to this node. 2. Port_event register bit Any of the Timeout, Pwr_Fail, or Loop register bits are 1 and the Resume_int register bit is also 1 ...
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... V Powerdown. When asserted high, PD turns off all internal circuitry except the bias-detect circuits that drive the CNA signal. Internal FW802A logic is kept in the reset state as long asserted. PD terminal is provided for backward compatibility recommended that the FW802A be allowed to manage its own power consumption using suspend/resume in conjunction with LPS ...
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... XO * Active-low signals are indicated by “/” at the beginning of signal names, within this document. Agere Systems Inc. Two-Cable Transceiver/Arbiter Device Name/Description pair cable. Board traces from each pair of positive and negative differen- tial signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector ...
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... LLC CNA 15 LPS LLC PULSE See Figure 4 for typical port termination network. Figure 3. Typical External Component Connections PIN #1 IDENTIFIER AGERE FW802A June 2001 DDA 43 TPBIAS1 42 TPA1+ 41 TPA1– PORT 1* 40 TPB1+ 39 TPB1– 38 TPBIAS0 37 TPA0+ 36 TPA0– PORT 0* 35 TPB0+ 34 TPB0– ...
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... E-mail: 1394support@agere.com Crystal Selection Considerations The FW802A is designed to use an external 24.576 MHz crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. IEEE 1394a-2000 standard requires that FW802A have less than ±100 ppm total variation from the nominal data rate, which is directly influenced by the crystal. To achieve this recommended that an oscillator with a nominal 50 ppm or less frequency tolerance be used. The total frequency variation must be kept below ± ...
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... The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency and minimizing noise introduced into the FW802A PLL. The crystal and two load capacitors should be considered as a unit during layout. They should be placed as close as possible to one another, while minimizing the loop area created by the combination of the three components ...
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... Output Current TPBIAS Output Voltage Current Source for Connect Detect Circuit * For a node that does not source power (see Section 4.2.2.2 in IEEE 1394-1995 Standard). Agere Systems Inc. Two-Cable Transceiver/Arbiter Device Test Conditions Source power node TPB cable inputs, speed signaling off ...
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... Mbits/s speed † signaling enabled 400 Mbits/s speed † signaling enabled June 2001 Symbol Min Typ Max V 172 — 265 OD V — — 20 OFF −1.05 I — 1.05 DIFF −2.53 −4.84 I — −8.1 — −12.4 SP Agere Systems Inc. Unit ...
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... Rising Input Threshold Voltage*, LREQ, CTLn, Dn Falling Input Threshold Voltage*, LREQ, CTLn, Dn Bus Holding Current, LREQ, CTLn, Dn Rising Input Threshold Voltage LPS Falling Input Threshold Voltage LPS * Device is capable of both differentiated and undifferentiated operation. Agere Systems Inc. Two-Cable Transceiver/Arbiter Device (continued) Test Conditions Symbol ...
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... See Figure 5 50% to 50% See Figure 6 Symbol Min f 24.5735 24.5760 June 2001 Min Typ Max — — — 0.15 — — — ±0 Ω, — — 1 Ω, — — 1 — — 0 — — 1 — 6 Typ Max Unit 24.5785 MHz Agere Systems Inc. Unit ...
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... June 2001 Timing Waveforms Figure 5. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms Figure 6. Dn, CTLn Output Delay Relative to SYSCLK Waveforms Agere Systems Inc. Two-Cable Transceiver/Arbiter Device SYSCLK tsu Dn, CTLn, LREQ SYSCLK td Dn, CTLn th 5-6017.a (F) 5-6018.a (F) 17 ...
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... IEEE Standard 1394-1995 for the encoding of this field. 7 This field has a constant value of seven, which indicates the extended PHY register map. June 2001 Bit 5 Bit 6 R Gap_count Total_ports Delay Pwr_class Port_event Enab_accel Enab_multi Port_select RESERVED Description Agere Systems Inc. Bit 7 PS ...
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... Loop 1 rw Pwr_fail 1 rw Timeout 1 rw Port_event 1 rw Agere Systems Inc. Two-Cable Transceiver/Arbiter Device (continued) 2 The number of ports implemented by this PHY. This count reflects the number. 010 Indicates the speed(s) this PHY supports: 2 000 = 98.304 Mbits/s 2 001 = 98.304 and 196.608 Mbits/s ...
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... PHY register addresses 1000 Ports are numbered monotonically starting at zero, p0. Contents Bit 2 Bit 3 Bit 4 BStat Child Int_enable Fault XXXXX RESERVED June 2001 Description through 2 through 1111 , inclusive Bit 5 Bit 6 Bit 7 Connected Bias Disabled XXXXX XXXXX XXXXX Agere Systems Inc. ...
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... Connected 1 r Bias 1 r Disabled 1 rw Negotiated_speed 3 r Int_enable 1 rw Fault 1 rw Agere Systems Inc. Two-Cable Transceiver/Arbiter Device (continued) Power Reset Value — TPA line state for the port invalid — TPB line state for the port (same encoding as AStat). ...
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... Table 13. PHY Register Vendor Identification Page Fields Field Size Type Compliance_level 8 r Vendor_ID 24 r Product_ID 24 r The vendor-dependent page provides access to information used in manufacturing test of the FW802A (continued) . The format of the vendor identification page is 2 Contents Bit 2 Bit 3 Bit 4 Compliance_level Vendor_ID ...
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... PIN #1 IDENTIFIER ZONE DETAIL A DETAIL B 0.50 TYP Ordering Information Device Code Package FW802A-DB 64-Pin TQFP Agere Systems Inc. Two-Cable Transceiver/Arbiter Device 49 48 10.00 ± 0.20 12.00 ± 0. 1.40 ± 0.05 1.60 MAX SEATING PLANE 0.08 ...
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... FRANCE: (33 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid) Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Copyright © 2001 Agere Systems Inc. ...