DP83815 National Semiconductor, DP83815 Datasheet
DP83815
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DP83815 Summary of contents
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... DP83815 is a single-chip 10/100 Mb/s Ethernet Controller for the PCI bus targeted at low-cost, high volume PC mother boards, adapter cards, and embedded systems. The DP83815 fully implements the V2.2 33 MHz PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU ...
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Connection Diagram . . . . . . . . . . . . . . . . . . 4 1.1 144 LQFP Package (VNG ...
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... D3hot State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.4.5 D3cold State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.5 Wake-On-LAN (WOL) Mode . . . . . . . . . . 90 6.5.1 Entering WOL Mode . . . . . . . . . . . . . . . . . . . . . . . 90 6.5.2 Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 3-1 DP83815 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Figure 3-2 MAC/BIU Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 3-3 Ethernet Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Figure 3-4 DSP Physical Layer Block Diagram .17 Figure 3-5 LED Loading Example ...
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... GNTN 63 REQN 64 PCIVSS1 65 AD31 66 AD30 67 AD29 68 PCIVDD1 69 AD28 70 AD27 71 AD26 72 Pin1 Identification DP83815 Order Number DP83815DVNG See NS Package Number VNG144A 4 MA2/LED100N 144 143 MA1/LED10N 142 MA0/LEDACTN MD7 141 MD6 140 MD5 139 MD4/EEDO 138 VDDIO5 137 VSSIO5 136 MD3 135 MD2 ...
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... Connection Diagram (Continued) 1.2 160 pin LBGA Package (UJB) Pin A1 Identification (Marked on Top Top View Order Number DP83815DUJB See NS Package Number UJB160A 5 www.national.com ...
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... As a target, the device monitors this signal before decoding the address to check if the current transaction is addressed to it Grant: This signal is asserted low to indicate to the DP83815 that it has been granted ownership of the bus by the central arbiter. This input is used when the DP83815 is acting as a bus master ...
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... LBGA Pin No(s) Dir N9 I/O Parity Error: The DP83815 as a master or target will assert this signal low to indicate a parity error on any incoming data (except for special cycles bus master, it will monitor this signal on all write operations (except for special cycles Request: The DP83815 will assert this signal low to request ownership of the bus from the central arbiter ...
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Pin Description (Continued) Media Independent Interface (MII) LQFP Pin Symbol No(s) COL 28 CRS 29 MDC 5 MDIO 4 RXCLK 6 RXD3/MA9, 12, RXD2/MA8, 11, RXD1/MA7, 10, RXD0/MA6 7 RXDV/MA11 15 RXER/MA10 14 RXOE 13 TXCLK 31 TXD3/MA15, 25, ...
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... MA2/LED100LNK, 144, MA1/LED10LNK, 143, MA0/LEDACT 142 MWRN 131 MRDN 130 Note: DP83815 supports NM27LV010 for the BIOS ROM interface device. LBGA Pin No(s) Dir G1, A-O Transmit Data: Differential common output driver. This differential F1 common output is configurable to either 10BASE-T or 100BASE-TX signaling: 10BASE-T: Transmission of Manchester encoded 10BASE-T packet data as well as Link Pulses (including Fast Link Pulses for Auto- Negotiation purposes) ...
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... Dir D8 I Crystal/Oscillator Input: This pin is the primary clock reference input for the DP83815 and must be connected MHz 0.005% (50ppm) clock source. The DP83815 device supports either an external crystal resonator connected across pins X1 and X2 external CMOS-level oscillator source connected to pin X1 only. ...
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Pin Description (Continued) External Reference Interface LQFP Pin Symbol No(s) VREF 40 No Connects LQFP Pin Symbol No(s) NC 34, 42, 43, 48 A1, A13, A14, B3, B13, B14, D4, F3, F4, G2, M2, M3, N1, N2, N13, N14, ...
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Pin Description (Continued) Supply Pins LQFP Pin Symbol No(s) SUBGND1, 37, SUBGND2, 49, SUBGND3 126 RXAVDD1, 39, RXAVDD2 47 RXAVSS1, 38, RXAVSS2 44 TXIOVSS1, 52, TXIOVSS2 55 TXDVDD 56 TXDVSS 51 MACVDD1, 58, MACVDD2 125 MACVSS1, 57, MACVSS2 124 ...
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... KB SRAM TX-2 KB PCI CLK PCI CNTL PCI AD Figure 3-1 DP83815 Functional Block Diagram (Media Access and an 802.3 MAC. The physical layer interface used is a single-port version of the 3.3V DsPhyter. Internal memory consists of one - 0.5 KB and two - 2 KB SRAM blocks. 3V DSP Physical Layer ...
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... PME or CLKRUN function. 3.1.1.1 Byte Ordering The DP83815 can be configured to order the bytes of data on the AD[31:0] bus to conform to little endian or big endian ordering through the use of the Configuration Register, bit 0 (CFG:BEM). By default, the device is in little endian ordering ...
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... FIFO from the MAC unit before a DMA request for system memory access occurs. Once the DP83815 gets the bus, it will continue to transfer the long words from the FIFO until the data in the FIFO is less than one long word, or has reached the end of the packet, or the max DMA burst size is reached (RXCFG:MXDMA) ...
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... The DP83815 supports the attachment of an external 46B-1500B 4B EEPROM. The EEPROM interface provides the ability for the DP83815 to read from and write data to an external serial EEPROM device. The DP83815 will auto-load values from the EEPROM to certain fields in PCI configuration space and operational space and perform a checksum to verify that the data is valid ...
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Functional Description POWER ON CONFIGURATION PINS TX_DATA TX_DATA TRANSMIT CHANNELS & STATE MACHINES 100 MB/S 10 MB/S 4B/5B ENCODER NRZ TO MANCHESTER SCRAMBLER ENCODER PARALLEL TO SERIAL LINK PULSE GENERATOR NRZ TO NRZI ENCODER TRANSMIT BINARY TO FILTER MLT-3 ...
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... ANAR and bit 12 in the BMCR register are determined at power-up. The BMCR provides software with a mechanism to control the operation of the DP83815. Bits 1 & the PHYSTS register are only valid if Auto-Negotiation is disabled or after Auto-Negotiation is complete. The Auto-Negotiation protocol compares the contents of the ANLPAR and ANAR ...
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... Negotiation after the break_link_timer has expired by issuing FLP (Fast Link Pulse) bursts. 3.4.5 Enabling Auto-Negotiation via Software It is important to note that if the DP83815 has been initialized upon power- non-auto-negotiating device (forced technology), and it is then required that Auto- Negotiation or re-Auto-Negotiation be initiated via software, ...
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... Configuration register must show full duplex support: — CFG:ANEG_SEL 3.7 Phy Loopback The DP83815 includes a Phy Loopback Test mode for easy board diagnostics. The Loopback mode is selected through bit 14 (Loopback) of the Basic Mode Control Register (BMCR). Writing 1 to this bit enables transmit data to be routed to the receive path early in the physical layer cell ...
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Functional Description FROM CGM BP_4B5B BP_SCR Figure 3-6 100BASE-TX Transmit Block Diagram 3.9.1 Code-group Encoding and Injection The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups for transmission. This conversion is required ...
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... After the transmit data stream has been serialized and scrambled, the data must be NRZI encoded in order to comply with the TP-PMD standard for 100BASE-TX transmission over Category-5 un-shielded twisted pair cable. There is no ability to bypass this block within the DP83815 binary_in Table 3-1 4B5B Code-Group Encoding/Decoding ...
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... TP-PMD transition times (3 ns < Tr < 5 ns). The 100BASE-TX transmit TP-PMD function within the DP83815 is capable of sourcing only MLT-3 encoded data. Binary output from the TD outputs is not possible in 100 Mb/s mode. 3.10 100BASE-TX Receiver The 100BASE-TX receiver consists of several functional blocks which convert the scrambled MLT-3 125 Mb/s serial data stream to synchronous 4-bit nibble data that is provided to the MAC ...
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Functional Description RXCLK LINK INTEGRITY MONITOR RX_DATA VALID SSD DETECT BP_SCR CLOCK CLOCK RECOVERY MODULE (Continued) RXD(3:0)/RXER BP_RX MUX MUX BP_4B5B 4B/5B DECODER SERIAL TO PARALLEL CODE GROUP ALIGNMENT MUX DESCRAMBLER NRZI TO NRZ DECODER MLT-3 TO BINARY DECODER ...
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... Conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. Therefore, the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length. The DP83815 utilizes an extremely robust equalization scheme referred to herein as Equalization’ ...
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... Figure 3-12 MLT-3 Signal Measured at AII after 50 Figure 3-13 MLT-3 Signal Measured at AII after 100 3.10.5 MLT-3 to NRZI Decoder The DP83815 decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary NRZI data. 26 2ns/div meters of CAT V cable ...
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... A Bad Start of Stream Delimiter (Bad SSD) is any transition from consecutive idle code-groups to non-idle code-groups which is not prefixed by the code-group pair J/K. If this condition is detected, the DP83815 will assert RXER and present RXD[3:0] = 1110 to the MAC for the cycles that correspond to received 5B code-groups until at least two IDLE code groups are detected ...
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... CSMA/CD protocol. — Full Duplex mode - capable of simultaneously transmitting and receiving without reporting a collision. The DP83815's 10 Mb/s ENDEC is designed to encode and decode simultaneously. 3.11.2 Smart Squelch The smart squelch is responsible for determining when valid data is present on the differential receive inputs (RD ) ...
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... Link Integrity Monitor, but will not be able to detect that its transmission is not propagating to the other station. If three or more FEFI IDLE patterns are detected by the DP83815, then bit 4 of the Basic Mode Status register is set to one until read by management, additionally bit 7 of the PHY Status register is also set. ...
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... MDC bit (bit 6). Control of data direction is done by the MDDIR bit (bit 5). Data is either recorded or written by the MDIO bit (bit 4). Setting the MDDIR bit allows the DP83815 to drive the MDIO pin. Setting the MDDIR bit allows the MDIO bit to reflect the value of the MDIO pin. See Section 4.2.3 ...
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Functional Description MDC Z MDIO (STA PHY Address Opcode Idle Start (Write) (PHYAD = 0Ch) Figure 3-16 Typical MDC/MDIO Write Operation The receive interface ...
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... Register Set 4.1 Configuration Registers The DP83815 implements a PCI version 2.2 configuration register space. This allows a PCI BIOS to "soft" configure the DP83815. Software Reset has no effect on configuration registers. Hardware Reset returns all configuration registers to their hardware reset state. For all unused registers, writes are ignored, and reads return 0. ...
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... Unused (reads return 0) 9 FBBEN Fast Back-to-Back Enable Set the PCI BIOS to enable the DP83815 to do Fast Back-to-Back transfers (FBB transfers as a master is not implemented in the current revision). 8 SERREN SERRN Enable When SERREN and PERRSP are set, DP83815 will generate SERRN during target cycles when an address parity error is detected from the system ...
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... PERRSP Parity Error Response When set, DP83815 will assert PERRN on the detection of a data parity error when acting as the target, and will sample PERRN when acting as the initiator. Also, setting PERRSP allows SERREN to enable the assertion of SERRN. When reset, all address and data parity errors are ignored and neither SERRN nor PERRN are asserted ...
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... IOBASE Base I/O Address This is set by software to the base I/O address for the Operational Register Map. 7-2 IOSIZE Size indication Read back as 0. This allows the PCI bridge to determine that the DP83815 requires 256 bytes of I/O space. 1 Unused (reads return 0). 0 IOIND I/O Space Indicator Set DP83815 to indicate that DP83815 is capable of being mapped into I/O space ...
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... Prefetchable Set DP83815. Read Only. 2-1 MEMLOC Location Selection Set DP83815. This indicates that the base register is 32-bits wide and can be placed anywhere in the 32-bit memory space. Read Only. 0 MEMIND Memory Space Indicator Set DP83815 to indicate that DP83815 is capable of being mapped into memory space. Read Only ...
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... ROMEN ROM Enable This is used by the PCI BIOS to enable accesses to boot ROM. This allows the DP83815 to share the address decode logic between the boot ROM and itself. The BIOS will copy the contents of the boot ROM to system RAM before executing it. Set to 1 enables the address decode for boot ROM disabling access to operational target registers ...
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... Bit Name 31-27 PMES PME Support This 5 bit field indicates the power states in which DP83815 may assert PMEN indicates PMEN is enabled for that state indicates PMEN is inhibited in that state. XXXX1 - PMEN can be asserted from state D0 XXX1X - PMEN can be asserted from state D1 ...
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... This value can be loaded from the EEPROM. 7-2 Unused (reads return 0) 1-0 PSTATE Power State This 2 bit field is used to determine the current power state of DP83815, and to set a new power state Description 3.3Vaux Max. Current Required 320 mA 0 (self powered) ...
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... Register Set (Continued) 4.2 Operational Registers The DP83815 provides the following set of operational registers mapped into PCI memory space or I/O space. Writes to reserved register locations are ignored. Reads to reserved register locations return undefined values. Offset Tag MAC/BIU Registers 00h 04h ...
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... TXR and a RXR. This bit will read back a 1 during the reset operation, and be cleared the hardware when the reset operation is complete. EEPROM configuration information is not loaded here. 7 SWI Software Interrupt Setting this bit forces the DP83815 to generate a hardware interrupt. This interrupt is mask-able via the IMR. 6 unused 5 ...
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Register Set (Continued) 4.2.2 Configuration and Media Status Register This register allows configuration of a variety of device and phy options, and provides phy status information. Tag: CFG Offset: 0004h Bit Bit Name 31 LNKSTS Link Status Link status ...
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... PESEL Parity Error Detection Action This bit controls the assertion of SERR when a data parity error is detected while the DP83815 is acting as the bus master. When set, parity errors will not result in the assertion of SERR. When reset, parity errors will result in the assertion of SERR, indicating a system error. This bit should be set to a one by software if the driver can handle recovery from and reporting of data parity errors ...
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... Controls the value of the MDC pin. When set, the MDC pin is 1; when clear the MDC pin is 0. R/W 5 MDDIR MII Management Direction Controls the direction of the MDIO pin. When set, DP83815 drives the MDIO pin. When clear MDIO bit reflects the current state of the MDIO pin. R/W 4 MDIO MII Management Data Software access to the MDIO pin (see MDDIR above) ...
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Register Set (Continued) PMATCH[47:0] can be accessed via the combination of the RFCR (offset 0048h) and RFDR (offset 004Ch) registers. PMATCH holds the Ethernet address info. See Section 3.3.3. The lower 8 bits of the checksum value should be ...
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... SSERR Signaled System Error The DP83815 signaled a system error on the PCI bus. 21 RMABT Received Master Abort The DP83815 received a master abort generated as a result of target not responding. 20 RTABT Received Target Abort The DP83815 received a target abort on the PCI bus. 19-17 unused ...
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Register Set (Continued) Bit Bit Name 7 TXDESC Tx Descriptor This event is signaled after a transmit descriptor when the INTR bit in the CMDSTS field has been updated. 6 TXOK Tx Packet OK This event is signaled after ...
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Register Set (Continued) Bit Bit Name 20 RTABT Received Target Abort When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 19-17 unused 16 RXSOVR Rx Status FIFO Overrun When this bit is ...
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Register Set (Continued) 4.2.8 Interrupt Enable Register The Interrupt Enable Register controls the hardware INTR signal. Tag: IER Offset: 0018h Bit Bit Name 31-1 unused 0 IE Interrupt Enable When set to 1, the hardware INTR signal is enabled. ...
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... MLB MAC Loopback Setting this bit places the DP83815 MAC into a loopback state which routes all transmit traffic to the receiver, and disables the transmit and receive interfaces of the MII this bit allows normal MAC operation. The transmitter and receiver must be disabled before enabling the loopback mode. (Packets received during MLB mode will reflect loopback status in the receive descriptor’ ...
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Register Set (Continued) Bit Bit Name 22-20 MXDMA Max DMA Burst Size per Tx DMA Burst This field sets the maximum size of transmit DMA data bursts according to the following table: 000 = 128 32-bit words (512 bytes) ...
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... Register Set (Continued) 4.2.12 Receive Configuration Register This register is used to set the receive configuration for DP83815. Receive properties such as accepting error packets, runt packets, setting the receive drain threshold etc. are controlled here. Tag: RXCFG Offset: 0034h Bit Bit Name ...
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Register Set (Continued) Bit Bit Name 5-1 DRTH Rx Drain Threshold Specifies the drain threshold in units of 8 bytes. When the number of bytes in the receive FIFO reaches this value (times 8), or the FIFO contains a ...
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... If another CLKRUN-enabled device in the system encounters a clock start or continue event, the cycle of assertions and de-assertions of CLKRUNN will cause the DP83815 clock mux to switch the clock to the RX block back and forth between the PCI clock and the X1 clock until the event completes. ...
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... Wake Command/Status Register The WCSR register is used to configure/control and monitor the DP83815 Wake On LAN logic. The Wake On LAN logic is used to monitor the incoming packet stream while in a low-power state, and provide a wake event to the system if the desired packet type, contents, or Link change are detected. ...
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... RXDP. The incoming packet can then be transferred into Description host memory for processing. Note that the wake packet is retained for processing - this is a feature of the DP83815. In addition to the above Wake on LAN features, DP83815 also provides Wake on Pattern Matching, Wake on DA match and Wake on Magic Packet . ...
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... Pause Control/Status Register The PCR register is used to control and monitor the DP83815 Pause Frame reception logic. The Pause Frame reception Logic is used to accept 802.3x Pause Frames, extract the pause length value, and initiate a TX MAC pause interval of the specified number of slot times. ...
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... Register Set (Continued) 4.2.16 Receive Filter/Match Control Register The RFCR register is used to control and configure the DP83815 Receive Filter Control logic. The Receive Filter Control Logic is used to configure destination address filtering of incoming packets. Tag: RFCR Offset: 0048h Bit Bit Name ...
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Register Set (Continued) Bit Bit Name 9-0 RFADDR Receive Filter Extended Register Address Selects which internal receive filter register is accessible via RFDR: Perfect Match Register (PMATCH) 000h 002h 004h Pattern Count Registers (PCOUNT) 006h 008h SecureOn Password Register ...
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Register Set (Continued) 4.2.18 Receive Filter Logic The Receive Filter Logic supports a variety of techniques for qualifying incoming packets. The most basic filtering options include Accept All Broadcast, Accept All Multicast and Accept All Unicast packets. These options ...
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Register Set (Continued) Pattern3Word7F Pattern2Word7F Pattern3Word7E Pattern2Word7E Pattern3Word1 Pattern2Word1 Pattern3Word0 Pattern2Word0 Pattern1Word3F Pattern0Word3F Pattern1Word3E Pattern0Word3E Pattern1Word1 Pattern0Word1 Pattern1Word0 Pattern0Word0 Bit# Figure 4-1 Pattern Buffer Memory - 180h words (word = 18bits) byte1 byte0 byte1 byte0 byte1 byte0 byte1 byte0 ...
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Register Set (Continued) Example: Pattern match on the following destination addresses: 02-00-03-01-04-02 12-10-13-11-14-12 22-20-23-21-24-22 32-30-33-31-34-32 set $PATBUF01 = 280 set $PATBUF23 = 300 # write counts iow l $RFCR (0006) iow l $RFDR (0406) iow l $RFCR (0008) iow ...
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Register Set (Continued) Accept on Multicast or Unicast Hash Multicast and Unicast addresses may be further qualified by use of the receive filter hash functions. An internal 512 bit (64 byte) RAM-based hash table is used to perform imperfect ...
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... Tag: SRR Offset: 0058h Bit Bit Name 31-16 unused (reads return 0) 15-0 Rev Revision Level SRR register value for the DP83815 silicon. DP83815CVNG DP83815DVNG/UJB 00000403h Size: 32 bits Access: Read Write Description Size: 32 bits Access: Read Write Description Size: 32 bits Access: Read Only ...
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Register Set (Continued) 4.2.22 Management Information Base Control Register The MIBC register is used to control access to the statistics block and the warning bits and to control the collection of management information statistics. Tag: MIBC Offset: 005ch Bit ...
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... All MIB counters are cleared to 0 when read. Due to cost and space limitations, the counter bit widths provided in the DP83815 MIB are less than the bit widths called for in the above specifications assumed that management agent software will maintain a set of fully compliant statistic values (" ...
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Register Set (Continued) 4.3 Internal PHY Registers The Internal Phy Registers are only 16 bits wide. Bits [31:16] are not used. In the following register definitions under the ‘Default’ heading, the following definitions hold true: — RW=Read Write access ...
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Register Set (Continued) Bit Bit Name 7 Collision Test Collision Test: Default Collision test enabled 0 = Normal operation When set, this bit will cause the COL signal to be asserted in response to the assertion ...
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... Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. National Semiconductor's IEEE assigned OUI is 080017h. Tag: PHYIDR1 ...
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Register Set (Continued) Bit Bit Name 9 T4 100BASE-T4 Support: Default 100BASE-T4 is supported by the local device 0 = 100BASE-T4 not supported 8 TX_FD 100BASE-TX Full Duplex Support: Default: dependent on setting of the ANEG_SEL ...
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Register Set (Continued) Bit Bit Name 5 10 10BASE-T Support 10BASE-T is supported by the Link Partner 0 = 10BASE-T not supported by the Link Partner 4:0 Selector Protocol Selection Bits: Link Partners’s binary encoded protocol selector. ...
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Register Set (Continued) Bit Bit Name 12 ACK2 Acknowledge2: Default Will comply with message 0 = Cannot comply with message Acknowledge2 is used by the next page function to indicate that Local Device has the ability ...
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Register Set (Continued) Bit Bit Name 6 Remote Fault Remote Fault Remote Fault condition detected (cleared on read of BMSR (address 0x84h) register or by reset). Fault criteria: notification from Link Partner of Remote Fault via Auto-Negotiation ...
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Register Set (Continued) 4.3.10 MII Interrupt Control Register This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Link State Change, Jabber Event, Remote Fault, Auto-Negotiation Complete or any of the counters becoming half-full. ...
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Register Set (Continued) 4.3.12 False Carrier Sense Counter Register This counter provides information required to implement the “FalseCarriers” attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification. Tag: FCSCR Offset: 00D0h Bit Bit ...
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Register Set (Continued) Bit Bit Name 8 SD_OPTION Signal Detect Option Enhanced signal detect algorithm 0 = Reduced signal detect algorithm 7:6 Reserved Reserved: Read FORCE_100_OK Force 100 Mb/s Good Link: OR’ed with MAC_FORCE_LINK_100 ...
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Register Set (Continued) 4.3.16 10BASE-T Status/Control Register Tag: TBTSCR Offset: 00E8h Bit Bit Name 15:9 Unused 8 LOOPBACK_10_DIS 10BASE-T Loopback Disable: This bit is OR’ed with bit 14 (Loopback) in the BMCR Mb/s Loopback is enabled ...
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... Register Set (Continued) 4.4 Recommended Registers Configuration For optimum performance of the DP83815, version noted as DP83815CVNG (SRR = 302h), the listed register modifications must be followed in sequence. The table below contains the register’s offset address value. The register address consists of: I/O Base Address + Offset Address ...
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... Set the data consumer of the descriptor to return ownership to the data producer of the descriptor. For transmit descriptors, the driver is the data producer, and the DP83815 is the data consumer. For receive descriptors, the DP83815 is the data producer, and the driver is the data consumer. ...
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Buffer Management (Continued Packet OK 26-16 --- 15-12 11-0 SIZE Descriptor Byte Count Set to the size in bytes of the data. Bit Tag Description 26 TXA Transmit Abort 25 TFU Transmit FIFO Underrun 24 CRS Carrier ...
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... To represent a packet in a single descriptor, the MORE bit in the cmdsts field is set to 0. Table 5-4 Receive Status Bit Definitions Set DP83815 when the receive was aborted, the value of this bit always equals RXO. Exists for backward compatibility. Set DP83815 to indicate that a receive overrun condition occurred ...
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... MORE bit in all descriptors except the last one in the packet. Ethernet applications (bridges, switches, routers, etc.) can optimize memory utilization by using a single small buffer per receive descriptor, and allowing the DP83815 hardware to use the minimum number of buffers necessary to store an incoming packet. link ...
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... Packet When the CR:TXE bit is set to 1 (regardless of the current state), and the DP83815 transmitter is idle, then DP83815 will read the contents of the current transmit descriptor into the TxDescCache. The DP83815’s TxDescCache can hold a single fragment pointer/count combination. ...
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Buffer Management (Continued) State Event txIdle CR:TXE && !CTDD CR:TXE && CTDD txDescRefr XferDone txDescRead XferDone && OWN XferDone && !OWN txFIFOblock FifoAvail (descCnt == 0) && MORE (descCnt == 0) && !MORE txFragRead XferDone txDescWrite XferDone txAdvance link ...
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... The device driver receives packets from an upper layer available DP83815 transmit descriptor allocated. The fragment information is copied from the NOS specific data structure(s) to the DP83815 transmit descriptor. 3. The driver adds this descriptor to it’s internal list of transmit descriptors awaiting transmission the internal list was empty (this descriptor ...
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... When the RXE bit is set the CR register (regardless of the current state), and the DP83815 receive state machine is idle, then DP83815 will read the contents of the descriptor referenced by RXDP into the Rx Descriptor Cache. The Rx Descriptor Cache allows the DP83815 to 5.3.1 Receive State Machine ...
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Buffer Management (Continued) State Event rxIdle CR:RXE && !CRDD CR:RXE && CRDD rxDescRefr XferDone rxDescRead XferDone && !OWN XferDone && OWN rxFIFOblock FifoReady (descCnt == 0) && (rxPktBytes > 0) rxPktBytes == 0 rxFragWrite XferDone rxDescWrite XferDone rxAdvance link!= ...
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... Receive Data Flow With a bus mastering architecture, some number of buffers and descriptors for received packets must be pre-allocated when the DP83815 is initialized. The number allocated will directly affect the system's tolerance to interrupt latency. The more buffers that you pre-allocate, the longer the ...
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... PME Enable bit is set to 0 for normal operation. 6.4 Power Management The Power Management Specification presents a low-level hardware interface to PCI devices for the purpose of saving power. The DP83815 supports power states D0, D1, D2, D3hot, and D3cold as defined in the PCI Power Management increasing power reduction in the order they are listed. ...
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... Wake Command/Status Register (WCSR). (Continued) 6.5.1 Entering WOL Mode The following steps are required to place the DP83815 into WOL mode: 1. Disable the receiver by writing the Receiver Dis- able bit 3 (RXD) in the Command Register (CR - offset 00h in operational registers) ...
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... If the Power Management state is D3cold, the system will assert PCI reset, stop the PCI clock, and remove power from the PCI bus. 6.6.2 Exiting Sleep Mode The following steps are required to bring the DP83815 out of Sleep Mode the Power Management state is D3cold, the system will assert PCI reset, restore PCI bus power, and restart the PCI clock ...
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DC and AC Specifications Absolute Maximum Ratings Supply Voltage ( 3.3 V PCI signaling, 5.0 V tolerant DC Input Voltage ( Output Voltage (V ) OUT Storage Temperature Range (T ) STG Power Dissipation ...
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DC and AC Specifications 7.2 AC Specifications 7.2.1 PCI Clock Timing PCICLK Number PCICLK Low Time 7.2.1.1 PCICLK High Time 7.2.1.2 PCICLK Cycle Time 7.2.1.3 7.2.2 X1 Clock Timing X1 Number X1 Low Time 7.2.2.1 X1 High Time 7.2.2.2 ...
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... EE Disabled Note 1: Minimum reset complete time is a function of the PCI, transmit, and receive clock frequencies. Note 2: Minimum access after reset is dependent on PCI clock frequency. Accesses to DP83815 during this period will be ignored. Note disabled for non power on reset. 7.2.4 Non Power On Reset ...
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DC and AC Specifications 7.2.5 POR PCI Inactive VDD T1 EESEL TPRD Number VDD stable to EE access 7.2.5.1 VDD indicates the digital supply (AUX power plane, except PCI bus power.) Guaranteed by design. EE Configuration load duration 7.2.5.2 ...
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DC and AC Specifications 7.2.6 PCI Bus Cycles The following table parameters apply to ALL the PCI Bus Cycle Timing Diagrams contained in this section. Number Input Setup Time 7.2.6.1 Input Hold Time 7.2.6.2 Output Valid Delay 7.2.6.3 Output ...
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DC and AC Specifications PCI Configuration Write PCICLK T1 T2 FRAMEN AD[31:0] Addr C/BEN[3:0] Cmd T2 T1 IDSEL T1 IRDYN TRDYN DEVSELN T1 T2 PAR PERRN PCI Bus Master Read PCICLK T3 T3 ...
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DC and AC Specifications PCI Bus Master Write PCICLK T3 FRAMEN T3 AD[31:0] Addr T3 C/BEN[3:0] Cmd IRDYN TRDYN DEVSELN PAR PERRN PCI Target Read PCICLK T2 T1 FRAMEN T1 T2 AD[31:0] Addr C/BEN[3:0] Cmd BE ...
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DC and AC Specifications PCI Target Write PCICLK T1 T2 FRAMEN AD[31:0] Addr C/BEN[3:0] Cmd T1 IRDYN TRDYN DEVSELN T1 T2 PAR PERRN PCI Bus Master Burst Read PCICLK T3 FRAMEN T4 T3 ...
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DC and AC Specifications PCI Bus Master Burst Write PCICLK T3 FRAMEN T3 AD[31:0] Addr T3 C/BEN[3:0] Cmd IRDYN TRDYN DEVSELN PAR PERRN PCI Bus Arbitration PCICLK T5 REQN GNTN (Continued Data Data Data T4 ...
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DC and AC Specifications 7.2.7 EEPROM Auto-Load EECLK EESEL EEDO EEDI Number EECLK Cycle Time 7.2.7.1 EECLK Delay from EESEL Valid 7.2.7.2 EECLK Low to EESEL Invalid 7.2.7.3 EECLK to EEDO Valid 7.2.7.4 EEDI Setup Time to EECLK 7.2.7.5 ...
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DC and AC Specifications 7.2.8 Boot PROM/FLASH T13 MCSN T17 MRDN MA[15:0] MD[7:0] MWRN Number Data Setup Time to MRDN Invalid 7.2.8.1 Address Setup Time to MRDN 7.2.8.2 Address Hold Time from MRDN Invalid 7.2.8.3 Address Invalid from MWRN ...
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DC and AC Specifications 7.2.9 100BASE-TX Transmit TPTD T2 TPTD eye pattern Parameter Description 100 Mb/s TPTD Rise and 7.2.9.1 Fall Times 100 Mb/s Rise/Fall Mismatch 100 Mb/s TPTD 7.2.9.2 Transmit Jitter Note: Normal Mismatch is the difference between ...
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DC and AC Specifications 7.2.10 10BASE-T Transmit End of Packet TPTD+/- TPTD+/- Parameter Description End of Packet High Time 7.2.10.1 (with ‘0’ ending bit) End of Packet High Time 7.2.10.2 (with ‘1’ ending bit) 7.2.11 10 Mb/s Jabber Timing ...
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DC and AC Specifications 7.2.12 10BASE-T Normal Link Pulse Parameter Description Pulse Width 7.2.12.1 Pulse Period 7.2.12.2 Note: These specifications represent both transmit and receive timings 7.2.13 Auto-Negotiation Fast Link Pulse (FLP) T1 Fast Link Pulse(s) Parameter Description Clock, ...
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DC and AC Specifications 7.2.14 Media Independent Interface (MII ) MDC MDIO(output) MDIO(input) RXCLK RXD[3:0] RXDV,RXER TXCLK TXD[3:0] TXEN Number MDC to MDIO Valid 7.2.14.1 MDIO to MDC Setup 7.2.14.2 MDIO from MDC Hold 7.2.14.3 RXD to RXCLK Setup ...
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... Physical Dimension inches (millimeters) unless otherwise noted Order Number: DP83815DVNG NS Package Number: VNG144A 107 www.national.com ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. Order Number: DP83815DUJB NS Package Number: UJB160A 2. A critical component is any component of a life ...