AM53CF96KC Advanced Micro Devices, AM53CF96KC Datasheet
AM53CF96KC
Specifications of AM53CF96KC
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AM53CF96KC Summary of contents
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... Selection, This document contains information on a product under development at Advanced Micro Devices Inc. The information is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. ...
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AMD parity error. This command facilitates data recovery and thereby minimizes the need to re-transmit data. AMD’s exclusive power-down feature can be enabled to help reduce power consumption during the chip’s sleep mode. The receivers on the SCSI bus may ...
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SYSTEM BUS MODE DIAGRAMS BUSMD 1 DMAWR BUSMD 0 Am53CF94/96 A 3–0 DMA 7–0 DACK DREQ Single Bus Architecture: 8-Bit DMA, 8-Bit Processor V DD BUSMD 1 DMAWR BUSMD 0 Am53CF94/96 A 3–0 DMA 15–0 DACK DREQ Single Bus Architecture: ...
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AMD SYSTEM BUS MODE DIAGRAMS V DD BUSMD 1 BUSMD 0 Am53CF94/96 DMA 15–0 Dual Bus Architecture: 16-Bit DMA with Byte Control BUSMD 1 BUSMD 0 Am53CF94/ ...
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BLOCK DIAGRAM 18 DMA 15-0 DMAP 1-0 4 DMA Control 8 AD 7-0 6 Host Control CS 8 BUSMD 1-0 DFMODE CLK 8 RESET FIFO 18 ...
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AMD CONNECTION DIAGRAMS Top View SD0 12 SD1 13 SD2 14 SD3 15 SD4 16 SD5 17 SD6 18 ...
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LOGIC SYMBOL DMA 15–0 DMAP 1–0 ALE [A3] DMARD [A2] BHE [A1] AS0 [A0] DREQ DACK AD 7–0 DMAWR WR INT BUSMD 1–0 *DFMODE CLK RESET Note: *Pins available on the Am53CF96 only. RELATED AMD PRODUCTS Part Number Description 85C30 ...
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AMD ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM53CF96 K Valid Combinations AM53CF94 JC AM53CF96 KC, KC ...
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SCSI OUTPUT CONNECTIONS Am53CF94 Single Ended SCSI Bus Configuration 7–0, P Am53CF94 SDC 7–0, P SEL, BSY, REQ, ACK, RST SELC, BSYC, REQC, ACKC, RSTC MSG, C/D, I/O, ...
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AMD SCSI OUTPUT CONNECTIONS Am53CF96 Single Ended SCSI Bus Configuration Am53CF96 Differential SCSI Bus Configuration 7–0, P Am53CF96 SDC 7–0, P SEL, BSY, REQ, ACK, RST SELC, ...
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TSEL MSG – MSG + MSG TSEL C/D – C/D + C/D TSEL I/O – I/O + I/O 75ALS170 ISEL ATN – ATN + ATN 75ALS170 Vcc SELC GND – SEL SEL + SEL BSYC GND – BSY BSY + ...
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AMD TSEL MSG MSG TSEL TSEL C/D C/D TSEL TSEL I/O I/O TSEL ISEL ATN ATN ISEL SELC GND SEL GND BSYC GND BSY GND RSTC GND RST GND TSEL REQC REQ GND ISEL ACKC ACK GND Differential Transceiver Connections ...
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PIN DESCRIPTION Host Interface Signals DMA 15–0 Data/DMA Bus (Input/Output, Active High, Internal Pull-up) The configuration of this bus depends on the Bus Mode 1–0 (BUSMD 1–0) inputs. When the device is config- ured for single bus operation, the host ...
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AMD DMAWR DMA Write (Input, Active Low) This signal writes the data onto the DMA 15–0 and DMAP 1–0 bus into the internal FIFO when DACK is also active. When in the single bus mode this signal must be tied ...
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SD P SCSI Data Parity (Input/Output, Active Low, Schmitt Trigger) When the device is configured in the Single Ended SCSI Mode (DFMODE inactive) this pin is defined as the input for the SCSI data parity. When the device is configured ...
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AMD RSTC Reset Control (Output, Active Low, Open Drain) This is a SCSI output with 48 mA drive. The Reset SCSI command will cause the device to drive RSTC active for 25 ms–40 ms, which will depend on the CLK ...
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Current Transfer Count Register (00H, 01H, 0EH) Read Only Current Transfer Count Register CTCREG CRVL23 CRVL22 CRVL21 CRVL20 CRVL19 CRVL18 CRVL15 CRVL14 CRVL13 CRVL12 CRVL11 ...
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AMD FIFO Register (02H) Read/Write FIFO Register FFREG FF7 FF6 FF5 FF4 FF3 FF2 FFREG – Bits 7:0 – FF 7:0 – FIFO 7:0 The FIFO on the Am53CF94/96 is ...
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Initiator Commands CMD6 CMD5 CMD4 CMD3 Target Commands CMD6 CMD5 CMD4 CMD3 ...
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AMD Status Register (04H) Read Status Register STATREG 7 INT 0 This read only register contains flags to indicate the status and phase of the SCSI transactions. It indicates whether an interrupt or error condition exists. It should be read ...
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STATREG – Bit 2 – MSG – Message STATREG – Bit 1 – C/D – Command/Data STATREG – Bit 0 – I/O – Input/Output Bit2 Bit1 Bit0 MSG C/D I ...
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AMD Interrupt Status Register (05H) Read Interrupt Status Register INSTREG 7 6 SRST ICMD 0 0 The Interrupt Status Register (INSTREG) will indicate the reason for the interrupt. This register is used with the Status Register (STATREG) and Internal State ...
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SCSI Timeout Register (05H) Write SCSI Timeout Register STIMREG STIM7 STIM6 STIM5 STIM4 STIM3 STIM2 This register determines how long the Initiator (Target) will wait for a response to a ...
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AMD Initiator Select without ATN Steps Internal State Interrupt Status Register (06H) Register (05H) Bits 2:0 (Hex) Bits 7:0 (Hex Initiator Select with ATN Steps Internal State Interrupt Status Register (06H) Register ...
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Target Select without ATN Steps Internal State Interrupt Status Register (06H) Register (05H) Bits 2:0 (Hex) Bits 7:0 (Hex Target Select with ATN Steps, SCSI-2 Bit NOT SET Internal State ...
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AMD Target Receive Command Steps Internal State Interrupt Status Register (06H) Register (05H) Bits 2:0 (Hex) Bits 7:0 (Hex Target Disconnect Steps Internal State Interrupt Status Register (06H) Register (05H) Bits 2:0 ...
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Synchronous Transfer Period Register (06H) Write Synchronous Transfer Period Register STPREG 7 6 RES RES x x The Synchronous Transfer Period Register (STPREG) contains a 5-bit value indicating the number of clock cy- cles each byte will take to be ...
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AMD Current FIFO/Internal State Register (07H) Read Current FIFO/Internal State Register CFISREG 7 6 IS2 IS1 0 0 This register has two fields, the Current FIFO field and the Internal State field. CFISREG – Bits 7:5 – IS 2:0 – ...
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Deassertion Delay SOFREG FASTCLK REQ/ACK Bits 7:6 Ctrl 3, Bit 3 Input CLK Cycles 00 0 Default – 0 cycles 01 0 1/2 cycle early cycle delay 11 0 1/2 cycle delay 00 1 Default – 0 ...
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AMD the PERE bit is reset and bad parity occurs it is not de- tected and no action is taken. CNTLREG1 – Bit 3 – STE – Self Test Enable The STE bit is for test use only. When the ...
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Forced Test Mode Register (0AH) Write Forced Test Mode Register FTMREG 7 6 RES RES x x The Forced Test Mode Register (FTMREG) is for test use only. The STE bit in the Control Register One (CNTLREG1) must be set ...
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AMD and then issue an information transfer command. The first word the device will write to the memory (via DMA) will consists of the lower byte from the DALREG and the upper byte from the first byte received from the ...
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Control Register Three (0CH) Read/Write Control Register Three CNTLREG3 7 6 ADID QTAG G2CB CHK 0 0 CNTLREG3 – Bit 7 – ADIDCHK – Additional ID Check Enables additional check on ID message during bus- initiated Select or Reselect with ...
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AMD CNTLREG3 CNTLREG3 FASTSCSI FASTCLK Clock Bit 4 Bit 3 Frequency 1 1 25–40 MHz 10 MBytes 25–40 MHz 5 MBytes/sec, –– 0 < MHz 5 MBytes/sec, –– = don’t care CNTLREG3 – Bit 2 – ...
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Control Register Four (0DH) Control Register Four CNTLREG4 7 6 GE1 GE0 0 0 This register is used to control several AMD proprietary features implemented in the Am53CF94/96. At power up, this register will show a ‘0’ value on all ...
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AMD Data Alignment Register (0FH) Write Data Alignment Register DALREG DA7 DA6 DA5 DA4 DA3 DA2 The Data Alignment Register (DALREG) is used if the first byte of ...
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COMMANDS The device commands can be broadly divided into two categories, DMA commands and non-DMA commands. DMA commands are those which cause data movement between the host memory and the SCSI bus while non- Summary of Commands Command Initiator Commands ...
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AMD COMMAND DESCRIPTION Initiator Commands Initiator commands are executed by the device when the Initiator mode. If the device is not in the Initia- tor mode and an Initiator command is received the device will ignore the ...
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Initiator Command Complete Steps (Command Code 11H/91H) The Initiator Command Complete Steps command is normally issued when the SCSI bus is in the Status In phase. One Status byte followed by one Message byte is transferred if this command completes ...
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AMD Send Data Command (Command Code 22H/A2H) The Send Data Command is used by the Target to inform the Initiator to receive data bytes. The SCSI bus phase lines are set to the Data-In Phase and data bytes are transferred ...
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Receive Command Steps Command (Command Code 2BH/ABH) The Receive Command Steps Command is used by the Target to request command information bytes from the Initiator. During this command the Target receives the command information bytes from the Initiator while the ...
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AMD Select without ATN Steps Command (Command Code 41H/C1H) The Select without ATN Steps Command is used by the Initiator to select a Target. When this command is issued the device arbitrates for the control of the SCSI bus. When ...
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FIFO before issuing this command. This com- mand will be terminated early in the following situations: The SCSI Timeout Register times out The Target does not go to the Message Out Phase following the Selection Phase The Target ...
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AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . ...
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DC OPERATING CHARACTERISTICS Parameter Symbol Parameter Description I Static Supply Current DDS I Dynamic Supply Current DDD I Latch Up Current LU C Capacitance SCSI Pins V Input High Voltage IH V Input Low Voltage IL V Input Hysterisis IHST ...
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AMD DC OPERATING CHARACTERISTICS (continued) Parameter Symbol Parameter Description Input Pins V Input High Voltage IH V Input Low Voltage IL I Input Low Voltage IL I Input High Voltage IH SWITCHING TEST CIRCUIT From Output Under Test SWITCHING TEST ...
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KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Will be Steady Steady May Will be Change Changing from from May Will be ...
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AMD CLK FastClk Disabled (Control Register Three (0CH) bit 3=0) Parameter No. Symbol Parameter Description Clock Pulse Width Low PWL 2 t Clock period ( Synchronization latency Clock Pulse Width ...
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RESET Parameter No. Symbol Parameter Description 5 t Reset Pulse Width High PWH Note: There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B). INT RD Parameter No. Symbol Parameter Description INT ...
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AMD A 3– 7–0 DMA 7–0 DMAP 0 Register Read with Non-Multiplexed Address Data Bus A 3– 7–0 DMA 7–0 DMAP 0 Register Write with Non-Multiplexed Address Data Bus ...
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Register Read/Write with Non-Multiplexed Address Data Bus Parameter No. Symbol Parameter Description Address Address Data Valid Delay PD RD Pulse ...
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AMD 32 ALE 7–0 Address CS RD Register Read with Muliplexed Address Data Bus 32 ALE 7–0 Address CS WR Register Write with Multiplexed Address Data Bus ...
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Register Read/Write with Multiplexed Address Data Bus Parameter No. Symbol Parameter Description 32 t ALE Pulse Width High PWH 33 t Address to ALE Address to ALE ALE ...
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AMD DREQ DACK DMA 15–0 DMAP 1–0 DREQ DACK DMAWR DMA 15–0 DMAP 1– DMA Read without Byte Control 58 59 ...
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DMA Read/Write without Byte Control Parameter No. Symbol Parameter Description DACK DACK DACK Pulse Width Low 60 t PWL DACK DACK DACK DACK Pulse Width ...
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AMD DREQ DACK AS 0 BHE DMARD DMA 15–0 DMAP 1–0 DREQ 76 DACK AS 0 BHE DMAWR DMA 15–0 DMAP 1– ...
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DMA Read/Write with Byte Control Parameter No. Symbol Parameter Description DACK DACK DACK Pulse Width Low 78 t PWL DACK BHE, AS0 to DMARD DMARD Pulse Width Low ...
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AMD DREQ DACK RD DMA 15–0 DMAP 1–0 Burst DMA Read without Byte Control—Modes 0 and 1 DREQ 104 DACK DMAWR 120 DMA 15–0 DMAP 1–0 Burst DMA Write without Byte Control—Modes 0 and ...
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Burst DMA Read/Write Mode 0, 1 Parameter No. Symbol Parameter Description DACK 104 t PD DACK Pulse Width Low 105 t PWL DACK 106 DACK 107 108 t to Data Valid Delay PD ...
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AMD DREQ DACK AS 0 BHE 129 DMARD DMA 15–0 DMAP 1–0 Burst DMA Read with Byte Control—Mode 2 DREQ DACK AS 0 BHE 146 DMAWR 145 DMA 15–0 DMAP 1–0 Burst DMA Write with Byte Control—Mode ...
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Burst DMA–Mode 2 Parameter No. Symbol Parameter Description DACK 127 t PD DACK Pulse Width Low 128 t PWL BHE, AS0 to DMARD 129 t S DACK 130 t S DMARD 131 t PD DMARD Pulse Width High 132 t ...
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AMD DREQ DACK DMA 15–0 DMAP 1–0 Burst DMA Read without Byte Control—Mode 3 DREQ DACK DMAWR/ DMA 15–0 DMAP 1–0 Burst DMA Write without Byte Control—Mode ...
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Burst DMA Mode 3 Parameter No. Symbol Parameter Description DACK 154 t PD DACK Pulse Width Low 155 t PWL DACK 156 t PD DACK 157 t PD DACK Pulse Width High 158 t PWH DACK 159 t Z DACK ...
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AMD SDC 7–0 SDCP ACKC REQ Single Ended: Parameter No. Symbol Parameter Description Data to ACKC 169 t S REQ 170 t PD REQ 171 t PD REQ 172 t PD Differential: Parameter No. Symbol Parameter Description Data to ACKC ...
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SD 7–0 SDP ACKC REQ Single Ended: Parameter No. Symbol Parameter Description REQ 173 t PD REQ 174 t PD Data to REQ 175 t S REQ 176 t H Differential: Parameter No. Symbol Parameter Description REQ 173 t PD ...
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AMD SD 7–0 SDP REQC ACK Single Ended: Parameter No. Symbol Parameter Description Data to REQC 177 t S ACK 178 t H ACK 179 t PD ACK 180 t PD Differential: Parameter No. Symbol Parameter Description Data to REQC ...
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SDC 7–0 SDCP REQC ACK Single Ended: Parameter No. Symbol Parameter Description ACK 181 t PD ACK 182 t PD Data to ACK 183 t S ACK 184 t H Differential: Parameter No. Symbol Parameter Description ACK 181 t PD ...
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AMD SDC 7–0 SDCP REQC ACKC Normal SCSI: (Single Ended) Parameter No. Symbol Parameter Description ACKC or REQC 185 t S Set Up Time REQC or ACKC Pulse Width Low 186 t PWL REQC or ACKC Pulse Width High 187 ...
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SDC 7–0 SDCP REQ ACK Parameter No. Symbol Parameter Description REQ Pulse Width Low 189 t PWL ACK Pulse Width Low 189 t PWL REQ Pulse Width High 190 t PWH ACK Pulse Width High 190 t PWH Data to ...
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AMD APPENDIX A Pin Connection Cross Reference for Am53CF94 Pin# AMD 1 DMAP0 DMA8 4 DMA9 5 DMA10 6 DMA11 7 DMA12 8 DMA13 9 DMA14 10 DMA15 11 DMAP1 SD0 12 SD1 13 SD2 14 ...
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APPENDIX A Pin Connection Cross Reference for Am53CF96 Pin# AMD DACK 1 DMAWR ISEL TSEL DMA0 9 DMA1 10 DMA2 11 DMA3 12 DMA4 13 DMA5 14 DMA6 ...
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AMD APPENDIX B Emulex to AMD Timing Parameters Cross Reference Emulex AMD Parameter # Parameter # Clock Input, Reset Input, Interrupt Output Register Interface Timing ...
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PHYSICAL DIMENSIONS* PL 084 Plastic Leaded Chip Carrier (measured in inches) .050 .042 REF .048 1.185 1.150 1.195 1.156 * For reference only. BSC is an ANSI standard for Basic Space Centering ...
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AMD PHYSICAL DIMENSIONS* PQR100 Plastic Quad Flatpack Trimmed and Formed (measured in millimeters) PQJ 100 (Plastic Quad Flat Pack; Trimmed and Formed) 0.22 0.38 0.65 REF 2.60 3.00 0.25 MIN * For reference only. BSC is an ANSI standard for ...
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PHYSICAL DIMENSIONS* PQR100 Plastic Quad Flatpack with Molded Carrier Ring (measured in millimeters) 35.50 27.87 22.15 35.90 28.13 22.25 25.15 35.87 31.37 19.80 25.25 36.13 31.63 20.10 .45 Typ .65 Pitch .65 Typ * For reference only. Not drawn to ...
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... Copyright 1993 Advanced Micro Devices. All rights reserved. AMD and Am386 are registered trademarks of Advanced Micro Devices, Inc. GLITCH EATER is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ...