CY7C016 Cypress Semiconductor Corporation., CY7C016 Datasheet

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CY7C016

Manufacturer Part Number
CY7C016
Description
16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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with Sem, In t, Busy
Features
Functional Description
The CY7C006 and CY7C016 are high-speed CMOS 16K x 8
and 16K x 9 dual-port static RAMs. Various arbitration
Cypress Semiconductor Corporation
Logic Block Diagram
• True dual-ported memory cells which allow
• 16K x 8 organization (CY7C006)
• 16K x 9 organization (CY7C016)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: I
• Fully asynchronous operation
• Automatic power-down
• TTL compatible
• Expandable data bus to 16/18 bits or more using
• Busy arbitration scheme provided
• Semaphores included to permit software handshaking
• INT flag for port-to-port communication
• Available in 68-pin PLCC (7C006), 64-pin (7C006) and
• Pin compatible and functional equivalent to
Notes:
1.
2.
simultaneous reads of the same memory location
Master/Slave chip select when using more than one
device
between ports
80-pin (7C016) TQFP
IDT7006/IDT7016
BUSY is an output in master mode and an input in slave mode.
Interrupt: push-pull output and requires no pull-up resistor.
CC
(7C016) I/O
= 140 mA (typ.)
BUSY
R/W
I/O
I/O
A
CE
OE
A
13L
7L
0L
8L
0L
L
L
L
L
[1,2]
INT
SEM
L
[2]
L
3901 North First Street
DECODER
ADDRESS
R/W
CE
OE
L
L
L
CONTROL
I/O
16K x 8/9 Dual-Port Static RAM
schemes are included on the CY7C006/016 to handle situa-
tions when multiple processors access the same piece of data.
Two ports are provided, permitting independent, asynchro-
nous access for reads and writes to any location in memory.
The CY7C006/016 can be utilized as a standalone
128-/144-Kbit dual-port static RAM or multiple devices can be
combined in order to function as a 16-/18-bit or wider mas-
ter/slave dual-port static RAM. An M/S pin is provided for im-
plementing 16-/18-bit or wider memory applications without
the need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multi-
processor designs, communications status buffering, and du-
al-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags, BUSY and INT, are provided on each port. BUSY signals
that the port is trying to access the same location currently
being accessed by the other port. The Interrupt flag (INT) per-
mits communication between ports or systems by means of a
mail box. The semaphores are used to pass a flag, or token,
from one port to the other to indicate that a shared resource is
in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared re-
source is in use. An automatic power-down feature is con-
trolled independently on each port by a Chip Enable (CE) pin
or SEM pin.
The CY7C006 and CY7C016 are available in 68-pin PLCC
(CY7C006), 64-pin (CY7C006) TQFP , and 80-pin (CY7C016) TQFP .
ARBITRATION
SEMAPHORE
INTERRUPT
MEMORY
ARRAY
M/S
San Jose
CONTROL
I/O
DECODER
CE
OE
R/W
ADDRESS
with Sem, Int, Busy
R
R
R
CA 95134
SEM
INT
R
R
[2]
December 22, 1999
R/W
CE
OE
I/O
I/O
I/O
BUSY
A
A
13R
0R
CY7C006
CY7C016
8R
R
R
7R
0R
R
C006-1
(7C016)
R
408-943-2600
[1,2]

Related parts for CY7C016

CY7C016 Summary of contents

Page 1

... Available in 68-pin PLCC (7C006), 64-pin (7C006) and 80-pin (7C016) TQFP • Pin compatible and functional equivalent to IDT7006/IDT7016 Functional Description The CY7C006 and CY7C016 are high-speed CMOS 16K x 8 and 16K x 9 dual-port static RAMs. Various arbitration Logic Block Diagram (7C016) I/O Notes: 1 ...

Page 2

... I GND I/O 0R I I/O 3R I/O 4R I/O 5R I/O6 R I/O 2L I/O 3L I/O 4L I/O 5L GND I GND I/O 0R I I/O 3R I/O 4R I/O 5R Note: 3. I/O for CY7C016 only. 68-Pin PLCC Top View CY7C006 64-Pin TQFP Top View CY7C006 CY7C006 CY7C016 ...

Page 3

... Semaphores are requested by writing a 0 into the respective location. Interrupt Flag. INT is set when right port writes location 3FFE and is L cleared when left port reads location 3FFE. INT location 3FFF and is cleared when right port reads location 3FFF. Busy Flag Master or Slave Select Power Ground 3 CY7C006 CY7C016 ...

Page 4

... IN One Port Com’ – 0.2V Ind V V – 0. 0.2V, Active IN [5] Port Outputs MAX 4 CY7C006 CY7C016 7C006-35 7C006-55 7C016-35 7C016- 210 200 50 40 Ambient Temperature + – + 7C006-15 7C006-25 7C016-15 7C016-25 Min. Typ. Max. Min. Typ. Max. Unit 2.4 2.4 ...

Page 5

... MHz 5. =250 TH OUTPUT C= (b) Thévenin Equivalent (Load) ALL INPUT PULSES 3.0V 90% 90% 10% 10% GND CY7C006 CY7C016 7C006-35 7C006-55 7C016-35 7C016-55 Min. Typ. Max. Min. Typ. Max. Unit 2.4 2.4 0.4 0.4 2.2 2.2 0.8 0.8 –10 +10 –10 +10 –10 +10 –10 +10 150 210 ...

Page 6

... BDD [7] 7C006-15 7C006-25 7C016-15 7C016-25 Min. Max. Min. Max Note 13 Note 13 is less than t and t HZCE LZCE HZOE – t (actual – t (actual). WDD PWE DDD SD 6 CY7C006 CY7C016 7C006-35 7C006-55 7C016-35 7C016-55 Min. Max. Min. Max. Unit ...

Page 7

... L, SEM = H when accessing RAM SEM = L when accessing semaphores. L [7] (continued) 7C006-15 7C006-25 7C016-15 7C016-25 Min. Max. Min [15, 16 [15, 17, 18] t ACE t DOE LZOE DATA VALID 7 CY7C006 CY7C016 7C006-35 7C006-55 7C016-35 7C016-55 Max. Min. Max. Min. Max DATA VALID t HZCE t HZOE t PD Unit ...

Page 8

... R/W must be HIGH during all address transitions. [19, 20 MATCH t PWE t SD VALID MATCH t WDD [21, 22, 23 SCE PWE t SD DATA VALID HIGH IMPEDANCE allow the I/O drivers to turn off and data to be placed on PWE HZWE SD 8 CY7C006 CY7C016 DDD VALID C006- LZOE C006-13 ...

Page 9

... CE = HIGH for the duration of the above timing (both write and read cycle). [20, 22, 24 SCE PWE t SD DATA VALID t HZWE HIGH IMPEDANCE [25 VALID ADDRESS SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE 9 CY7C006 CY7C016 LZWE C006-14 t OHA t ACE DATA VALID OUT t DOE C006-15 ...

Page 10

... SPS MATCH t SPS MATCH t WC MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE HIGH CY7C006 CY7C016 C006- BHA t BDD t DDD VALID C006-17 C006-18 ...

Page 11

... R 31 depends on which enable pin (CE INS INR L [29] ADDRESS MATCH BLC ADDRESS MATCH BLC [28 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA ) is deasserted first R asserted last CY7C006 CY7C016 t BHC C006-19 t BHC C006-20 C006-21 C006-22 ...

Page 12

... INT R 31 INS Right Side Clears INT : R ADDRESS R INT R Right Side Sets INT : L ADDRESS R/W R INT L [30] t INS Left Side Clears INT : L ADDRESS R INT WRITE 3FFF [30 INR t WC WRITE 3FFF [30 INR 12 CY7C006 CY7C016 C006- READ 3FFF C006-24 C006- READ 3FFF C006-26 ...

Page 13

... L 3FFE 3FFF CY7C006 CY7C016 ) is set. This flag is cleared when the right port reads and INT are push-pull outputs and R L BLA after CE is taken LOW. BUSY and BUSY BLC L ). Otherwise, the slave chip may begin a write BLA before attempting to read the sema- ...

Page 14

... Plastic Leaded Chip Carrier A65 64-Lead Thin Quad Flat Package J81 68-Lead Plastic Leaded Chip Carrier 14 CY7C006 CY7C016 of each other, the semaphore will definitely SPS Status Semaphore free Left port obtains semaphore Right side is denied access Right port is granted access to semaphore No change ...

Page 15

... Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C016-15AC 25 CY7C016-25AC CY7C016-25AI 35 CY7C016-35AC CY7C016-35AI 55 CY7C016-55AC CY7C016-55AI Document #: 38-00416-B Package Diagrams 64-Lead Thin Plastic Quad Flat Pack ( 1.4 mm) A65 Package Name Package Type A80 80-Lead Thin Quad Flat Package A80 80-Lead Thin Quad Flat Package A80 ...

Page 16

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 80-Pin Thin Plastic Quad Flat Pack A80 68-Lead Plastic Leaded Chip Carrier J81 CY7C006 CY7C016 51-85065-B 51-85005-A ...

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