DP83924 National Semiconductor, DP83924 Datasheet
DP83924
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DP83924 Summary of contents
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... DP83924BVCE Quad 10 Mb/s Ethernet Physical Layer - 4TPHY™ General Description The DP83924B Quad 10Mbps Ethernet Physical Layer (4TPHY 4-Port Twisted Pair PHYsical Layer Trans- ceiver that includes all the circuitry required to interface four Ethernet Media Access Controllers (MACs) to 10BASE-T. This device is ideally suited for switch hub applications where ports are commonly used ...
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... The transceivers include on-chip filtered transmit outputs, which reduce emissions and eliminate the need for exter- nal filter. The DP83924BVCE maintains complete hardware and software backwards compatibility with the DP83924AVCE with only a change to one resistor value and disconnecting a second resistor. Transmit ...
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Table of Contents 1.0 Pin Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 Pin ...
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... VDD_DIG 86 LED_CLK 87 LED_DATA 88 LINK_1 89 LINK_2 90 GND_2 91 LINK_3, INT 92 LPBK, MDC 93 LINK_4, MDIO GND_CLK 96 VDD_CLK 100 Figure 1. 100-Pin Plastic Quad Flat Pack (PQFP) Pinout DP83924B Order Number DP83924BVCE NS Package Number VCE100A TXE[3] 46 TXD[3] 45 RXC[4] 44 COL[4] 43 CRS[4] 42 RXD[4] 41 TXE[4] 40 TXD[4] 39 RESET 38 FDX[4] 37 FDX[3] 36 ...
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Pin Information (Continued) 1.2 Pin Description Table 1. NRZ CONTROLLER INTERFACE and MANAGEMENT INTERFACE. These pins provide the interface signalling between the Media Access Controller and the transceiver. (30 Pins) Symbol Pin # Type TXC 77 O Transmit Clock: ...
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Pin Information (Continued) Table 1. NRZ CONTROLLER INTERFACE and MANAGEMENT INTERFACE. These pins provide the interface signalling between the Media Access Controller and the transceiver. (30 Pins) Symbol Pin # Type MDIO 94 I/O Management Data I/O: When management ...
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Pin Information (Continued) Table 3. LED & GENERAL CONFIGURATION Pins (8 Pins) Symbol Pins Type LED_DATA 88 O LED serial data output: This pin outputs the serial LED data. See S ection2.3 for a de- scription of the LED ...
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Pin Information (Continued) Table 5. POWER AND GROUND Pins (33 Pins) Symbol Pins 100 VDD_TPI_4 VDD_TPI_3 27 VDD_TPI_2 VDD_TPI_1 GND_TPI_4 28 GND_TPI_3 22 GND_TPI_2 ...
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... The 4TPHY utilizes a programmable MAC digital interface which enables it to directly interface to standard controllers from National Semiconductor, TI, AMD, Seeq, Fujitsu, and Intel. The compatibility modes are selected either by soft- ware via the Global Control/Status Register or by hardware strap options on pins RXD[3:1]. See Table 7 below. ...
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Interface Descriptions In addition to the compatibility mode options, the recovered clock (RXC) is selectable for 5 RXCs after the deassertion of carrier sense (CRS) or for continuous RXCs after the TXC Setup TXE TXD COL RXC Setup CRS ...
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Interface Descriptions Parameter RXCs Active Edge of TXc that TXD is sampled Polarity of active TXE Edge of RXC that RXD is clocked Polarity of CRS asserted Level of RXD during CRS deassertion Low Polarity of active COL Polarity ...
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Interface Descriptions LED_CLK act.1 LED_DATA Figure 4. Normal LED Mode Timing Diagram LED_CLK FDX Link FDX Link LED_DATA coded coded Port.1 Port.2 Figure 5. Enhanced Mode LED Timing Diagram TXU+ TXU- RXI+ RXI- ROC ~ 1 KOhm Figure 6. ...
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Interface Descriptions CD+ CD- RX+ RX- TX+ TX- R1 39.2 Oscillator 20MHz, 0.01% 40-60% Duty Cycle Drive 2 TTL Loads V CC Oscillator Figure 8. External Oscillator Connection Diagram (Continued 39.2 39.2 39 0.01 ...
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Detailed Functional Description This product utilizes the standard 10BASE-T and AUI inter- face core building blocks which are replicated on this device, one per port. The basic function of these blocks are described in the following sections. Also described ...
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Detailed Functional Description 1 the chip side and 2 on the cable side) isolation transformer. 3.2 ENDEC Module The ENDEC consists of two major blocks: — The Manchester encoder accepts NRZ data from the controller, encodes the ...
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Detailed Functional Description CRS a RXC b RXC c RXC RXD Figure 10. Receive Clock Timing - Continuous RXC Mode vs. 5 RXC Mode a. There will be a transition period where the RXC switches from the internal clock ...
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Detailed Functional Description control logic is used to select the non-default modes, instead of pull down resistors, then the level on the strap- ping pins must be maintained for approximately 10 clocks after the RESET signal deasserts. There are ...
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... Block Auto-negotiation Block Figure 11. Auto-Negotiation Block Diagram The DP83924B reserves five pins, called the Test Access Port (TAP), to provide test access: TMS, TCK, Test Data Input (TDI), Test Data Output (TDO) and Test Reset (TRST). These signals are describe able4 on page7. ...
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... The bypass instruction uses the bypass register. The bypass register contains a single shift-register stage and is used to provide a minimum length serial path between the TDI and TDO pins of the DP83924B when test operation is not required. This allows more rapid movement of test data to and from other testable devices in the system. ...
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Detailed Functional Description MANUFACTURER CODE IDCODE REGISTER BOUNDARY SCAN REGISTER (CELLS ARE ANY ONE OF BC1 THRU BC6) TDI BYPASS REGISTER GATED DR-CLOCK AND MODE SIGNALS RESET TMS TAP TCK CONTROLER TRST (Continued) CORE LOGIC DATA MUX PAD LOGIC ...
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... Register Map and Descriptions The following is an overall register map for the trans- ceiver/ENDEC. There are two groups of registers. The first group provides individual port control which configures and Table 11. DP83924B Register Map Accessible via the Management Interface Register Name Address 00H Port 1 Control/Status ...
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Register Descriptions Table 12. Port N Control/Status Register, addr = 00h - 03h (port 1 to port 4) D15 D14 D13 D12 D11 RST LPBK LNKPLS FDX JABE This register controls the various operating modes available for the transceiver ...
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Register Descriptions Table 13. Global Control/Mask Register, addr = 08h D15 : D14 D13 D12 RESV LNKJABINT AUTOSW TPIAUI HBEN ENPOLSW This register controls the various operating modes available for the transceiver and ENDEC functions. This register will affect ...
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Register Descriptions Table 14. Basic Mode Control/Status Register, addr 09 - 0CH (port 1 to port 4) D15 : D5 RESV This register controls the Auto-Negotiation functions and reports status for this port. Name Bit resv D15:5 Reserved ANCA ...
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Register Descriptions Table 16. Auto-Negotiation Advertisement Register, addr 0EH - 11H (port 1 to port 4) D15 D14 NPI RESV This register contains the advertised abilities of this device as they will be transmitted to it’s Link Partner during ...
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Register Descriptions Table 18. Auto-Negotiation Expansion Register, addr 16H - 19H (port 1 to port 4) D15:D5 RESV Name Bit resv D15:5 Reserved PDF D4 Parallel Detection Fault fault has been detected via parallel detection. 0 ...
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Application Information 5.1 Magnetics Specifications This section describes the required magnetics to be used with the 4TPHY. The external filter/transformer used in con- ventional twisted pair ports is now replaced by a trans- former. By integrating the transmit filter, ...
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Application Information Bypass for all other supplies should use a 0.01uF capaci- tor.Additional bypass for the VDD_TPI supplies should use a 1.0 uF capacitor. 5.3 LED interface considerations The 4TPHY will update the LEDs every 50 ms. LED data ...
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... Description: When connected to a 100M node that is configured into non Auto Negotiation mode, the scrambled Idles transmit- ted by this 100M node may cause the DP83924B to assert CRS. Since 100 Mbps scrambled idles can have waveforms passing the smart squelch levels and frequency require- ments, this expected. Also IEEE 802.3 Clause 14, Figure 14.6 shows that it’ ...
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User Information (Continued) 6.6 Link pulse template: Issue: The 924B will not link if the received NLPs have under- shoot exceeding 800 mV for a duration exceeding 80 ns. Description: IEEE 802.3 Clause 14, section 14.3.1.2.1 Figure 14-12 shows ...
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AC and DC Electrical Specifications Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Storage Temperature Range (T ) STG On Chip Power Dissipation ( Lead ...
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AC and DC Electrical Specifications 7.2 AC Switching Specifications 7.2.1 LED Interface Timing LED_CLK LED_DATA Symbol t LED Clock Duty Cycle 0 t LED Clock Cycle Time ...
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AC and DC Electrical Specifications 7.2.3 Management Interface Timing MDC MDIO (input) MDC MDIO (output) Symbol t Mdc Frequency 6 t Mdc Duty Cycle 7 t Mdio (input) Set Up to Mdc rising edge 8 t Mdio (input) Hold ...
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AC and DC Electrical Specifications 7.2.4 Twisted Pair Start of Transmit Packet TXC TXE t 12 TXD t 14 TXU± Symbol t TXE Setup time to TXC rising edge 11 t TXD Setup time to TXC rising edge 12 ...
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AC and DC Electrical Specifications 7.2.5 Twisted Pair Transmit End of Packet TXC TXE TXD TXU± ‘0’ Ending Pkt TXU± ‘1’ Ending Pkt Symbol t TXE Hold Time from TXC rising edg 19 t TXU End of Packet Hold ...
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AC and DC Electrical Specifications 7.2.6 Twisted Pair Start of Receive Packet RXI± CRS RXC RXD Symbol t Carrier Sense Turn On Delay (RXI to CRS Decoder Acquisition Time (Note Receive Data Valid ...
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AC and DC Electrical Specifications 7.2.7 Twisted Pair End of Receive Packet RXI± RXC CRS Symbol t Carrier Sense Turn Off Delay 27 t Number of RXCs after CRS low 28 1. This only applies when the GATERXC bit, ...
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AC and DC Electrical Specifications 7.2.10 Jabber Specifications TXE TXU± COL Symbol t Jabber Activation Time 33 t Jabber Deactivation Time 34 7.2.11 AUI Start of Packet Transmit Timing TXC TXE t 36 TXD t 38 TX± Symbol t ...
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AC and DC Electrical Specifications 7.2.12 AUI End of Packet Transmit Timing TXC 1 TXD TXE TX± ‘0’ Ending Pkt TX± ‘1’ Ending Pkt Symbol t TXE Hold Time from TXC rising edg End of Packet ...
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AC and DC Electrical Specifications 7.2.13 AUI Start of Packet Receive Timing RX± CRS t 44 RXC RXD Symbol t Carrier Sense Turn On Delay (RX to CRS Decoder Acquisition Time 44 t Receive Data ...
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AC and DC Electrical Specifications 7.2.15 AUI Collision Specifications CD± COL Symbol t Collision Turn On Delay (CD to COL Collision Turn Off Delay (CD to COL) 50 7.2.16 Network Test Loads TX+ TX- Figure 15. Attachment ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Natio nal reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted Plastic Quad Flat Pack (VCE) Order Number DP83924BVCE NS Package Number VCE100A 2. A critical component is any component of a life support ...