CY7C144-35JI Cypress Semiconductor Corporation., CY7C144-35JI Datasheet
CY7C144-35JI
Available stocks
Related parts for CY7C144-35JI
CY7C144-35JI Summary of contents
Page 1
... Semaphores included to permit software handshaking between ports • INT flag for port-to-port communication • Available in 68-pin PLCC, 64-pin and 80-pin TQFP • Pb-Free packages available Functional Description The CY7C144 and CY7C145 are high-speed CMOS and dual-port static RAMs. Various arbitration schemes Logic Block Diagram R ...
Page 2
... I/O 4R I/O 5R Notes: 3. I/O on the CY7C145 I/O on the CY7C145. 8L Document #: 38-06034 Rev. *C 68-Pin PLCC Top View CY7C144 2728 29 30 3132 64-Pin TQFP Top View CY7C144 CY7C144 CY7C145 INT L BUSY L GND M/S BUSY R INT INT L BUSY L GND M/S BUSY R INT Page [+] Feedback ...
Page 3
... Top View CY7C145 Description is set when right port writes location 1FFE and is cleared when left port reads L is set when left port writes location 1FFF and is cleared when right port reads R 7C144-15 7C144-25 7C144-35 7C145-15 7C145-25 7C145- 220 180 60 40 CY7C144 CY7C145 ...
Page 4
... V < 0.2V One Port Com’ > V – 0.2V Ind V > V – 0. < 0.2V, Active IN [7] Port Outputs MAX CY7C144 CY7C145 Ambient Temperature V CC ° ° 5V ± 10 +70 C ° ° −40 5V ± 10 +85 C 7C144-15 7C144-25 7C145-15 7C145-25 Min. Max. Min. Max. ...
Page 5
... CE > V – 0.2V Ind V > V – 0. < 0.2V, Active IN [7] Port Outputs MAX Test Conditions T = 25° MHz 5.0V CC CY7C144 CY7C145 7C144-35 7C144-55 7C145-35 7C145-55 Min. Max. Min. Max. Unit 2.4 2.4 V 0.4 0.4 V 2.2 2.2 V 0.8 0.8 V −10 −10 µ ...
Page 6
... Min. Max. Min. Max less than t and t HZCE LZCE CY7C144 CY7C145 893Ω OUTPUT 347Ω (c) Three-State Delay (Load 3) 7C144-35 7C144-55 7C145-35 7C145-55 Min. Max. Min. Max. Unit less than t . HZOE LZOE ...
Page 7
... For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform. 14. Test conditions used are Load 2. Document #: 38-06034 Rev. *C [9] (continued) 7C144-15 7C144-25 7C144-35 7C145-15 7C145-25 7C145-35 Min. Max. Min. Max. Min CY7C144 CY7C145 7C144-55 7C145-55 Max. Min. Max. Unit Page [+] Feedback ...
Page 8
... L, SEM = H when accessing RAM SEM = L when accessing semaphores. L 19. BUSY = HIGH for the writing port. 20 LOW Document #: 38-06034 Rev. *C [15, 16 [15, 17, 18] t ACE t DOE DATA VALID [19, 20 MATCH t PWE t SD VALID MATCH t WDD CY7C144 CY7C145 DATA VALID t HZCE t HZOE DDD VALID Page [+] Feedback ...
Page 9
... Data I/O pins enter high impedance when OE is held LOW during write. Document #: 38-06034 Rev. *C [21, 22, 23 SCE PWE t SD DATA VALID HIGH IMPEDANCE [21, 23, 24 SCE PWE DATAVALID t HZWE HIGH IMPEDANCE allow the I/O drivers to turn off and data to PWE HZWE SD CY7C144 CY7C145 LZOE LZWE Page [+] Feedback ...
Page 10
... SPS Document #: 38-06034 Rev. *C [25 VALID ADDRESS SOP t SD DATA VALID SWRD t SOP READ CYCLE MATCH t SPS MATCH = CE = HIGH L CY7C144 CY7C145 t OHA ACE DATA VALID OUT t DOE Page [+] Feedback ...
Page 11
... Switching Waveforms (continued) [20] Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATAIN ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Document #: 38-06034 Rev MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C144 CY7C145 BHA t BDD t DDD VALID Page [+] Feedback ...
Page 12
... BUSY will be asserted PS Document #: 38-06034 Rev. *C [29] ADDRESS MATCH BLC ADDRESS MATCH BLC [29 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C144 CY7C145 t BHC t BHC Page [+] Feedback ...
Page 13
... R 31 depends on which enable pin (CE or R/W INS INR L Document #: 38-06034 Rev WRITE 1FFF [30 [31] t INR t WC WRITE 1FFE [30 [31] t [31] INR ) is deasserted first asserted last. L CY7C144 CY7C145 t RC READ 1FFF t RC READ 1FFE Page [+] Feedback ...
Page 14
... Architecture The CY7C144/5 consists array of 8K words of 8/9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port ...
Page 15
... Right port is granted access to semaphore change. Left port is denied access 0 1 Left port obtains semaphore port accessing semaphore address 1 0 Right port obtains semaphore port accessing semaphore 0 1 Left port obtains semaphore port accessing semaphore CY7C144 CY7C145 Operation Right Port R INT 0− 1FFE ...
Page 16
... AMBIENT TEMPERATURE (°C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25.0 20.0 15.0 10 4. 25° 200 400 600 800 1000 CAPACITANCE (pF) CY7C144 CY7C145 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 200 160 120 25° 5.0 0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs ...
Page 17
... Ordering Information 8K x8 Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C144-15AC CY7C144-15AXC CY7C144-15JC CY7C144-15JXC CY7C144-15AI CY7C144-15AXI 25 CY7C144-25AC CY7C144-25AXC CY7C144-25JC CY7C144-25AI CY7C144-25JI 35 CY7C144-35AC CY7C144-35JC CY7C144-35AI CY7C144-35JI 55 CY7C144-55AC CY7C144-55AXC CY7C144-55JC CY7C144-55JXC CY7C144-55AI CY7C144-55JI 8K x9 Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C145-15AC CY7C145-15AXC CY7C145-15JC 25 CY7C145-25AC CY7C145-25JC CY7C145-25AI CY7C145-25JI 35 ...
Page 18
... Package Diagrams 64-Lead Thin Plastic Quad Flat Pack ( 1.4 mm) A65 64-Lead Pb-Free Thin Plastic Quad Flat Pack ( 1.4 mm) A65 Document #: 38-06034 Rev. *C CY7C144 CY7C145 51-85046-*B Page [+] Feedback ...
Page 19
... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 80-Pin Thin Plastic Quad Flat Pack A80 68-Lead Plastic Leaded Chip Carrier J81 CY7C144 CY7C145 51-85065-*B 51-85005-*A ...
Page 20
... Document History Page Document Title: CY7C145, CY7C144 8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Document Number: 38-06034 Issue Orig. of REV. ECN NO. Date Change ** 110175 09/29/01 *A 122285 12/27/02 *B 236752 See ECN *C 393320 See ECN Document #: 38-06034 Rev. *C Description of Change SZV ...