CY62148BLL-70SI Cypress Semiconductor Corporation., CY62148BLL-70SI Datasheet

no-image

CY62148BLL-70SI

Manufacturer Part Number
CY62148BLL-70SI
Description
512K x 8 Static RAM
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY62148BLL-70SI
Manufacturer:
CYPRESS
Quantity:
900
Part Number:
CY62148BLL-70SI
Manufacturer:
CY
Quantity:
1 000
Part Number:
CY62148BLL-70SI
Manufacturer:
CY
Quantity:
1 000
Part Number:
CY62148BLL-70SI
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Cypress Semiconductor Corporation
Document #: 38-05039 Rev. *C
Features
Functional Description
The CY62148B is a high-performance CMOS static RAM
organized as 512K words by 8 bits. Easy memory expansion
• High Speed: 70 ns
• 4.5V–5.5V operation
• Low active power
• Low standby current
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• CMOS for optimum speed/power
• Available in standard 32-lead (450-mil) SOIC, 32-lead
Logic Block Diagram
WE
CE
OE
— Typical active current: 2.5 mA @ f = 1 MHz
— Typical active current: 12.5 mA @ f = f
TSOP II and 32-lead Reverse TSOP II packages
A
A
A
A
A
A
A
A
A
A
12
14
16
17
0
1
4
5
6
7
INPUT BUFFER
512 K x 8
DECODER
COLUMN
ARRAY
POWER
DOWN
max
198 Champion Court
(70 ns)
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. This device
has an automatic power-down feature that reduces power
consumption by more than 99% when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH for read. Under these conditions, the
contents of the memory location specified by the address pins
will appear on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY62148B is available in a standard 32-pin 450-mil-wide
body width SOIC, 32-pin TSOP II, and 32-pin Reverse TSOP
II packages.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
4-Mbit (512K x 8) Static RAM
0
1
2
3
4
5
6
7
0
San Jose
through I/O
,
CA 95134-1709
7
) is then written into the location
CY62148B MoBL™
Pin Configuration
GND
GND
A
A
A
I/O
I/O
I/O
A
0
I/O
I/O
I/O
A
A
A
A
A
A
A
A
A
A
A
A
12
14
16
0
17
Revised August 2, 2006
A
A
A
A
A
A
A
through I/O
17
A
1
2
3
4
5
6
7
16
14
12
0
2
1
0
6
5
4
3
2
1
0
through A
0
1
2
7
4
3
2
1
16
15
14
13
12
11
10
9
8
7
6
5
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
Top View
Top View
TSOP II
TSOP II
Reverse
SOIC
18
7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
) are placed in a
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
).
408-943-2600
A
A
CE
I/O
I/O
I/O
I/O
I/O
I/O
V
A
WE
A
A
A
A
OE
I/O
I/O
OE
I/O
I/O
CE
A
A
I/O
A
A
A
A
A
V
CC
18
9
10
WE
15
13
8
11
6
10
11
9
8
13
18
15
cc
7
5
4
3
5
7
4
6
3
[+] Feedback

Related parts for CY62148BLL-70SI

CY62148BLL-70SI Summary of contents

Page 1

Features • High Speed • 4.5V–5.5V operation • Low active power — Typical active current: 2 MHz — Typical active current: 12 • Low standby current • Automatic ...

Page 2

... Product Portfolio V Range CC Product Min. Typ. CY62148BLL 4.5 V 5.0V Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage Relative GND........ – ...

Page 3

Capacitance Parameter Description C Input Capacitance IN C Output Capacitance OUT AC Test Loads and Waveforms R1 1800 Ω OUTPUT OUTPUT R2 100 pF 990 Ω INCLUDING INCLUDING JIG AND JIG AND SCOPE SCOPE (a) Note: 4. ...

Page 4

Switching Characteristics Over the Operating Range Parameter READ CYCLE t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE LOW to Data Valid ACE t OE LOW to Data ...

Page 5

Data Retention Characteristics Parameter Description V V for Data Retention Data Retention Current CCDR [4] t Chip Deselect to Data Retention Time CDR [9] t Operation Recovery Time R Data Retention Waveform Switching Waveforms ...

Page 6

Switching Waveforms (continued) [13] Write Cycle No. 1 (CE Controlled) ADDRESS DATA I/O Write Cycle No. 2 (WE Controlled, OE HIGH During Write) ADDRESS CE t HZCE DATA I/O NOTE 15 t HZOE ...

Page 7

... High Data Out Data High Z Ordering Information Speed Ordering Code (ns) 70 CY62148BLL-70SC CY62148BLL-70ZC CY62148BLL-70ZRC CY62148BLL-70SI CY62148BLL-70ZI CY62148BLL-70ZRI Please contact your local Cypress sales representative for availability of these parts Document #: 38-05039 Rev. *C [13, 14 SCE PWE t SD DATA VALID Mode 7 Power-Down Read Write ...

Page 8

Package Diagrams Document #: 38-05039 Rev. *C 32-lead (450 MIL) Molded SOIC (51-85081) CY62148B MoBL™ 51-85081-A Page [+] Feedback ...

Page 9

Package Diagrams (continued) 32-lead Thin Small Outline Package Type II (51-85095) All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05039 Rev. *C CY62148B MoBL™ 51-85095-** Page ...

Page 10

Package Diagrams (continued) 32-lead Reverse Thin Small Outline Package Type II (51-85138) Document #: 38-05039 Rev. *C © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the ...

Page 11

Document History Page Document Title: CY62148B 4-Mbit (512K x 8) Static RAM Document Number: 38-05039 Issue REV. ECN NO. Date ** 106833 05/01/01 *A 106970 07/16/01 *B 109766 10/09/01 *C 485639 See ECN Document #: 38-05039 Rev. *C Orig. of ...

Related keywords