ML6692CQ Micro Linear, ML6692CQ Datasheet
ML6692CQ
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ML6692CQ Summary of contents
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GENERAL DESCRIPTION The ML6692 implements the complete physical layer of the Fast Ethernet 100BASE-TX standard. The ML6692 interfaces to the controller through the standard-compliant Media Independent Interface (MII). The ML6692 functionality includes auto-negotiation, 4B/5B encoding/ decoding, Stream Cipher scrambling/descrambling, 125MHz ...
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ML6692 PIN CONFIGURATION DGND1 DGND2 DGND3 2 ML6692 52-Pin PLCC (Q52 TXER 8 TXCLK 9 RXD3 10 11 RXD2 12 DVCC1 13 RXD1 14 15 RXD0 16 ...
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PIN CONFIGURATION TXCLK 1 RXD3 2 DGND1A 3 DGND1B 4 RXD2 5 DVCC1A 6 DVCC1B 7 RXD1 8 DGND2A 9 DGND2B 10 RXD0 11 RXCLK 12 CRS 13 COL 14 DGND3A 15 DGND3B 16 ML6692 64-Pin TQFP (H64-10 ...
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ML6692 PIN DESCRIPTION (Pin Numbers for TQFP package in parentheses) PIN NAME FUNCTION 1 (56) TXCLKIN Transmit clock TTL input. This 25MHz clock is the frequency reference for the internal transmit PLL clock multiplier. This pin should be driven by ...
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PIN DESCRIPTION (Continued) PIN NAME FUNCTION 25 (21) MDIO MII Management Interface data TTL input/output. Serial data are written to and read from the ML6692’s management registers through this I/O pin. Input data is sampled on the rising edge of ...
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ML6692 PIN DESCRIPTION (Continued) 37 (36) RTSET Transmit level bias resistor input. An external 2.49kW, 1% resistor connected between RTSET and AGND3 sets a precision constant bias current for the twisted pair transmit level. 38 (37, 38) AGND3 Analog ground. ...
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ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. V Supply Voltage Range .................. GND –0. ...
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ML6692 DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TRANSMITTER (Continuied) X TPOUTP/N Differential Output ERR Current Error X TPOUTP/N 100BASE-X Output CMP100 Current Compliance Error V TPOUTP/N 10BASE-T Output OCM10 Voltage Compliance Range V 10BTTXNN/P Input ICM10 Common-Mode Voltage Range POWER SUPPLY ...
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AC ELECTRICAL CHARACTERISTICS Over full range of operating conditions unless otherwise specified SYMBOL PARAMETER RECEIVER V TPINP/N Input Common-Mode ICM Voltage (CMREF) TRANSMITTER (NOTE 3) t TPOUTP-TPOUTN Differential TR/F Rise/Fall Time t TPOUTP-TPOUTN Differential TM Rise/Fall Time Mismatch t TPOUTP-TPOUTN ...
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ML6692 AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER MDC-MDIO (MII MANAGEMENT INTERFACE) t Write Setup Time, MDIO Data SPWS Valid to MDC Rising Edge 1.4V Point t Write Hold Time, MDIO Data SPWH Valid After MDC Rising Edge 1.4V Point t Read ...
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V CC TPOUTP R LP 200 R LP 200 TPOUTN TXCLKIN TXCLK TXD<3:0> TXER TXEN t TPS Figure 2. MII Transmit Timing RXCLK RXD<3:0> RXER RXDV t RCS Figure 3. MII Receive Timing MDC MDIO t SPWS Figure 4. MII ...
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ML6692 FUNCTIONAL DESCRIPTION TRANSMIT SECTION 100BASE-TX Operation The transmitter includes everything necessary to accept 4-bit data nibbles clocked in at 25MHz at the MII and output scrambled, 5-bit encoded MLT-3 signals into twisted pair at 100Mbps. The on-chip transmit PLL ...
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FUNCTIONAL DESCRIPTION does not detect or correct errors in the polarity of fast or normal link pulses. USING THE ML6692 WITH AUTOMATIC LINK CONFIGURATION The ML6692 supports automated link protocol negotiation and configuration. In the ML6692, the auto negotiation state ...
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ML6692 INITIALIZATION INTERFACE The ML6692 has an Initialization Interface to allow register programming that is not supported by the MII Management Interface. The intitialization data is loaded at power-up and cannot be changed afterwards. The pin EDIN selects one of ...
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INITIALIZATION INTERFACE REGISTER BIT(S) NAME I.15 PHY A4 I.14 PHY A3 I.13 PHY A2 I.12 PHY A1 I.11 PHY A0 I.10 10HDUP I.9 10FDUP I.8 100T4 I.7 ISODIS I.6 REPEATER I.5–I.0 Not used Note: Bits I<10:8> are the values for ...
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ML6692 MII MANAGEMENT INTERFACE REGISTERS BIT(S) NAME 1.15 100BASE-T4 1.14 100BASE-TX full duplex 1.13 100BASE-TX half duplex 1.12 10Mb/s full duplex 1.11 10BASE-T (half duplex) 1.10 – 1.6 Not Used 1.5 Auto negotiation compl. 1.4 Not Used 1.3 Auto negotiation ...
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MII MANAGEMENT INTERFACE REGISTERS BIT(S) NAME 5.15 Next Page 5.14 Acknowledge 5.13 Remote fault 5.12-5.10 Reserved 5.9 100BASE-T4 capability 5.8 100BASE-TX full duplex 5.7 100BASE-TX 5.6 10BASE-T full duplex 5.5 10BASE-T 5.4-5.1 Selector field 5.0 Selector field BIT(S) NAME 6.15-6.5 ...
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ML6692 VCC GND VCC TX+ FD GND LTP TXC RPOL TXD COL TXE CS0 RTX INTERFACE 7-WIRE 18 DUPLEX 10BTTXINN 10BTTXINP 10BTRCV 10BTLINKEN AVCC1 TXCLKIN AGND1 TXD3 TXD2 TXD1 TXD0 TXEN Table 8. 10/100 BASE-T Application Circuit ECLK SEL10FD/ SEL10HD ...
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ML6692 SCHEMATIC Figure 8 shows a general 10BASE-T and 100BASE-TX design using the ML2653 (10BASE-T PHY) and ML6692 (100BASE-TX PHY). The inductors L1 and L2 are for the purpose of improving return loss. Capacitor C7 is recommended. It decouples some ...
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ML6692 PHYSICAL DIMENSIONS 0.785 - 0.795 (19.94 - 20.19) 0.750 - 0.754 (19.05 - 19.15) 1 PIN 1 ID 0.042 - 0.048 (1.07 - 1.22 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.013 - 0.021 ...
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... ORDERING INFORMATION PART NUMBER ML6692CH ML6692CQ Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted by this document ...