ISPLSI2064VE-135LT44I Lattice Semiconductor Corp., ISPLSI2064VE-135LT44I Datasheet
ISPLSI2064VE-135LT44I
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ISPLSI2064VE-135LT44I Summary of contents
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... Interconnectivity • LEAD-FREE PACKAGE OPTIONS Copyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
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Functional Block Diagram Figure 1. ispLSI 2064VE Functional Block Diagram (64-I/O and 32-I/O Versions) Input Bus Output Routing Pool (ORP) Megablock I I/O 2 I/O 3 I/O 4 I/O 5 Global Routing Pool ...
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Absolute Maximum Ratings Supply Voltage V cc ................................................... Input Voltage Applied ..................................... -0.5 to +5.6V Off-State Output Voltage Applied .................. -0.5 to +5.6V Storage Temperature ..................................... -65 to 150°C Case Temp. with Power Applied .................... -55 to 125°C Max. Junction ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see Figure 2) TEST CONDITION A Active ...
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External Timing Parameters 3 TEST PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay pd2 f max A 3 Clock Frequency with Internal Feedback f – 4 Clock Frequency ...
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External Timing Parameters 3 TEST PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay pd2 Clock Frequency with Internal Feedback max f – 4 Clock Frequency ...
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Internal Timing Parameters 2 PARAMETER # Inputs Input Buffer Delay t 21 Dedicated Input Delay din GRP t grp 22 GRP Delay GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...
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Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...
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Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset Y0,1,2 GOE 0 Derivations of su, h and co from the Product Term Clock Logic + Reg ...
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Power Consumption Power consumption in the ispLSI 2064VE device de- pends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax I CC can ...
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Signal Descriptions Signal Name RESET Active Low (0) Reset pin resets all the registers in the device. GOE 0, GOE1 Global Output Enable input pins. Y0, Y1, Y2 Dedicated Clock Input – These clock inputs are connected to one ...
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Signal Locations ...
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Signal Configuration ispLSI 2064VE 100-Ball caBGA Signal Diagram (0.8mm Ball Pitch/10.0 x 10.0mm Body Size I/O I I/O I I/O I I/O I ...
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Pin Configuration ispLSI 2064VE 100-Pin TQFP Pinout Diagram (0.5mm Lead Pitch/14.0 x 14.0mm Body Size ...
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Pin Configuration ispLSI 2064VE 44-Pin PLCC Pinout Diagram (0.05in Lead Pitch/0.65 x 0.65in Body Size) I/O 28 I/O 29 I/O 30 I/O 31 GOE1/Y0 VCC BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 Pin Configuration ispLSI 2064VE 44-Pin TQFP ...
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Part Number Description ispLSI 2064VE XXX X XXXXX Device Family Device Number Speed f 280 = 280 MHz max f 200 = 200 MHz max f 135 = 135 MHz max f 100 = 100 MHz max ispLSI 2064VE Ordering ...
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Ordering Information (Cont.) Lead-Free Packaging FAMILY fmax (MHz) tpd (ns) 280 3.5 280 3.5 200 4.5 200 4.5 ispLSI 135 7.5 135 7.5 100 10 100 10 FAMILY fmax (MHz) tpd (ns) 135 7.5 ispLSI 135 7.5 Specifications ...