RTL8201BL REALTEK, RTL8201BL Datasheet

no-image

RTL8201BL

Manufacturer Part Number
RTL8201BL
Description
Manufacturer
REALTEK
Datasheet
1. Features........................................................................... 2
2. General Description ....................................................... 2
3. Block Diagram................................................................ 3
4. Pin Assignments ............................................................. 4
5. Pin Description ............................................................... 5
6. Register Descriptions ..................................................... 8
7. Functional Description ................................................ 14
2002-03-29
5.1 100 Mbps MII & PCS Interface ................................ 5
5.2 SNI (Serial Network Interface): 10Mbps only .......... 5
5.3 Clock Interface .......................................................... 6
5.4 100Mbps Network Interface...................................... 6
5.5 Device Configuration Interface ................................. 6
5.6 LED Interface/PHY Address Config......................... 7
5.7 Reset and other pins .................................................. 7
5.8 Power and Ground pins ............................................. 7
6.1 Register 0 Basic Mode Control Register ................... 8
6.2 Register 1 Basic Mode Status Register ..................... 9
6.3. Register 2 PHY Identifier Register 1 ....................... 9
6.4. Register 3 PHY Identifier Register 2 ....................... 9
6.5.
Register(ANAR) ........................................................... 10
6.6 Register 5 Auto-Negotiation Link Partner Ability
Register(ANLPAR) ....................................................... 10
6.7
Register(ANER)............................................................ 11
6.8 Register 16 Nway Setup Register(NSR) ................. 11
6.9 Register 17 Loopback, Bypass, Receiver Error Mask
Register(LBREMR) ...................................................... 12
6.10 Register 18 RX_ER Counter(REC)....................... 12
6.11 Register 19 10Mbps Network Interface Configuration Register... 12
6.12 Register 20 PHY 1_1 Register .............................. 13
6.13 Register 21 PHY 1_2 Register .............................. 13
6.14 Register 22 PHY 2 Register .................................. 13
6.15 Register 23 Twister_1 Register ............................. 13
6.16 Register 24 Twister_2 Register ............................. 13
6.17 Register 25 Test Register....................................... 13
Register
Register
FAST ETHERNET PHYCEIVER
4
6
Auto-negotiation
REALTEK SINGLE CHIP
Auto-negotiation
SINGLE PORT 10/100M
Advertisement
RTL8201BL
Expansion
1
8. Electrical Characteristics ............................................ 21
9. Mechanical Dimensions............................................... 28
10. Revision History......................................................... 29
7.1 MII and Management Interface............................... 14
7.2 Auto-negotiation and Parallel Detection ................. 15
7.3 Flow control support ............................................... 16
7.4 Hardware Configuration and Auto-negotiation................. 16
7.5 LED and PHY Address Configuration.................... 17
7.6 Serial Network Interface ......................................... 17
7.7 Power Down, Link Down, Power Saving, and Isolation Modes... 18
7.8 Media Interface ....................................................... 18
7.9 Repeater Mode Operation ....................................... 19
7.10 Reset, and Transmit Bias(RTSET) ........................ 19
7.11 3.3V power supply and voltage conversion circuit 19
7.12 Far End Fault Indication (FEFI)............................ 20
8.1 D.C. Characteristics ................................................ 21
8.2 A.C. Characteristics ................................................ 22
8.3 Crystal and Transformer Specifications .................. 27
7.1.1 Data Transition ................................................ 14
7.1.2 Serial Management.......................................... 14
7.8.1 100Base TX..................................................... 18
7.8.2 100Base-FX Fiber Mode Operation ................ 18
7.8.3 10Base Tx/Rx .................................................. 19
8.1.1. Absolute Maximum Ratings........................... 21
8.1.2. Operating Conditions ..................................... 21
8.1.3. Power Dissipation........................................... 21
8.1.4 Supply Voltage: Vcc ........................................ 21
8.2.1 MII Timing of Transmission Cycle ................. 22
8.2.2 MII Timing of Reception Cycle ...................... 23
8.2.3 SNI Timing of Transmission Cycle ................. 24
8.2.4 SNI Timing of Reception Cycle ...................... 25
8.2.5 MDC/MDIO timing......................................... 26
8.2.6 Transmission Without Collision ...................... 26
8.2.7 Reception Without Error ................................. 26
8.3.1 Crystal Specifications...................................... 27
8.3.2 Transformer Specifications.............................. 27
RTL8201BL
Rev.1.2

Related parts for RTL8201BL

RTL8201BL Summary of contents

Page 1

... SNI Timing of Transmission Cycle ................. 24 8.2.4 SNI Timing of Reception Cycle ...................... 25 8.2.5 MDC/MDIO timing......................................... 26 8.2.6 Transmission Without Collision ...................... 26 8.2.7 Reception Without Error ................................. 26 8.3 Crystal and Transformer Specifications .................. 27 8.3.1 Crystal Specifications...................................... 27 8.3.2 Transformer Specifications.............................. 27 9. Mechanical Dimensions............................................... 28 10. Revision History......................................................... 29 1 RTL8201BL Rev.1.2 ...

Page 2

... Features The Realtek RTL8201BL is a Fast Ethernet Phyceiver with selectable MII or SNI interface to the MAC chip. It provides the following features: Supports MII/7-wire Interface) interface Supports 10/100Mbps operation Supports half/full duplex operation Support of twisted pair or Fiber mode output IEEE 802.3/802.3u compliant Supports IEEE 802.3u clause 28 auto negotiation ...

Page 3

... Parrallel to Serial Variable Current Baseline wander Correction 3 Level MLT-3 Comparator to NRZI ck Slave PLL data Control Voltage 3 RTL8201BL Descrambler Link pulse 10M Output waveform shaping Receive low pass filter 3 Level Driver Peak Detect Adaptive Equalizer Master PPL 25M RXD RXC 25M TXD ...

Page 4

... Pin Assignments 37. ANE 38. DUPLEX 39. SPEED 40. RPTR 41. LDPS 42. RESETB 43. ISOLATE 44. M II/SNIB /RTT3 45. DGND 46. X1 47. X2 48. DVDD33 2002-03-29 RTL8201BL 4 RTL8201BL 24. RXER /FXEN 23. CRS 22. RXDV 21. RXD0 20. RXD1 19. RXD2 18. RXD3 17. DGND 16. RXC 15. LED4/ PH YAD4 14. DVDD33 13. LED3/ PH YAD3 Rev.1.2 ...

Page 5

... Management Data Input/Output: This pin provides the bi-directional signal used to transfer management information. Collision Detect Received Serial Data Carrier Sense Receive Clock: Resolved from received data Transmit Serial Data Transmit Clock: Generate by PHY Transmit Enable: For MAC to indicate transmit operation 5 RTL8201BL Description Description Rev.1.2 ...

Page 6

... GND or VCC. Refer to Section 7.7 for more information. This pin is latched to input during a power on or reset condition. Pull high to set the RTL8201BL into MII mode operation. Set low for SNI mode. This pin can be directly connected to GND or VCC. In test mode, this pin is an output pin and ...

Page 7

... LED Interface/PHY Address Config These five pins are latched into the RTL8201BL during power up reset to configure PHY address [0:4] used for MII management register interface. And then, in normal operation after initial reset, they are used as driving pins for status indication LED. The driving polarity, active low or active high, is determined by each latched status of the PHY address [4:0] during power-up reset ...

Page 8

... Register Descriptions This section will describe definitions and usage for each of the registers available in the RTL8201BL. 6.1 Register 0 Basic Mode Control Register Address Name Description/Usage 0:<15> Reset This bit sets the status and control registers of the PHY in a default state. This bit is self-clearing. ...

Page 9

... Reserved 1:<6> MF Preamble The RTL8201BL will accept management frames Suppression with preamble suppressed. The RTL8201BL accepts management frames without preamble. A Minimum of 32 preamble bits are required for the first SMI read/write transaction after reset. One idle bit is required between any two management transactions as per IEEE802 ...

Page 10

... NOT supported by Link partner 5:<9> 100Base-T4 is supported by link partner 0 = 100Base-T4 not supported by link partner 5:<8> TXFD 1 = 100Base-TX full duplex is supported by link partner 0 = 100Base-TX full duplex not supported by link partner 2002-03-29 Description/Usage Auto-Negotiation Description/Usage 10 RTL8201BL Default/Attribute <00001>, RW Link Partner Ability ...

Page 11

... Nway to loopback mode. 16:<8;3> Reserved 16:<2> FLAGABD 1 = Auto-neg experienced ability detect state 16:<1> FLAGPDF 1 = Auto-neg experienced parallel detection fault state 16:<0> FLAGLSC 1 = Auto-neg experienced link status check state 2002-03-29 Description/Usage link partner’s ability register Description/Usage 11 RTL8201BL <00000>, RO Default/Attribute Default/Attribute Rev.1.2 ...

Page 12

... Register 17 Loopback, Bypass, Receiver Error Mask Register(LBREMR) Address Name 17:<15> RPTR Set put the RTL8201BL into repeater mode 17:<14> BP_4B5B Assertion of this bit allows bypassing of the 4B/5B & 5B/4B encoder. 17:<13> BP_SCR Assertion of this bit allows bypassing of the scrambler/descrambler. 17:<12> ...

Page 13

... Test Reserved for internal testing 25<1> LINK10 1: Link established in 10Base link established in 10Base 25<0> LINK100 1: Link established in 100Base link established in 100Base 2002-03-29 Description/Usage Description/Usage Description/Usage Description/Usage Description/Usage Description/Usage 13 RTL8201BL Default/Attribute R/W Default/Attribute R/W Default/Attribute RO R/W Default/Attribute R/W Default/Attribute R/W Default/ Attribute R ...

Page 14

... MII and Management Interface 7.1.1 Data Transition To set the RTL8201BL for MII mode operation, pull MII/SNIB pin high and properly set the ANE, SPEED, and DUPLEX pins. The MII (Media Independent Interface 18-signal interface which is described in IEEE 802.3u supplying a standard interface between PHY and MAC layer. This interface operates in two frequencies – ...

Page 15

... FLP and wait for the link partner to respond. If the RTL8201BL receives FPL, then the auto-negotiation process will go on receives NLP, then the RTL8201BL will change to 10Mbps and half duplex mode receives a 100Mbps IDLE pattern, it will change to 100Mbps and half duplex mode. ...

Page 16

... RPTR pin: Pull high to set the RTL8201BL into repeater mode. This pin is pulled low by default. Please refer to the section covering Repeater mode operation. 3) LDPS pin: Pull high to set the RTL8201BL into LDPS mode. This pin is pulled low by default. Please refer to the section covering Power Down mode and Link Down Power Saving. ...

Page 17

... The RTL8201BL also supports the traditional 7-wire serial interface to cooperate with legacy MACs or embedded systems. To setup for this mode of operation, pull the MII/SNIB pin low and by doing so, the RTL8201BL will ignore the setup of the ANE and SPEED pins. In this mode, the RTL8201BL will set the default to work in 10Mbps and Half-duplex mode. But the RTL8201BL may also support full duplex mode operation if the DUPLEX pin has been pulled high ...

Page 18

... The digital functions in this mode are still available which allows reacquisition of analog functions. 2) LDPS mode: Setting bit 12 of register pulling the LDPS pin high will put the RTL8201BL into LDPS (Link Down Power Saving) mode. In LDPS mode, the RTL8201BL will detect the link status to decide whether or not to turn off the transmit function ...

Page 19

... Reset, and Transmit Bias(RTSET) The RTL8201BL can be reset by pulling the RESETB pin low for about 10ms, then pulling the pin high. It can also be reset by setting bit 15 of register and then setting it back to 0. Reset will clear the registers and re-initialize them, and the media interface will first disconnect and restart the auto-negotiation/parallel detection process ...

Page 20

... FEFI is an alternative in-band signaling method which is composed of 84 consecutive ‘1’ followed by one ‘0’. From the point of view of the RTL8201BL, when this pattern is detected three times, Reg.1.4 is set, which means the transmit path (the Remote side’s receive path) has a problem. On the other hand, the incoming signal failure in causing a link OK will force the RTL8201BL to start sending this pattern, which in turn causes the remote side to detect a Far-End-Fault ...

Page 21

... Minimum 3.0V 0°C Condition Minimum 0.5*Vcc -0.5V IOH=-8mA 0.9*Vcc IOL=8mA Vout=Vcc or -10uA GND Vin=Vcc or -1.0uA GND Iout=0mA Vdd-1.16V Vdd-1.81V Vdd-1.02V 21 RTL8201BL Typical Maximum 3.3V 3.6V 125°C Typical Maximum 3.3V 3.6V 70°C Total Current Consumption Typical Maximum Vcc+0.5V ...

Page 22

... RTL8201BL Typical Maximum 20 26 200 260 20 26 200 260 40 400 400 160 2000 70 140 400 100 170 IH(min) V IL(max IH(min) ...

Page 23

... Minimum 100Mbps 14 10Mbps 140 100Mbps 14 10Mbps 140 100Mbps 10Mbps 100Mbps 10 10Mbps 6 100Mbps 10 10Mbps 6 100Mbps 10Mbps 100Mbps 10Mbps 100Mbps 10Mbps 100Mbps 10Mbps RTL8201BL Typical Maximum Unit 200 260 200 260 400 130 ns 600 ns 240 ns 600 ns 150 ns 3200 ns 120 ns 800 ns V IH(min) ...

Page 24

... TXCLK low pulse width 2 t TXCLK period 3 t TXEN, TXD0 setup to TXCLK rising edge 4 t TXEN, TXD0 hold after TXCLK rising edge 5 t Transmit latency 8 TXCLK TXEN TXCLK TXEN TXD0 TPTX+- 2002-03-29 Minimum TXD0 RTL8201BL Typical Maximum 120 IH(min) V IL(max IH(min) V IL(max Unit Rev.1.2 ...

Page 25

... RXD0 hold after RXCLK rising edge 5 t Receive frame to CRS high 6 t End of receive frame to CRS low 7 t Decoder acquisition time 8 RXCLK RXD0 RXCLK RXD0 t 6 CRS TPRX+- 2002-03-29 Minimum Typical RTL8201BL Maximum Unit ns ns 120 160 ns 600 1800 ns V IH(min) V IL(max) V IH(min) V IL(max Rev.1.2 ...

Page 26

... Shown is an example transfer of a packet from MAC to PHY. 8.2.7 Reception Without Error Shown is an example of transfer of a packet from PHY to MAC 2002-03-29 Minimum 160 160 400 MDC MDIO STA t 6 MDIO 26 Typical Maximum 300 IH(min) V IL(max IH(min) V IL(max) V IH(min) V IL(max) RTL8201BL Unit Rev.1.2 ...

Page 27

... DC resistance (max) 2002-03-29 25.000 MHz Base wave ±50 ppm ±50 ppm -10℃ ~ +70℃ 30 ohm Max. 0 Max. Mega ohm Min./DC 100V Saunders 250A ±0.0003% Transmit End 1:1 CT 350 uH @ 8mA 0.05-0. 0.4 ohm 27 RTL8201BL Range Receive End 1:1 350 uH @ 8mA 0.05-0. 0.4 ohm Rev.1.2 ...

Page 28

... PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm 0.50 BSC 0.40 0.60 0.80 APPROVE 1.00 REF 0° 3.5° 9° CHECK 0° 12° TYP 12° TYP REALTEK SEMI-CONDUCTOR CORP. 28 RTL8201BL TITLE: 48LD LQFP ( 7x7x1.4mm) LEADFRAME MATERIAL: DOC. NO. VERSION 1 PAGE OF DWG NO. SS048 - P1 DATE Sept. 25.2000 Rev.1.2 ...

Page 29

... PWFBOUT and PWFBIN.” ACR; MII; SNI Modify 1. Modify net label: Pin32: AVDD25 Pin8: DVDD25 2. Add pull-high resistor for MDIO 3. Modify ResetB circuit to meet wake-on-lan application 29 RTL8201BL Text Text PWFBOUT PWFBIN Rev.1.2 ...

Related keywords