RTL8208B REALTEK, RTL8208B Datasheet

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RTL8208B

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RTL8208B
Description
Manufacturer
REALTEK
Datasheet

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RTL8208B-LF
RTL8208BF-LF
SINGLE-CHIP OCTAL 10/100BASE-TX/FX
PHY TRANSCEIVER
DATASHEET
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
Track ID: JATR-1076-21
22 September 2006
Rev. 1.3

Related parts for RTL8208B

RTL8208B Summary of contents

Page 1

... RTL8208B-LF RTL8208BF-LF SINGLE-CHIP OCTAL 10/100BASE-TX/FX PHY TRANSCEIVER DATASHEET Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www.realtek.com.tw Rev. 1.3 22 September 2006 Track ID: JATR-1076-21 ...

Page 2

... Summary Draft release. First approved release. Change bias resistor value to 2K ohm in Figure 22 on page 49. 1. Add Fiber Application information for RTL8208BF-LF. 2. Modify Figure 1, page 3, and Figure 2, page 4. 3. Modify Table 1. Pin Assignments, on page 5. 4. Modify Table 5. RMII/SMII/SS-SMII Pins, page 7. 5. Corrected SMI Clock frequency from 25MHz to 2.5MHz (Table 6, page 9, section 7 ...

Page 3

... 30: C ORT EGISTER ABLE 7. FUNCTION DESCRIPTION ............................................................................................................................................26 7.1. G ...................................................................................................................................................................26 ENERAL 7.1.1. SMI (Serial Management Interface) .....................................................................................................................26 7.1.2. Port Pair-Loop Back Mode (PP-LPBK) (RTL8208BF-LF Only) .........................................................................26 7.1.3. PHY Address.........................................................................................................................................................27 7.1.4. Auto-Negotiation ..................................................................................................................................................27 7.1.5. Full-Duplex Flow Control ....................................................................................................................................27 7. NITIALIZATION AND ETUP 7.2.1. Reset .....................................................................................................................................................................28 7.2.2. Setup and Configuration.......................................................................................................................................28 7 ...

Page 4

... ASELINE ANDER OMPENSATION 7.6. 100B -FX (RTL8208BF-LF O ASE 7.6.1. Transmit Function ................................................................................................................................................32 7.6.2. Receive Function ..................................................................................................................................................32 7.6.3. Link Monitor.........................................................................................................................................................32 7.6.4. Far-End-Fault-Indication.....................................................................................................................................32 7.6.5. Reduced Fiber Interface .......................................................................................................................................33 7.7. RMII/SMII/SS-SMII .................................................................................................................................................33 7.7.1. RMII (Reduced MII) .............................................................................................................................................34 7.7.2. SMII (Serial MII)..................................................................................................................................................35 7.7.3. SS-SMII (Source Synchronous -Serial MII) ..........................................................................................................36 7. OWER AVING AND OWER 7 ...

Page 5

... I )......................................................................................................................9 NTERFACE ............................................................................................................................................. ...................................................................................................................18 EGISTER 2 R ...................................................................................................................18 EGISTER A ....................................................................................................19 DVERTISEMENT .........................................................................................21 INK ARTNER BILITY E .............................................................................................................23 XPANSION ........................................................................................24 ESTER ONTROL EGISTER 1.........................................................................................24 ESTER ONTROL EGISTER S R ...........................................................................................................25 TATUS EGISTER ..........................................................................................................................................26 (PP-LPBK) .................................................................................................................26 ODE ......................................................................................................................................32 ......................................................................................................................................33 ....................................................................................................................................33 .......................................................................................................................................35 .................................................................................................................................36 T 2SB1182 ...................................................................................................47 RANSISTOR ..................................................................................................................................50 ............................................................................................................................52 .............................................................................................................................................54 ..............................................................................................................................................55 ...........................................................................................................................................55 ........................................................................................................................................56 .....................................................................................................................................57 ANGE ..............................................................................................................................................57 ............................................................................................................................................59 v RTL8208B-LF/RTL8208BF-LF Datasheet Track ID: JATR-1076-21 Rev. 1.3 ...

Page 6

... (RTL8208B-LF) .............................................................................................................................3 IGURE IN SSIGNMENTS (RTL8208BF-LF)...........................................................................................................................4 IGURE IN SSIGNMENTS F 3. RMII S D IGURE IGNAL IAGRAM F 4. SMII S D IGURE IGNAL IAGRAM F 5. SMII R ........................................................................................................................................................35 IGURE ECEPTION F 6. SMII T ..................................................................................................................................................36 IGURE RANSMISSION F 7. SS-SMII S D IGURE IGNAL IAGRAM F 8. SS-SMII R ...................................................................................................................................................37 IGURE ECEPTION F 9. SS-SMII T ...

Page 7

... Ethernet transceivers implemented in 0.18µm CMOS technology. They are currently the world’s smallest Octal-PHY chip package. Realtek patented removal of traditional SD pins in 100Base-FX (RTL8208BF-LF only) allow us to obtain a lower pin- count. Flexible hardware settings are provided to configure the various operating modes of the chip. ...

Page 8

... Octal PHY for Fast Ethernet switch with twisted pair interface and fiber capability Single-Chip Octal 10/100-TX/FX PHY Transceiver RTL8208B-LF/RTL8208BF-LF Supports Port-Pair Loopback mode (PP- LPBK mode, RTL8208BF-LF only) Supports two power reduction methods: Power saving mode (cable detection) Power down mode Power-on auto reset function eliminates the ...

Page 9

... Note: Signal type codes are listed in section 5 Pin Descriptions, page 6. 4.2. Lead (Pb)-Free Package Identification Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in Figure 1. Single-Chip Octal 10/100-TX/FX PHY Transceiver Figure 1. Pin Assignments (RTL8208B-LF) 3 RTL8208B-LF/RTL8208BF-LF Datasheet Track ID: JATR-1076-21 Rev. 1.3 ...

Page 10

... Note: Signal type codes are listed in section 5 Pin Descriptions, page 6. 4.4. Lead (Pb)-Free Package Identification Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in Figure 2. Single-Chip Octal 10/100-TX/FX PHY Transceiver Figure 2. Pin Assignments (RTL8208BF-LF) 4 RTL8208B-LF/RTL8208BF-LF Datasheet Track ID: JATR-1076-21 Rev. 1.3 ...

Page 11

... I/O,Pd VDDA 8mA I/O,Pd XI 8mA I/O, I,ND VSSA - I,ND DTEST1 - I,ND VSSA - DP VDDA - DG IBREF 8mA I/O,Pd VCTRL 8mA I/O,Pd VDDAH 8mA I/O,Pu VDDA 5 RTL8208B-LF/RTL8208BF-LF Datasheet Pin# Type 65 I,ND 66 I, I/O,Pd 71 I/O,Pu 72 I/O,Pu 73 I,ND 74 I,ND 75 I,ND 76 I/O,Pd 77 I/O,Pd 78 I/O,ND 79 I,ND ...

Page 12

... Pin Descriptions In order to reduce pin count, and therefore size and cost, some pins have multiple functions. In such cases the functions are separated with a “ / ” symbol. For the RTL8208B-LF refer to Figure 1, page 3; for the RTL8208BF-LF refer to Figure 2, page 4, for a graphical representation. ...

Page 13

... SS-SMII: TXD0 behaves as SMII except synchronous to TX_CLK instead of REFCLK and inputs a new 10-bit segment starting with TX_SYNC instead of SYNC. I Transmit Data Input (bit 1). RMII: TXD1 and TXD0 are the input di-bits synchronously to REFCLK. SMII/SS-SMII: The I/O pin of TX_EN should not be used. 7 RTL8208B-LF/RTL8208BF-LF Datasheet Track ID: JATR-1076-21 Rev. 1.3 ...

Page 14

... All pins driver capacity = 8mA, except pin 78 (16mA Sync/Transmit Synchronous. (Pd) SMII: SYNC is a sync signal used to delimit a 10-bit segment of RXD0 and TXD0 for all ports. SS-SMII: TX_SYNC is a sync signal used to delimit the 10-bit segment of TXD0 for all ports. 8 RTL8208B-LF/RTL8208BF-LF Datasheet Track ID: JATR-1076-21 Rev. 1.3 ...

Page 15

... IEEE802.3u). The MAC controller access of the MII registers should be delayed at least 700µs after completion of the reset because of the internal reset operation of the RTL8208B(F)-LF. Pin driver capacity = 8mA. 112 I, (Pd) Management Data Clock 2.5MHz clock sourced by MAC to sample MDIO ...

Page 16

... Forces the flow control capability of Reg.4.10 and Reg.5.10 upon power-on reset. 1: With flow control ability in 100Base-FX 0: Without flow control ability in 100Base-FX Note: RTL8208BF-LF only. I/O, (Pd) Twisted Pair Asymmetric Pause capability (default =0). Sets the Asymmetric Flow control ability of Reg.4.11 for UTP ports upon power-on reset ...

Page 17

... LEDSEL 1’b1: Scan LED 1’b0: Serial LED I/O, LEDMODE[1:0] (default = 00). (Pd, Pd) When using the RTL8208B(F)-LF LED solution , we recommend using an external resister to pull high or pull low. In Serial LED, LEDMODE[1:0] controls the forms of serial LED status. LEDMODE Mode 2’b00 3-bit serial stream 2’b01 2-bit serial stream 2’ ...

Page 18

... Table 9. Test Pins Type Description I/O, Enable analog parameter write (default =0). (Pd) 1: Enable analog parameter write operation 0: Disable analog parameter write operation I, Reserved for internal use. (Pd) Must be left floating. I/O Reserved for internal use. Must be left floating. 12 RTL8208B-LF/RTL8208BF-LF Datasheet Track ID: JATR-1076-21 Rev. 1.3 ...

Page 19

... Status Register. 2 PHY Identifier 1 Register. 3 PHY Identifier 2 Register. 4 Auto-Negotiation Advertisement Register. 5 Auto-Negotiation Link Partner Ability Register. 6 Auto-Negotiation Expansion Register. Single-Chip Octal 10/100-TX/FX PHY Transceiver RTL8208B-LF/RTL8208BF-LF LL: LH: Table 10. Register Descriptions 13 Datasheet Latch Low until cleared Latch High until cleared Track ID: JATR-1076-21 Rev. 1.3 ...

Page 20

... Serial Management Interface composed of MDC, MDIO, that allows the MAC to manage the PHY. Reset – In order to reset the RTL8208B(F)-LF using software control, a ‘1’ must be written to bit 15 using an SMI write operation. The bit clears itself after the reset process has completed. Writes to other Control register bits will have no effect until the reset process has completed (approximately 1µ ...

Page 21

... Auto negotiation can be disabled via software control by setting 0.12=0. Power Down – The RTL8208B(F)-LF supports a low power mode. Writing a ‘1’ will enable power down mode, and writing a ‘0’ will return the RTL8208B(F)-LF to normal operation. When read, this register will return a ‘ ...

Page 22

... Jabber Detect 1.0 Extended Capability 100Base_T4 – The RTL8208B(F)-LF does not support the T4 function. Any reads to this bit will return a ‘0’. 100Base_TX_FD – The RTL8208B(F)-LF is capable of operating in 100Base-TX full duplex mode. 100Base_TX_HD – The RTL8208B(F)-LF is capable of operating in 100Base-TX half duplex mode. ...

Page 23

... Link Status – The RTL8208B(F)-LF will return a ‘1’ on bit 2 when the link state machine is in Link Pass, indicating that a valid link has been established. Otherwise, it will return ‘0’. When a link failure occurs after the link pass state has been entered, the Link Status bit will be latched at ‘ ...

Page 24

... Description Composed of the 3rd to 18th bits of the Organizationally Unique Identifier (OUI). Table 14. Register3: PHY Identifier 2 Register Description th th Assigned to the 19 through 24 Manufacturer’s model number. Manufacturer's revision number. 18 RTL8208B-LF/RTL8208BF-LF Type RO Type bits of the OUI Track ID: JATR-1076-21 Rev. 1.3 Datasheet Default 001C h ...

Page 25

... Selector Field Next Page – The RTL8208B(F)-LF does not implement the Next Page function, so bit 15 will always return a ‘0’ when read. Acknowledge – Because the Next Page function is not implemented, bit 14 will always return a ‘0’ when read. ...

Page 26

... This bit is used by one MAC to communicate Pause Capability to its Link Partner and has no effect on PHY operation. 100Base-T4 – Because the RTL8208B(F)-LF does not support the T4 function, any reads to this bit will return a ‘0’. 100Base-TX-FD – This bit advertises that the RTL8208B(F)-LF can operate in 100Base-TX full duplex mode. Writing a ‘ ...

Page 27

... Link Partner When auto-negotiation is disabled, this bit is set when Reg.0.13=0 and Reg.0.8=1. 1: 10Base-TX half duplex supported by Link Partner 0: 10Base-TX half duplex not supported by Link Partner When auto-negotiation disabled, this bit is set when Reg.0.13=0 and Reg.0.8=0. [00001]=IEEE 802.3. 21 RTL8208B-LF/RTL8208BF-LF Datasheet Type Default ...

Page 28

... Asymmetric Pause – Indicates that the Link Partner asymmetric pause bit is set. Pause – Indicates that the Link Partner pause bit is set. 100Base-T4 – Though the RTL8208B(F)-LF does not support the T4 function, this bit reflects the T4 ability of the Link Partner. 100Base-TX-FD – This bit indicates that the Link Partner can support 100Base-TX full duplex mode. ...

Page 29

... Link Partner Next Page Able – Bit 3 returns a ‘1’ when the Link Partner has Next Page capabilities. It has the same value as bit 15 of the Link Partner Ability Register. Local Next Page Able – The RTL8208B(F)-LF does not have Next Page capabilities will always return a ‘0’ when bit 2 is read. ...

Page 30

... Cable test on TX pair 0: Cable test on RX pair Must be set to the default value. Must be set to the default value. Must be set to the default value. 0: Select RX_Pair (pair 1/2) to run cable test 1: Select TX_Pair (pair 3/6) to run cable test 24 RTL8208B-LF/RTL8208BF-LF Datasheet Type Default ...

Page 31

... These bits are valid after completion of the cable test process. Single-Chip Octal 10/100-TX/FX PHY Transceiver Description 1: Cable test status is ready 0: Cable test status is not ready Cable tester status. 00: Normal cable 01: Open in cable 10: Short in cable 11: Reserved Distance of Reflection. 25 RTL8208B-LF/RTL8208BF-LF Datasheet Type Default Track ID: JATR-1076-21 Rev. 1 ...

Page 32

... Port Pair-Loop Back Mode (PP-LPBK) mode is enabled by pulling the pin high on reset. When in PP-LPBK mode, the ports of the RTL8208BF-LF are configured as four pairs, port0 & port1, port2 & port3, port4 & port5, and port6 & port7. Each pair is set as RMII interface loopback, acting as a signal regeneration /transformation repeater switch controller is not necessary ...

Page 33

... Auto-Negotiation is finished, the link partner’s ability is stored in Register 5. If the link partner is Auto-Negotiation disabled, the RTL8208B(F)-LF enters a parallel-detection state to identify the speed of the link partner. The RTL8208B(F)-LF will link at the same speed as the link partner, in half duplex mode if FRC_PARA_FULL=0 upon reset full duplex mode if FRC_PARA_FULL=1 upon reset ...

Page 34

... Register 0.15=1, which is self-clearing. 7.2.2. Setup and Configuration The operational modes of the RTL8208B(F)-LF can be configured either by hardware pin (pulled high or low) upon reset software programming via accessing the RTL8208B(F)-LF registers through the SMI (see section 5 Pin Descriptions, page 6 for details). ...

Page 35

... Transmit Function Upon detection of TX_EN high, the RTL8208B(F)-LF converts RMII/SMII/SS-SMII TXD to a 5-bit code-group and substitutes J/K code-groups for the first two code-groups (Start of Stream Delimiters (SSD)). As long as TX_EN is asserted high, 4B5B coding continues for all data. At the end of TX_EN, T/R code-groups are appended to the last data field ...

Page 36

... Transmit Error (used to force signaling errors) 00000 Invalid code 00001 Invalid code 00010 Invalid code 00011 Invalid code 00101 Invalid code 00110 Invalid code 01000 Invalid code 01100 Invalid code 10000 Invalid code 11001 Invalid code 30 RTL8208B-LF/RTL8208BF-LF Datasheet Track ID: JATR-1076-21 Rev. 1.3 ...

Page 37

... Pass’ state and the transmit and receive functions will be enabled. 7.5. Baseline Wander Compensation The RTL8208B(F)-LF is ANSI TP-PMD compliant and supports input and Base Line Wander (BLW) compensation in 100Base-TX mode. The RTL8208B(F)-LF does not require external attenuation circuitry at its receive inputs, RXIP/RXIN. It accepts TP-PMD compliant waveforms directly, requiring only a 100Ω ...

Page 38

... Reg.1.4 is set, which means the transmit path (Remote side’s receive path) has problems. If the RTL8208BF-LF detects no valid link pulse on the RxOP/N pair, it sends out a FEFI stream pattern, which in turn will cause the remote side to detect a Far-End-Fault. This means the RTL8208BF-LF sees problems on the receive path ...

Page 39

... Reduced Fiber Interface The RTL8208BF-LF ignores the underlying SD signal of the fiber transceiver to complete link detection and connection. This is achieved by monitoring RD signals from the fiber transceiver and checking whether any link integrity events are encountered. This significantly reduces pin-count, especially for high-port PHY devices ...

Page 40

... RMII (Reduced MII) The RTL8208B(F)-LF meets all of the RMII requirements outlined in the RMII Consortium specifications. The main advantage introduced by RMII is pin count reduction; e.g., it operates with only one 50MHz reference clock for both the TX and RX sides, without separate clocks needed for both paths, as with the MII interface ...

Page 41

... SMII (Serial MII) The RTL8208B(F)-LF also supports SMII interface to MAC, which allows a further reduction in the number of signals. As illustrated below, both the MAC and RTL8208B(F)-LF are synchronous to a 125MHz reference clock. Receive Path Receive data and control information are signaled in 10-bit segments. The SYNC signal is used to delimit the 10-bit segments ...

Page 42

... TXD[0] TX_ER TX_EN Collision Detection The RTL8208B(F)-LF does not indicate that a collision has occurred left to the MAC to detect the assertion of both CRS_DV and TX_EN. 7.7.3. SS-SMII (Source Synchronous -Serial MII) Source-Synchronous SMII is designed for applications requiring a trace delay of more than 1ns. Three signals are added to the SMII interface: RX_SYNC, RX_CLK, TX_CLK ...

Page 43

... MII receive path. The PHY can sample one of the ten segments TX_CLK TX_SYNC TXD[0] TX_ER TX_EN Collision Detection The RTL8208B(F)-LF does not indicate that a collision has occurred left to the MAC to detect the assertion of both CRS_DV and TX_EN. Single-Chip Octal 10/100-TX/FX PHY Transceiver RXD0 RXD1 ...

Page 44

... Serial LEDs The RTL8208B(F)-LF supports serial LED status streams for LED display. The forms of LED status streams, shown below, are controlled by LEDMODE[1:0] pins, which are latched upon reset. All LED statuses are represented as active-low, except Link/Act in Bi-color LED mode, whose polarity depends on Spd status ...

Page 45

... Low for 100Mbps, high for 10Mbps. Link/Activity/Speed Indicator. Low for link established. Blinking every 43ms for 100Mbps activity. Blinking every 120ms for 10Mbps activity. 640 ns 3 Spd Figure 10. 3-Bit Serial Stream Mode 640 ns Figure 11. 2-Bit Serial Stream Mode 39 RTL8208B-LF/RTL8208BF-LF 640 ns 640 ns 640 ns 640 Col/Dup Link/Act ...

Page 46

... QB CLK QC QD VDD 74164 CLR 40 RTL8208B-LF/RTL8208BF-LF VDD Port 7 Spd LED Port 7 Link/Act LED Port 7 Col/Dup LED Port 6 Spd LED Port 6 Link/Act LED Port 6 Col/Dup LED Port 5 Spd LED Port 5 Link/Act LED Port 5 Col/Dup LED Port 4 Spd LED Port 4 Link/Act LED Port 4 Col/Dup LED ...

Page 47

... LED package with two LEDs connected in parallel and with opposite polarities. Spd 7.9.2. Scan LED The RTL8208B(F)-LF supports Scan LED display mode. The forms of LED status streams, as shown below, are controlled by LEDMODE[1:0] pins, which are latched upon reset. LEDMODE[1: LED Status ...

Page 48

... T2: Fall time of all SCAN signals, typically 40ns. Single-Chip Octal 10/100-TX/FX PHY Transceiver 2.5µS 2.5µS 2.5µS 3-bit LED 3-bit LED 3-bit LED 90% 10% 42 RTL8208B-LF/RTL8208BF-LF 2.5µS 2.5µS 2.5µS 3-bit LED 3-bit LED 3-bit LED 90% 10% Track ID: JATR-1076-21 Rev. 1.3 Datasheet 2.5µ ...

Page 49

... External Circuit for Scan LED Mode 0 Single-Chip Octal 10/100-TX/FX PHY Transceiver Figure 17. External Circuit for Scan LED Mode 0 43 RTL8208B-LF/RTL8208BF-LF Datasheet Track ID: JATR-1076-21 Rev. 1.3 ...

Page 50

... External Circuit for Scan LED Mode 1 Single-Chip Octal 10/100-TX/FX PHY Transceiver Figure 18. External Circuit for Scan LED Mode 1 44 RTL8208B-LF/RTL8208BF-LF Datasheet Track ID: JATR-1076-21 Rev. 1.3 ...

Page 51

... External Circuit for Scan LED Mode 2 Single-Chip Octal 10/100-TX/FX PHY Transceiver Figure 19. External Circuit for Scan LED Mode 2 45 RTL8208B-LF/RTL8208BF-LF Datasheet Track ID: JATR-1076-21 Rev. 1.3 ...

Page 52

... Crossover Detection and Auto Correction During the link setup phase, the RTL8208B(F)-LF checks whether it receives active signals on each port in order to determine if a connection can be established. In cases where the RTL8208B(F)-LF receiver data pin pair is connected to the receiver data pin pair of the peer device, or vice versa, the RTL8208B(F)-LF will automatically change its configuration to swap receiver data pins with transmitter data pins ...

Page 53

... Emitter and Collector of the power transistor. If your system needs more than one RTL8208B(F)-LF chip (greater than 8 ports), do not use one PNP transistor for all of the RTL8208B(F)-LF chips, even if the rating is enough. Instead, use one transistor for each RTL8208B(F)-LF ...

Page 54

... Application Information 8.1. 10Base-T/100Base-TX Application Single-Chip Octal 10/100-TX/FX PHY Transceiver Figure 21. 10Base-T/100Base-TX Application 48 RTL8208B-LF/RTL8208BF-LF Datasheet Track ID: JATR-1076-21 Rev. 1.3 ...

Page 55

... Application (RTL8208BF-LF only) Figure 22. 100Base-FX Application (RTL8208BF-LF only) Single-Chip Octal 10/100-TX/FX PHY Transceiver RTL8208B-LF/RTL8208BF-LF 49 Track ID: JATR-1076-21 Rev. 1.3 Datasheet ...

Page 56

... Power saving Power down 10Base-T, idle 10Base-T, peak continuous 100% utilization 100Base-TX, idle 100Base-TX, peak continuous 100% utilization Power saving Power down 50 RTL8208B-LF/RTL8208BF-LF Max Units °C +125 +1.98 V +3.63 V VDD+0.3 V Max - +70 3 ...

Page 57

... OH TX+/- Output Current I Low OL RX+/- Common-mode Input Voltage - RX+/- Differential Input Resistance - Differential Input Resistance - Input Squelch Threshold - Single-Chip Octal 10/100-TX/FX PHY Transceiver Transmitter, 100Base-TX (1:1 Transformer Ratio) Transmitter, 10Base-T(1:1 Transformer Ratio) Receiver, 100Base-TX Receiver, 10Base-T 51 RTL8208B-LF/RTL8208BF-LF Datasheet Typical Min Max 0 ...

Page 58

... Table 40. Digital Timing Characteristics Conditions 100Base-TX Transmit System Timing From TXD[1:0] to TXOP/N 100Base-TX Receive System Timing From RXIP/N to CRS_DV From RXIP/N to CRS_DV From RXIP/N to RXD[1:0] 10Base-TX Transmit System Timing From TXD[1:0] to TXOP/N From TX_EN assert to TXOP/N 52 RTL8208B-LF/RTL8208BF-LF Datasheet Min Typical Max 2.022 - - 100 2.7 ...

Page 59

... While LED blinking Jabber Timing (10Base-T Only) From TX_EN=1 to Jabber asserted From TX_EN=0 to Jabber de-asserted SMI Timing MDC clock rate Write cycle Write cycle Read cycle Table 41. RMII Receive Timing Minimum T_opd_rxd_rmii REFCLK RXD Figure 23. RMII Receive Timing 53 RTL8208B-LF/RTL8208BF-LF Min Typical - ...

Page 60

... Single-Chip Octal 10/100-TX/FX PHY Transceiver Table 42. RMII Transmit Timing Minimum T_ipsu_txd_rmii REFCLK TXD Valid Data Figure 24. RMII Transmit Timing Table 43. SMII Receive Timing Minimum T_opd_rxd_smii REFCLK RXD Figure 25. SMII Receive Timing 54 RTL8208B-LF/RTL8208BF-LF Typical Maximum T_iphd_txd_rmii Typical Maximum 3.5 4 4.5 Track ID: JATR-1076-21 Rev. 1.3 ...

Page 61

... RX_CLK rising edge to RXD/RX_SYNC delay. Single-Chip Octal 10/100-TX/FX PHY Transceiver Table 44. SMII Transmit Timing Minimum T_ipsu_txd_smii REFCLK TXD Valid Data Figure 26. SMII Transmit Timing Table 45. SS-SMII Receive Timing T_opd_rxd_s3mii RX_CLK RXD Figure 27. SS-SMII Receive Timing 55 RTL8208B-LF/RTL8208BF-LF Typical Maximum 1 T_iphd_txd_smii Minimum Typical Maximum 1 Track ID: JATR-1076-21 Rev ...

Page 62

... Power Stable, stable supply voltage to reset high duration. • trw: max. 50ms, Reset_wait (Start normal PHY after reset deassertion). Single-Chip Octal 10/100-TX/FX PHY Transceiver Table 46. SS-SMII Transmit Timing Minimum T_ipsu_txd_s3mii TX_CLK TXD Valid Data Figure 28. SS-SMII Transmit Timing 56 RTL8208B-LF/RTL8208BF-LF Typical Maximum 1 T_iphd_txd_s3mii Track ID: JATR-1076-21 Rev. 1.3 ...

Page 63

... Note: PCB conditions (JEDEC JESD51-7) Single-Chip Octal 10/100-TX/FX PHY Transceiver Figure 30. Cross-section of 128-Pin QFP Table 47. Thermal Operating Range Conditions Table 48. Thermal Resistances Conditions 2 layer PCB, 0 ft/s airflow 2 layer PCB, 0 ft/s airflow 57 RTL8208B-LF/RTL8208BF-LF Datasheet Min Typical Max - 25 125 - 25 70 Min ...

Page 64

... Mechanical Dimensions See the Mechanical Dimensions notes on the next page. Single-Chip Octal 10/100-TX/FX PHY Transceiver RTL8208B-LF/RTL8208BF-LF 58 Track ID: JATR-1076-21 Rev. 1.3 Datasheet ...

Page 65

... BSC CHECK - - 0.10 0° - 12° REALTEK SEMICONDUCTOR CORP. Table 49. Ordering Information Package 128-pin QFP with lead (Pb)-free package RTL8208B-LF with Fiber support 59 RTL8208B-LF/RTL8208BF-LF Datasheet & not include mold protrusion visual inspection. TITLE: DOC. NO. VERSION PAGE DWG NO. DATE Status Track ID: JATR-1076-21 Rev ...

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