MX29LV640BBTC-90 Macronix International Co., MX29LV640BBTC-90 Datasheet
MX29LV640BBTC-90
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MX29LV640BBTC-90 Summary of contents
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FEATURES GENERAL FEATURES • Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program opera- tions • 8,388,608 4,194,304 x 16 switchable • Sector structure - 8KB (4KW and 64KB(32KW) x ...
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MX29LV640BT/BB uses a command register to manage this functionality. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the combination of ...
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PIN CONFIGURATION 48 TSOP A15 1 A14 2 A13 3 A12 4 A11 5 A10 A19 9 A20 10 WE# 11 RESET# 12 A21 13 WP#/ACC 14 RY/BY# 15 A18 16 A17 ...
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PIN DESCRIPTION SYMBOL PIN NAME A0~A21 Address Input Q0~Q14 Data Inputs/Outputs Q15/A-1 Q15(Word Mode)/LSB addr(Byte Mode) CE# Chip Enable Input WE# Write Enable Input OE# Output Enable Input RESET# Hardware Reset Pin, Active Low WP#/ACC Hardware Write Protect/Programming Acceleration Input ...
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BLOCK DIAGRAM CE# OE# CONTROL WE# INPUT WP#/ACC LOGIC BYTE# RESET# ADDRESS LATCH A0-A21 AND BUFFER Q0-Q15 P/N:PM1076 MX29LV640BT/BB PROGRAM/ERASE HIGH VOLTAGE FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 5 ...
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MX29LV640BT SECTOR GROUP ARCHITECTURE Sector Sector Sector Address Group A21-A12 1 SA0 0000000xxx 1 SA1 0000001xxx 1 SA2 0000010xxx 1 SA3 0000011xxx 2 SA4 0000100xxx 2 SA5 0000101xxx 2 SA6 0000110xxx 2 SA7 0000111xxx 3 SA8 0001000xxx 3 SA9 0001001xxx ...
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Sector Sector Sector Address Group A21-A12 11 SA40 0101000xxx 11 SA41 0101001xxx 11 SA42 0101010xxx 11 SA43 0101011xxx 12 SA44 0101100xxx 12 SA45 0101101xxx 12 SA46 0101110xxx 12 SA47 0101111xxx 13 SA48 0110000xxx 13 SA49 0110001xxx 13 SA50 0110010xxx 13 ...
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Sector Sector Sector Address Group A21-A12 21 SA80 1010000xxx 21 SA81 1010001xxx 21 SA82 1010010xxx 21 SA83 1010011xxx 22 SA84 1010100xxx 22 SA85 1010101xxx 22 SA86 1010110xxx 22 SA87 1010111xxx 23 SA88 1011000xxx 23 SA89 1011001xxx 23 SA90 1011010xxx 23 ...
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Sector Sector Sector Address Group A21-A12 31 SA120 1111000xxx 31 SA121 1111001xxx 31 SA122 1111010xxx 31 SA123 1111011xxx 32 SA124 1111100xxx 32 SA125 1111101xxx 32 SA126 1111110xxx 33 SA127 1111111000 34 SA128 1111111001 35 SA129 1111111010 36 SA130 1111111011 37 ...
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MX29LV640BB SECTOR GROUP ARCHITECTURE Sector Sector Sector Address Group A21-A12 1 SA0 0000000000 2 SA1 0000000001 3 SA2 0000000010 4 SA3 0000000011 5 SA4 0000000100 6 SA5 0000000101 7 SA6 0000000110 8 SA7 0000000111 9 SA8 0000001xxx 9 SA9 0000010xxx ...
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Sector Sector Sector Address Group A21-A12 17 SA39 0100000xxx 17 SA40 0100001xxx 17 SA41 0100010xxx 17 SA42 0100011xxx 18 SA43 0100100xxx 18 SA44 0100101xxx 18 SA45 0100110xxx 18 SA46 0100111xxx 19 SA47 0101000xxx 19 SA48 0101001xxx 19 SA49 0101010xxx 19 ...
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Sector Sector Sector Address Group A21-A12 27 SA79 1001000xxx 27 SA80 1001001xxx 27 SA81 1001010xxx 27 SA82 1001011xxx 28 SA83 1001100xxx 28 SA84 1001101xxx 28 SA85 1001110xxx 28 SA86 1001111xxx 29 SA87 1010000xxx 29 SA88 1010001xxx 29 SA89 1010010xxx 29 ...
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Sector Sector Sector Address Group A21-A12 37 SA119 1110000xxx 37 SA120 1110001xxx 37 SA121 1110010xxx 37 SA122 1110011xxx 38 SA123 1110100xxx 38 SA124 1110101xxx 38 SA125 1110110xxx 38 SA126 1110111xxx 39 SA127 1111000xxx 39 SA128 1111001xxx 39 SA129 1111010xxx 39 ...
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Table 1. BUS OPERATION (1) Operation CE# OE# WE# RE- Read L L Write (Program/Erase Accelerated Program L H Standby VCC X 0.3V Output Disable L H Reset X X Sector Group Protect L H (Note 2) Chip ...
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Table 2. AUTOSELECT CODES (High Voltage Method) Operation CE# OE# WE# A0 Manufactures Code Read Device Code Silicon (Top Boot Block) ID Device Code (Bottom Boot Block) Sector Protect Verify Secured Silicon Sector Indicator Bit (Q7) Notes: 1.code=xx00h means unprotected, ...
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REQUIREMENTS FOR READING ARRAY DATA To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array ...
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MX29LV640BT/BB addresses remain stable during ac- cess time of tACC+30ns not necessary to control CE#, WE#, and OE# on the mode. Under the mode, the current consumed is typically 0.2uA (CMOS ...
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It is recommended to protect all sectors before ac- tivating chip unprotect mode. To activate this mode, the programming equipment must ...
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During power up the device automatically re- sets the state machine in the Read mode. In addition, with its control register architecture, alteration ...
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FACTORY LOCKED:Secured Silicon Sector Programmed and Protected At the Factory In device with an ESN, the Secured Silicon Sector is protected when the device is shipped from the factory. The Secured Silicon Sector cannot be modified in any way. A ...
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SOFTWARE COMMAND DEFINITIONS Device operations are selected by writing specific ad- dress and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. ...
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Legend: X=Don't care RA=Address of the memory location to be read. RD=Data read from location RA during read operation. PA=Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# or CE# pulse, ...
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READING ARRAY DATA The device is automatically set to reading array data after device power-up. No commands are required to re- trieve data. The device is also ready to read array data after completing an Automatic Program or Automatic Erase ...
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The Byte/Word Program command sequence should be reinitiated once the device has reset to read- ing array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A ...
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Sector Erase(30H) or Erase Suspend(B0H) during the time-out period resets the device to read mode. ERASE SUSPEND This command only has meaning while the state ma- chine is executing Automatic Sector Erase operation, and therefore will only be responded ...
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Table 4-1. CFI mode: Identification Data Values (All values in these tables are in hexadecimal) Description Query-unique ASCII string "QRY" Primary vendor command set and control interface ID code Address for primary algorithm extended query table Alternate vendor command set ...
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Number of erase block regions Erase block region 1 information [2E,2D blocks in region -1 [30, 2F] = size in multiples of 256-bytes Erase Block Region 2 Information (refer to CFI publication 100) Erase Block Region 3 ...
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WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/BY#. Table 5 and the following subsections describe the func- tions of these bits. Q7, RY/BY#, and Q6 ...
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Q7: Data# Polling The Data# Polling bit, Q7, indicates to the host system whether an Automatic Algorithm is in progress or com- pleted, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of ...
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Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 5 to compare ...
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Toggle Bit low ("0"), the device will accept addi- tional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . ..... -65 Ambient Temperature with Power Applied .... ...
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DC CHARACTERISTICS TA=- VCC=2.7V~3.6V Para- meter Description I LI Input Load Current (Note 1) I LIT A9 Input Leakage Current I LO Output Leakage Current ICC1 VCC Active Read Current (Notes 2,3) ICC2 VCC Active Write ...
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SWITCHING TEST CIRCUITS DEVICE UNDER TEST CL 6.2K ohm KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Don't Care, Any Change Permitted Does Not Apply SWITCHING TEST WAVEFORMS 3.0V 0.0V INPUT P/N:PM1076 MX29LV640BT/BB TEST SPECIFICATIONS Test Condition Output Load 2.7K ohm Output ...
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AC CHARACTERISTICS Read-Only Operations TA=- VCC=2.7V~3.6V Parameter Std. Description tRC Read Cycle Time (Note 1) tACC Address to Output Delay tCE Chip Enable to Output Delay tOE Output Enable to Output Delay tDF Chip Enable to ...
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Figure 1. COMMAND WRITE OPERATION VCC 3V VIH Addresses VIL tAS VIH WE# VIL CE# VIH VIL tCS OE# VIH VIL VIH Data VIL P/N:PM1076 MX29LV640BT/BB ADD Valid tAH tWP tCWC tCH tDS tDH DIN 36 tWPH REV. 1.2, SEP. ...
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READ/RESET OPERATION Figure 2. READ TIMING WAVEFORMS VIH Addresses VIL VIH CE# VIL VIH WE# VIL VIH OE# VIL HIGH Z VOH Outputs VOL VIH RESET# VIL RY/BY# 0V P/N:PM1076 MX29LV640BT/BB tRC ADD Valid tCE tRH tRH tOEH tOE tACC ...
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AC CHARACTERISTICS Parameter Description tREADY1 RESET# PIN Low (During Automatic Algorithms) to Read or Write (See Note) tREADY2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write (See Note) tRP1 RESET# Pulse Width (During Automatic Algorithms) tRP2 RESET# ...
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ERASE/PROGRAM OPERATION Figure 4. AUTOMATIC CHIP/SECTOR ERASE TIMING WAVEFORM Erase Command Sequence(last two cycle) tWC 2AAh Address CE# OE# tWP WE# tCS tDS tDH Data RY/BY# tVCS VCC NOTES: 1.SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write ...
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Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART P/N:PM1076 MX29LV640BT/BB START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H ...
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Figure 6. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART P/N:PM1076 MX29LV640BT/BB START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address ...
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Figure 7. ERASE SUSPEND/RESUME FLOWCHART P/N:PM1076 MX29LV640BT/BB START Write Data B0H ERASE SUSPEND NO Toggle Bit checking Q6 not toggled YES Read Array or Program Reading or NO Programming End YES Write Data 30H ERASE RESUME Continue Erase Another NO ...
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Figure 8. SECURED SILICON SECTOR PROTECTED ALGORITHMS FLOWCHART Device Failed P/N:PM1076 MX29LV640BT/BB START Enter Secured Silicon Sector Wait 1us First Wait Cycle Data=60h Second Wait Cycle Data=60h A6=0, A1=1, A0=0 Wait 300us No Data = 01h ? Yes Write Reset ...
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AC CHARACTERISTICS Erase and Program Operations Parameter Std. Description tWC Write Cycle Time (Note 1) tCWC Command Write Cycle Time (Note 1) tAS Address Setup Time tASO Address Setup Time to OE# low during toggle bit polling tAH Address Hold ...
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Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORMS Program Command Sequence(last two cycle) tWC XXXh Address CE# OE# tWP WE# tCS Data RY/BY# tVCS VCC NOTES: 1.PA=Program Address, PD=Program Data, DOUT is the true data the program address Figure 10. ACCELERATED PROGRAM ...
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AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Parameter Std. Description tWC Write Cycle Time (Note 1) tAS Address Setup Time tAH Address Hold Time tDS Data Setup Time tDH Data Hold Time tGHEL Read Recovery Time Before Write ...
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Figure 11. CE# CONTROLLED PROGRAM TIMING WAVEFORM 555 for program 2AA for erase Address tWC tWH WE# tGHEL OE# CE# tWS Data tRH RESET# RY/BY# NOTES: 1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device. 2.Figure indicates ...
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Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART Increment Address P/N:PM1076 MX29LV640BT/BB START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data Poll from system No Verify Word Ok ? YES No ...
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SECTOR GROUP PROTECT/CHIP UNPROTECT Figure 13. Sector Group Protect / Chip Unprotect Waveform (RESET# Control) VID VIH RESET# SA, A6 A1, A0 Sector Group Protect or Chip Unprotect Data 60h 1us CE# WE# OE# Note: For sector group protect A6=0, ...
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Figure 14. IN-SYSTEM SECTOR GROUP PROTECT/CHIP UNPROTECT ALGORITHMS WITH RESET#=VID START PLSCNT=1 RESET#=VID Wait 1us No First Write Temporary Sector Unprotect Mode Cycle=60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A6=0, A1=1, A0=0 Wait ...
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AC CHARACTERISTICS Parameter Description tVLHT Voltage transition time tWPP1 Write pulse width for sector group protect tWPP2 Write pulse width for chip unprotect tOESP OE# setup time to WE# active Figure 15. SECTOR GROUP PROTECT TIMING WAVEFORM (A9, OE# Control) ...
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Figure 16. SECTOR GROUP PROTECTION ALGORITHM (A9, OE# Control) No PLSCNT=32? Yes Device Failed P/N:PM1076 MX29LV640BT/BB START Set Up Sector Addr PLSCNT=1 OE#=VID, A9=VID, CE#=VIL A6=VIL Activate WE# Pulse Time Out 150us Set WE#=VIH, CE#=OE#=VIL A9 should remain VID Read ...
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Figure 17. CHIP UNPROTECT TIMING WAVEFORM (A9, OE# Control) A1 12V 3V A9 tVLHT A6 12V 3V OE# tVLHT WE# CE# Data P/N:PM1076 MX29LV640BT/BB tWPP 2 tOESP 53 Verify tVLHT 00H F0H tOE REV. 1.2, SEP. 07, 2005 ...
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Figure 18. CHIP UNPROTECT FLOWCHART (A9, OE# Control) Increment Sector Addr * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM1076 MX29LV640BT/BB START Protect All Sectors PLSCNT=1 Set OE#=A9=VID CE#=VIL, A6=1 Activate WE# Pulse ...
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AC CHARACTERISTICS Parameter Description tVIDR VID Rise and Fall Time (see Note) tRSP RESET# Setup Time for Temporary Sector Unprotect tRRB RESET# Hold Time from RY/BY# High for Temporary Sector Group Unprotect Figure 19. TEMPORARY SECTOR GROUP UNPROTECT WAVEFORMS 12V ...
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Figure 20. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART Note : 1. All protected sectors are temporary unprotected. P/N:PM1076 MX29LV640BT/BB Start RESET# = VID (Note 1) Perform Erase or Program Operation Operation Completed RESET# = VIH Temporary Sector Unprotect Completed(Note 2) VID=11.5V~12.5V ...
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Figure 21. SILICON ID READ TIMING WAVEFORM VCC 3V VID ADD VIH A9 VIL VIH ADD A0 VIL tACC A1 VIH VIL VIH ADD VIL CE# VIH VIL tCE VIH WE# VIL VIH OE# VIL VIH DATA VIL Q0-Q15 P/N:PM1076 ...
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WRITE OPERATION STATUS Figure 22. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) tRC Address VA tACC tCE CE# tCH tOE OE# tOEH WE# Q7 Q0-Q6 tBUSY RY/BY# NOTES: VA=Valid address. Figure shows are first status cycle after command sequence, last ...
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Figure 23. DATA# POLLING ALGORITHM Notes: 1.VA=valid address for programming. 2.Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1076 MX29LV640BT/BB Start Read Q7~Q0 Add.=VA(1) Yes Q7 = Data ? ...
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Figure 24. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) tRC Address VA tACC tCE CE# tCH tOE OE# tOEH WE# tDH Q6/Q2 Valid Status RY/BY# NOTES: VA=Valid address; not required for Q6. Figure shows first two status cycle after command ...
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Figure 25. TOGGLE BIT ALGORITHM NO Note: 1. Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 changes to "1". P/N:PM1076 MX29LV640BT/BB START Read Q7~Q0 Read ...
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Figure 26. Q6 versus Q2 Enter Embedded Erase Erasing Suspend Erase WE NOTES: The system can use toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended P/N:PM1076 MX29LV640BT/BB Enter Erase ...
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ERASE AND PROGRAMMING PERFORMANCE (1) PARAMETER Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Accelerated Word/Byte Program Time Chip Programming Time Erase/Program Cycles Note: 1. Not 100% Tested, Excludes external system level over head. 2. Typical ...
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... MX29LV640BTTC-90 90 MX29LV640BTTC-12 120 MX29LV640BBTC-90 90 MX29LV640BBTC-12 120 MX29LV640BTTI-90 90 MX29LV640BTTI-12 120 MX29LV640BBTI-90 90 MX29LV640BBTI-12 120 MX29LV640BTTC-90G 90 MX29LV640BTTC-12G 120 MX29LV640BBTC-90G 90 MX29LV640BBTC-12G 120 MX29LV640BTTI-90G 90 MX29LV640BTTI-12G 120 MX29LV640BBTI-90G 90 MX29LV640BBTI-12G 120 P/N:PM1076 MX29LV640BT/BB Ball Pitch/ PACKAGE Ball size 48 Pin TSOP (Normal Type) 48 Pin TSOP (Normal Type) 48 Pin TSOP ...
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PART NO. ACCESS TIME (ns) MX29LV640BTXBC-90 90 MX29LV640BTXBC-12 120 MX29LV640BBXBC-90 90 MX29LV640BBXBC-12 120 MX29LV640BTXBI-90 90 MX29LV640BTXBI-12 120 MX29LV640BBXBI-90 90 MX29LV640BBXBI-12 120 MX29LV640BTXBC-90G 90 MX29LV640BTXBC-12G 120 MX29LV640BBXBC-90G 90 MX29LV640BBXBC-12G 120 MX29LV640BTXBI-90G 90 MX29LV640BTXBI-12G 120 MX29LV640BBXBI-90G 90 MX29LV640BBXBI-12G 120 P/N:PM1076 MX29LV640BT/BB Ball ...
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PACKAGE INFORMATION P/N:PM1076 MX29LV640BT/BB 66 REV. 1.2, SEP. 07, 2005 ...
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P/N:PM1076 MX29LV640BT/BB 67 REV. 1.2, SEP. 07, 2005 ...
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REVISION HISTORY Revision No. Description 1.0 1. Removed "Preliminary" 1.1 1. Added "BYTE#" in Pin Description & Logic Symbol 1.2 1. Modified "RESET# TIMING WAVEFORM" P/N:PM1076 MX29LV640BT/BB Page P1 P4 P38 68 Date MAR/08/2005 MAR/22/2005 SEP/07/2005 REV. 1.2, SEP. 07, ...
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... MX29LV640BT/BB MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. ...