LH28F160S5NS-L70 Sharp, LH28F160S5NS-L70 Datasheet
LH28F160S5NS-L70
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LH28F160S5NS-L70 Summary of contents
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... P S RODUCT PECIFICATIONS LH28F160S5NS-L70 Flash Memory 16M (2MB × 8/1MB × 16) (Model No.: LHF16KA4) Issue Date: August 22, 2000 ® Spec No.: EL128040 Integrated Circuits Group ...
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... SHARP . - l Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. l When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions ...
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SHAl ...................................................... 1 INTRODUCTION 1 .l Product Overview ................................................ 2 PRINCIPLES OF OPERATION ................................ 2.1 Data Protection ................................................... 3 BUS OPERATION.. .................................................. 3.1 Read ................................................................... 3.2 Output Disable .................................................... 3.3 Standby ............................................................... 3.4 Deep Power-Down .............................................. ...
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... Scalable Command Set (SCS) and the Common Flash Interface CFI) specification which enable universal and upgradable interface, enable the highest system/device data transfer ‘ates and minimize device and system-level implementation costs. The LH28F160S5NS-L70 is manufactured ndustry-standard package: the 56-Lead SSOP, ideal for board constrained applications. ...
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... LH28F160SSNSL70 specifications. Section 1 provides a flash memory overview. Sections and 5 describe memory organization and functionality. covers electrical specifications Product Overview The LH28F160S5NSL70 is a high-performance bit Smart 5 Flash memory 2MBx8/1 MBxl6. The 2MB of data is arranged thirty-two 64K-byte blocks which are individually erasable, lockable, and unlockable memory map is shown in Figure 3 ...
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SHARF CEn,# A12. A13. A14 / A20 49 Ale A17 4s VCC GND DQ6 DQ14 DQ7 DQls STS OE# WE# WP# DQn DQ5 DQ12 DQ4 vcc L LHFlGKA4 Figure 1. Block Diagram 56 LEAD SSQP ...
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SHARI Symbol Type ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. Ao: Byte Select Address. Not used in x16 mode(can be floated). INPUT A0420 AI-AK Column ...
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... SHARP . . - .- - 2 PRINCIPLES OF OPERATION The LH28F160S5NS-L70 Flash memory includes an on-chip WSM to manage block erase, full chip erase, write and (multi) word/byte configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erase, full chip erase, (multi) word/byte block lock-bit configuration, and minimal processor overhead with RAM-Like interface timings ...
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... RP#-low deselects the memory state ant until initial memory access device important flash memories provide status If a CPU reset occurs with no flash may no! instead of array data. SHARP’s allow proper CPU initialization RP# is controlled by the Rev. 1 ...
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SHARI= 3.5 Read Identifier Codes Operation The read identifier codes operation manufacturer code, device code, block status codes for each block (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with its ...
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SliARP - RP# Mode Notes Read 1,2,3,9 V,H V,w Output Disable 3 3 Standby VI, V,, Deep Power-Down 4 Read Identifier 9 VI, Codes 9 Query VI Write 13,7,8,9 1 V,H V,, Deep Power-Down 4 Read identifier 9 ...
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... Following the Third Bus Cycle, inputs the write address and write data of ‘N’ times. Finally, input the confirm command ‘DOH’. 10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. LHFlGKA4 Table 4 ...
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... SHARP . - - 4.1 Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the ...
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... SHARP -- - 1.5 Query Command ;luery database can be read by writing Query :ommand (98H). Following the command write, read ycle from address shown in Table 7-l 1 retrieve the xitical information to write, erase and otherwise :ontrol the flash component query offset iddress is ignored when X8 mode (BYTE#=V,L). ...
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... SHARP ~. . - -- - 4.5.2 CFI Query Identification The Identification String provides specification. Additionally, it indicates which version of the spec and which Vendor-specified command set(s) is(are) supported. Offset Length (Word Address) Query Unique ASCII string “QRY” lOH,llH,12H 03H 51 H,52H,59H 02H Primary Vendor Command Set and Control Interface ID Code ...
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... SHARP . - 1.5.4 Device Geometry Definition rhis field provides critical details of the flash device geometry. Offset Length (Word Address) OlH Device Size 27H 15H (15H=2 1, 221 =2097152=2M 02H Flash Device Interface description 28H,29H 02H,OOH (x8/x1 6 supports x8 and xl 6 via BYTE#) Maximum Number of Bytes in Multi word/byte write ...
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... SHARP . - -- - 4.6 Block Erase Command Block erase is executed one block at a time and initiated by a two-cycle command. setup is first written, followed by an block erase confirm. This command sequence appropriate sequencing and an address within the block to be erased (erase changes all block data to FFH) ...
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... XSR.7. Thf Multi Word/Byte Write command while WSM is busy as long as XSR.7 indicates “1” because LH28F160S5NS-L70 error occurs while writing, the device will stop writin< and flush next multi word/byte write command loadec in multi word/byte write command. Status register bi SR.4 will be set to “ ...
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... SHARP . - .- _- 1.10 Block Erase Suspend Command The Block Erase Suspend command erase interruption to read or (multi) word/byte-write data in another block of memory. Once the block- 3rase process starts, writing the Suspend command requests that the WSM suspend :he block erase sequence at a predetermined :he algorithm. The device outputs status register data Nhen read after the Block Erase Suspend command s written ...
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Set Block Lock-Bit Command A flexible block locking and unlocking scheme is enabled via block lock-bits. The block lock-bits gate program and erase operations With WP#=V,,+ individual block lock-bits can be set using the Set ...
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... SHARP ~. _ - I.14 STS Configuration Command The Status (STS) pin can be configured to different ;tates using the STS Configuration he STS pin has been configured, it remains in that :onfiguration until another configuration command is ssued, the device is powered down or RP# is set to J,,. Upon initial device power-up and after exit from ...
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SHARI WSMS 1 BESS / ECBLBS SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in ...
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SHARI= r Check if Desired FULL STATUS CHECK PROCEDURE (7) Figure 5. Automated LHF16KA4 Command Read Statis write Register Read Standby Wnte Erase Setup Erase write Confirm Read / Standby Repeat for subsequent block erasures. Full stake check can be ...
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... SHARP - _ - (-y-) Check if Desired Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Figure 6. Automated LHFlGKA4 Command Data=70H Read Status write Register Addr=X 1 Read 1 1 Status Register Data Check SR.7 Standby l.WSM Ready O-WSM Busy Data-3OH Full Chip Erase Write Ad& ...
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Read stahls Reglrter 0 SR. &, Data and Address Check if Desired FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Dwce Protect Error Figure 7. Automated Bus Command Operation Read Status Data=70H write Register Addr-X Read Status ...
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... SHARP Read Extend status Register Write Anotier Block Address Multi Word/Byte Write Abort Write Buffer Data, Device Address Figure 8. Automated LHFlGKA4 Bus Command Operation DatapE3f-l SetuP Wlik Multi WordlByte Write Addr=Stwt Address Extended Status Register Data Read Check XSR.7 standby 1rMulti Wml/Byk ...
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SHARI= _- FULL STATUS CHECK PROCEDURE FOR MULTI WORD/BYTE WRITE OPERATION Device Protect Enor Figure 9. Full Status Check Procedure LHFlGKA4 Bus Command Operalion Check SR.3 Standby l-VP,, Error Detect Check SRI l=Dovica Protect Detect WP#+,Block standby Only required for ...
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SR.7= 1 Read Figure IO. Block Erase Suspend/Resume LHFlGKA4 status Ragistar Data Reed Addr.=X Check SR.7 Standby 1 -WSM Rea&y O-WSM Busy check SR.6 standby l-Block Erase Sutpwded O-Block Ease Completed Data-WI-l Write Addr-X Flowchart Rev.1.9 ...
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SHARI= stall write 5x4 =I_I Read status Register SR. (Multi) woldmte Complel Figure 11. (Multi) Word/Byte LHF16KA4 Command (Multi) wonvByta Wntc Suspend Read standby write\ ted Write Suspend/Resume 27 Comments Data-SOH AddhX Status Register Data Addr-X Check ...
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SHARI= Check if Desired Set Block Lock-Sit FULL STATUS CHECK PROCEDURE LHFlGKA4 Command Sat Block Write Lock-Bit Selup I Set Block write Lock-Bit Confirm Repeat for subsequent block lock-bit set operations. Full status cback can be done after each block ...
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... SHARP Wlite 60H Write DOH Full Status Check if Dewed Clear Block Lock-Sits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) LHF16KA4 Clear Block Write Lock-Bits Confinn Read Standby Write FFH after the Clear Block Lock-Bits operation to place device in read army mode. ...
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... SHARI DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. three control SHARP provides accommodate multiple memory connections. Three- Line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. ...
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... SHARP .- - 5.5 Vcc, Vpp, RP# Transitions Block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are not guaranteed if V,, falls outside of a valid V,,,, outside of a valid Vcc,,2 range, or RP#=V,,. If V,, error is detected, status register bit SR.3 is set to “1” ...
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... SHARP . - -- - 6 ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Erase, Write and Block Lock-Bit Configuration . . . . . . ..O”C to +70”C(1) Temperature under Bias . . . . . . . . . . . . . . . -10°C to +8O”C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125”C Voltage On Any Pin (except Vcc, V,,) . . . . . . . . . . . . . . . -09 V,, Suply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2v to +7.ov(2) ...
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... SHARP 2.2 AC INPUT/OUTPUT TEST CONDITIONS AC test inputs are driven at 3.OV for a Logic “1” and O.OV for a Logic “0.” input timing begins, Input rise and fall times (10 ns. Figure 14. Transient 4 o~T-)(--pzfzy)(yr AC test inputs are driven at VOH (2.4 (2 ...
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SHARI 5.2.3 DC CHARACTERISTICS Symbol Parameter Input Load Current ‘Ll Output Leakage Current ‘LO Vcc Standby Current ‘cc, V,, Deep Power-Down ‘CCD 4 Current V,, Read Current ‘CCR Vcc Write Current ‘ccw ((Multi) W/B Write or Set Block ...
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SHARI Parameter Symbol Input Low Voltage v,, Input High Voltage Output Low Voltage Output High Voltage ‘OH1 u-w Output High Voltage VOH2 (CMOS) VP, Lockout during Normal ‘PPLK Operations I ’ VP, during Write or Erase VPPH1 Operations ...
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SHARI= 6.2.4 AC CHARACTERISTICS Versiond4) Sym. 1 Parameter NOTES: 1. See AC input/Output Reference Waveform for maximum allowable input slew rate. 2. OE# may be delayed up to tELov-&ov 3. Sampled, not 100% tested. 4. See Ordering Information for device ...
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... SHARP Address rc VIH CE#(E) ML VIH OE#(G) ML WE#(W) VIL VOH DATA( D/Q) VOL kc RP#(P) ML NOTE: CE# isdefined as the latter of CEO# and CE,# Figure 17. AC Waveform for Read Operations LHFlGKA4 Device Selection Address Stable kVAV going Low or the first of CEo# or CE1# going High Rev. 1.9 ...
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SHARI= .- Address VIH OE#(G) WL {VlH BYTE#(F) VIL VOH HIGH Z DATA D/Cl) &l PQo- 7) VOL VOH DATA( D/Q) PQdQd VOL NOTE: CE# is defined as the latter of CEO# and CE,# LHFlGKA4 Device Selection Address Stable tFLClV=tAVQV ...
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AC CHARIicTERISTICS Vcc=5VdMV, Versions@) Parameter Sym. I tavnv 1 Write Cycle Time High Recovery to WE# Going tPHWL tF, ,,,,, 1 CE# Setup to ’ tvpww 1 Vpp Setup to W tnvwcr 1 Data Setup to W &,,-,Y 1 ...
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SHARI= ADDRESSES(A) CE#(E) OE#(G) WEW’) DATA(D/Q) STS(R) WP#(S) RP#(P) ::: VPPHl vPP(v) VPPLK NOTES: VIL- 1. Vcc power-up and standby. 2. Write erase or write setup. 3. Write erase donfirm or,valid address 4. Automated erase or program delay. 5. Read ...
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ALTERNAfliiE CE#-CONTROLLED Vcc=5V*0.5V, NOTES systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold and inactive WE# times should be measured relative to the CE# waveform. 2. Sampled, not 100% ...
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... SHARP -- r ADDRESSES(A) WE#(W) OE#(G) CE#(E) DATA( D/Q) 4 STS(R) WP#(S) NOTES: 1. Vcc power-up and standby. 2. Write erase or write setup. 3. Write erase confirm or.valid address 4. Automated erase or pragram delay. 5. Read status,register data. 6. Write ReadArray command. 7. CE# is defined as the latter of CEO# and CE,# going Low or the first of CEo# or CE1# going High. ...
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SHARI 6.2.7 RESET OPERATIONS High Z STS(R) VOL VIH RP#(P) VIL High Z STS( R) VOL VIH RP vcc VIL VIH RP#(P) VIL Figure 21. AC Waveform for Reset Operation I. Parameter Symbol ...
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... SHARP - 6.2.8 BLOCK EFiiSE, FULL LOCK-BIT CONFIGURATION t WKM Set Block Lock-Bit Time tfH(J”g t WI-K&M Clear Block Lock-Bits Time tFHn”d ‘WHnHl Write Suspend Latency Time to Read f&qqRH, pHnr-f2 Erase Suspend Latency Time to Read FHRH? NOTES: 1. Typical values measured at TA=+25”C and nominal voltages. Assumes corresponding block lock-bits are not set ...
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... IL/H~2181FI1/6/O/S15~H1/NSI-/L17lO~ Device Density 160 = 16-Mbit Architecture S = Regular Block Power Supply Type 5 = Smart 5 Technology Operating Temperature Blank = 0°C - +7O” -40°C - +85”C Jption Order Code 1 LH28F160S5NS-L70 .I’ LHFlGKA4 u P- Package T = 56-Lead TSOP R = 56-Lead TSOP(Reverse Bend 56-Lead SSOP B = 64-Ball CSP :,, 64-Lead SDIP Valid Operational v~~=5v*o ...
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SHARI= Flash memory LI@XXKXX family Noises having a level exceeding generated under specific operating Such noises, when induced onto WE# signal or power supply, commands, caus ing undesired To protect the data stored operating with the flash memory should have ...
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... SHARP -- - LH28F16OSXX-LXX Flash MEMORY ERRATA 1. Multi Word/Byte Write Operations PROBLEM; When two planes of 32-byte page buffer are both in full and first buffer data are being written to the flash array, the extended status register bit XSR.7 may be erroneously set to “l”, which indicates the Multi Word/Byte Write command is available ...
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... SHARP .- -- - LH28Fl6OSXX-LXX Flash MEMORY ERRATA Use One Page Buffer Use Two Page Buffers .,.’ No Multi Word/Byte Command Sequence Full Status check if desired 1 LHF16KA4 Multi Command Sequence Write E8H + I Read XSR Write Write Buffer Data, Device Address 48 I ...
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... SHARP _- RELATED DOCUhiEkT INFORMATIOti’) Document No. Flash AP-#l-SD-E Data Protection Method of SHARP Flash Memory AP-006-P-r-E I-- I RP#, Vpp Electric Potential Switching Circuit AP-O07SW-E NOTE : 1. International customers should contact their local SHARP or distribution sales o5ce. Document Name Memory Family Software Drivers -1 ...
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SHARI= IPRELlh,llNARy DETAIL ‘ {Yk / TIN-LEAC M SSOP56-P-600 LEAD FINISH i PLATING NOTE Plastic 4m [ MAWING NO. i AA2021 UNIT j PIG. A l7Xir 1h?-:iM%ft, 4 ~2Z?#~dtt4 D body dimensions do not ...