SDA9361 Siemens Semiconductor Group, SDA9361 Datasheet
SDA9361
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ICs for Consumer Electronics DDC-PLUS-Deflection Controller SDA 9361 Data Sheet 1998-02-01 ...
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Edition 1998-02-01 This edition was realized using the software system FrameMaker Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third ...
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SDA 9361 Revision History: Previous Version: Page Page (in previous (in current Version) Version Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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DDC-PLUS-Deflection Controller 1 Overview 1.1 Features • Deflection - Protection - 16:9 / 4:3 • No external clock needed • PLL and PLL on chip 2 • C-Bus alignment of all deflection parameters • All EW-, V- and H- functions ...
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Protection against missing V-deflection (CRT-protection) • Selectable softstart of the H-output stage • Clock generation on chip • P-MQFP-44-2 package • supply voltage 1.2 General Description The SDA 9361 is a highly integrated deflection controller for CTV ...
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Pin Description Pin No. Symbol Type 1 CLKI I/TTL SDAT IQ 5 SCLK I 6 RESN I/TTL 7 SCAN Q/TTL 8 SCP DD( SS(D) 11 ...
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Pin Description (cont’d) Pin No. Symbol Type 28 VSYNC I/TTL TEST I/TTL 31 FH1_2 I/TTL 32 CLEXT I/TTL 33 SELFH1_2 I/TTL DD(A3) 35 HSYNC REFC ...
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Block Diagram SCLK 2 C SDAT VOFFD SELFH1_2 FH1_2 TEST Control CLEXT VSYNC HSYNC CLL CLKI PLL Figure 2 Semiconductor Group SCP SCAN HPROT SSD VPROT Protection Start REFC REFL REFH ...
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System Description 2.1 Functional Description The main input signals are HSYNC with standard or doubled horizontal frequency and VSYNC with vertical frequencies of 50/100 Hz or 60/120 Hz. The VSYNC is processed in a noise reduction circuit to enable ...
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VPROT: Vertical saw-tooth voltage V < first half of V-period > second half: HD disabled i The pin SCP delivers the composite blanking signal SCP. It contains burst ( V blanking HBL ( ...
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Circuit Description The HSYNC is reference for a numeric PLL. This PLL generates a clock which is phase locked to the incoming horizontal sync pulse and exactly 864 times faster then the horizontal frequency. In order to lock the ...
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By means of digital PI filtering an increment is gained from this. The PI filter can 2 be set by the C-Bus VCR bit so that the lock-in behavior of the PLL is optimal in relation to either the ...
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Reset Modes The circuit is completely reset at power-on/off (timing diagram see figure 11 the pin RESN has L-level (timing diagram see figure 12). During standby operation some parts of the circuit are not affected (timing diagram ...
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Frequency Ranges H 15.625 kHz 15.75 kHz 31.25 kHz 31.5 kHz 32.4 kHz 1) 33.75 kHz 1) 35 kHz 1) Only with internal clock generation The allowed deviation of all input line frequencies is max. ± 4 ...
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C-Bus Control I 2 2.5.1 I C-Bus Address 2.5.2 I C-Bus Format write read ...
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I C-Bus Commands Control item Allowed Deflection control Deflection control Vertical shift -128..127 -128..127 H ...
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The effective range for Vertical Blanking Time: 16 ... 127 (absolute value) 0 ... 127 (offset value) b) The "default value if disabled" for Vertical Blanking Time: 21 (absolute value)if STE = 0 8 (offset value)if STE = 1. ...
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STDBY: Stand-by mode 0: normal operation 1: stand-by mode (all internal clocks are disabled) 2FH: Setting of line frequency 0: low range of line frequency (14900 Hz ... 17650 Hz) 1: high range of line frequency (29800 Hz ... 35300 ...
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STE: Scan time enable 0: control items for vertical scan width 0 and width 1 are disabled 1: control items for vertical scan width 0 and width 1 are enabled GBE: Guard band enable 0: control item for guard band ...
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NL2 ... NL0: Number of lines per field when and no vertical sync at the input is detected NL2 NL1 The Internal PLL Control Byte includes the ...
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GENMOD = 0: GENMOD = 1: (FQ = 24.576 MHz) Application PAL NTSC PAL (100 Hz) NTSC (120 Hz) ATV MUSE Macintosh Default value: INCR = 6 Warning: 1)A change of INCR or 2FH causes spontaneous changes ...
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The Universal Register 1 (Subaddress NOISY NOISYVCR: Handling of noisy input signals in VCR mode 0: normal handling 1: improved handling Note: this bit is don’t care if bit VCR = 0 (TV mode) The Universal Register ...
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BANDG4OFF must BANDG4OFF: Bandgap 4 V Off 0: internal bandgap reference is used for 1: external reference on The Status Byte includes the following bits: HPON VPON HPON: protection on ...
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Vertical Scan (width0 and width1) The total width of this control item is 10 Bit. Therefore two registers (width0 and width1) are necessary. If enabled (STE = 1) it defines the duration of the vertical scan. When the vertical period ...
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Vertical EHT Compensation This item controls the influence of the beam current dependent input signal ABL on the outputs VD+ and VD- according to the following equation: Vertical EHT compensation = ----------------------------------------------------------------------- - * 0, VDPP ABL ...
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Additional to the control items Vertical angle, Vertical bow and Horizontal shift, this product influences the horizontal phase at the output HD according to the following equation: AFC EHT compensation = --------------------------------------------------------------- - * V * ABL AFC EHT compensation ...
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HSYNC VSYNC Start of odd Field VD- VBL (BSE = 0) VBL (BSE = 1, VBT = 16) 2 Lines VBL (BSE = 1, VBT = 25) 3 Lines VBL (BSE = 1, VBT = 26) Figure 5 Vertical Blanking ...
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Field = Constant b) Case of STE = 1 In this case the control item Vertical blanking time is an extension for the V-blanking pulse BSE = 1 and VBT = 0 the V-blanking pulse has its minimum: ...
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Minimum Number of Lines per Field It defines the minimum number of lines per field for the vertical synchronisation. If the TV standard at the inputs VSYNC and HSYNC has less lines per field than defined by Minimum Number of ...
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Most Important V-Deflection Modes for 4:3 CRT Description Characteristics N0 Normal mode Self adaptation (for 4:3 source, scan start = line 9 Letterbox) start of V-ramp = line 9 with default scan time: depends on source signal settings guard band ...
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Most Important V-Deflection Modes for 16:9 CRT Description Characteristics N0 Normal mode Self adaptation (for 16:9 or scan start = line 9 4:3 source) start of V-ramp = line 9 with default scan time: depends on source signal settings guard ...
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Absolute Maximum Ratings Parameter Operating temperature Storage temperature Junction temperature Soldering temperature Input voltage Output voltage Supply voltages Supply total voltage differentials Total power dissipation Latch-up protection 1) Between any internally non-connected supply pin of the same kind. All ...
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Recommended Operating Conditions Parameter Symbol Supply voltages V T Ambient temperature TTL Inputs: CLKI, VSYNC, TEST, FH1_2, SELFH1_2, CLEXT, SSD, VOFFD, RESN V H-input voltage V L-input voltage Input VPROT Threshold V1 Threshold V2 Input HPROT Threshold V1 Threshold ...
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Recommended Operating Conditions (cont’d) Parameter Symbol Input 2 V L-input voltage V H-input voltage Input HSYNC (CLEXT = 0) Input voltage range V V Input voltage low level V Input voltage high level Pulse width t w (HSWID = ...
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Recommended Operating Conditions (cont’d) Parameter Symbol Input CLKI (External Clock Generation, CLEXT = High) f Input frequency I Quartz Oscillator Input / Output X1, X2 Crystal frequency Crystal resonant impedance External capacitance 2 C Bus (All Values are Referred ...
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Characteristics (Assuming Recommended Operating Conditions) Parameter Symbol Average supply I CC current Stand-by supply current Output Pins: SCAN, PWM V Output low level V Output high level Input / Output SDAT V Output low level Output SCP Output low ...
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Characteristics (Assuming Recommended Operating Conditions) (cont’d) Parameter Symbol DAC output high C Load capacitance Output load Zero error Gain error INL DNL 2 1.2 V REFH REFL 2 ...
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Characteristics (Assuming Recommended Operating Conditions) (cont’d) Parameter Symbol Reference Output V REFP ( Reg 48 , Bit Bit Output voltage min Output voltage max I Output current Q V Reference Output REFH ...
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Application Information 2 TV Contr. C NVM 24.576 MHz VSYNC Source Sel HSYNC Synch Sep LF Figure 7 Semiconductor Group HD SDA 9361 E/W VD- VD+ VPROT 40 SDA 9361 V EHT B ...
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Waveforms 5.1 VD- Output Voltage, 4/3-CRT and 16/9-Source V VD- V 0(max) V 0(min) 2 SRS 0 SRSE = 1 Start Reduced Scan (SRS) selectable (line 0, 2...63) Figure 8 Semiconductor Group ...
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Timing Diagram of SCAN HSYNC (odd field) HSYNC (even field (internal) d0 VSYNC VBL (BSE = 0) 1 Line VD- (SSE = 0) appr. 8.5 Lines SCAN (SSE = 0) ...
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HSYNC (odd field) HSYNC (even field (internal) VSYNC VD- VBL (BSE = 0) 4 Lines SCAN Figure 10 Timing Diagram of SCAN if STE = 1 Semiconductor Group Line ...
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Power On/Off Diagram Supply Voltage Power- On- Reset 32 Cycles X1, X2 SSD = 0: ~ 250 SSD = 1: ~ 380 HD 2 Tristate C Bus V , REFP V , REFH V REFL Active Protection Inactive 2 ...
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Standby Mode, RESN Diagram Standby RESN HD 2-Loop Active CPU Inactive Active V , REFP V , Inactive REFH V REFL Active Protection Inactive 2 C Bus 2 C Reg. Programmable 01 ... ...
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Function of H,V Protection HPROT ... Depends on ...
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Package Outlines P-MQFP-44-2 (Plastic Metric Quad Flat Package) 0.8 0.3 +0. Index Marking 1) Does not include plastic or metal protrusions of 0.25 max per side Figure 13 Sorts of Packing Package outlines for tubes, trays ...