CY7C1340A-66AI Cypress Semiconductor Corporation., CY7C1340A-66AI Datasheet

CY7C1340A-66AI

Manufacturer Part Number

CY7C1340A-66AI

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY7C1340A-66AI.pdf (12 pages)

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Cypress Semiconductor Corporation

Document #: 38-05153 Rev. *C

Features

Selection Guide

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

• Fast access times: 5 and 7 ns

• Fast clock speed: 100 and 66 MHz

• Provides high-performance 3-1-1-1 access rate

• Fast OE access times: 5 and 7 ns

• Optimal for performance (two-cycle chip deselect,

• Single +3.3V –5% and +10%power supply

• Supports +2.5V I/O

• 5V tolerant inputs except I/Os

• Clamp diodes to V

• Common data inputs and outputs

• Byte Write Enable and Global Write control

• Three chip enables for depth expansion and address

• Address, control, input, and output pipeline registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst

• Automatic power-down for portable applications

• High-density, high-speed packages

• Low-capacitive bus loading

• High 30-pF output drive capability at rated access time

depth expansion without wait state)

pipeline

sequence)

SSQ

at all outputs

•

128K x 32 Synchronous-Pipelined RAM

3901 North First Street

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced

triple-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high valued

resistors.

The CY7C1340A/GVT71128C32 SRAM integrates 131,072 ×

32 SRAM cells with advanced synchronous peripheral circuitry

and a two-bit counter for internal burst operation. All

synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

inputs include all addresses, all data inputs, address-pipelining

chip enable (CE), depth-expansion Chip Enables (CE2 and

CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write

Enables (BW1, BW2, BW3, BW4, and BWE), and Global Write

(GW).

Asynchronous inputs include the Output Enable (OE) and

Burst Mode Control (MODE). The data outputs (Q), enabled

by OE, are also asynchronous.

Addresses and chip enables are registered with either

Address Status Processor (ADSP) or Address Status

Controller (ADSC) input pins. Subsequent burst addresses

can be internally generated as controlled by the Burst Advance

Pin (ADV).

Address, data inputs, and Write controls are registered on-chip

to initiate self-timed Write cycle. Write cycles can be one to

four bytes wide as controlled by the Write control inputs.

Individual byte Write allows individual byte to be written. BW1

controls DQ1–DQ8. BW2 controls DQ9–DQ16. BW3 controls

DQ17–DQ24. BW4 controls DQ25–DQ32. BW1, BW2, BW3,

and BW4 can be active only with BWE being LOW. GW being

LOW causes all bytes to be written. This device also incorpo-

rates pipelined enable circuit for easy depth expansion without

penalizing system performance.

The CY7C1340A/GVT71128C32 operates from a +3.3V

power supply. All inputs and outputs are TTL-compatible. The

device is ideally suited for 486, Pentium®, 680 × 0, and

PowerPC™ systems and for systems that benefit from a wide

synchronous data bus.

7C1340A-100

225

•

San Jose

CA 95134

7C1340A-66

120

Revised March 31, 2004

•

CY7C1340A

408-943-2600

Unit

Related parts for CY7C1340A-66AI

CY7C1340A-66AI Summary of contents

Page 1

... Each memory cell consists of four transistors and two high valued resistors. The CY7C1340A/GVT71128C32 SRAM integrates 131,072 × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK) ...

Page 2

... The functional block diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. Document #: 38-05153 Rev. *C BYTE 1 WRITE D Q BYTE 2 WRITE D Q BYTE 3 WRITE D Q BYTE 4 WRITE D Q ENABLE Input Register Address Register CLR Binary Counter & Logic CY7C1340A OUTPUT REGISTER DQ1 DQ32 Page ...

Page 3

... CLK. Global Write: This active LOW input allows a full 32-bit Write to occur independent of the BWE and BWn lines and must meet the set-up and hold times around the rising edge of CLK. CY7C1340A NC 80 ...

Page 4

... No Connect: These signals are not internally connected. ) Burst Address Table (MODE = GND) CC Fourth First Address Address (internal) (external) A...A11 A...A00 A...A10 A...A01 A...A01 A...A10 A...A00 A...A11 CY7C1340A Description . CC Second Third Address Address (internal) (internal) A...A01 A...A10 A...A10 A...A11 A...A11 A...A00 A...A00 A...A01 ...

Page 5

... BWE BW1 CY7C1340A ADSC ADV WRITE OE CLK ...

Page 6

... Device deselected; all inputs < V inputs static Max.; CLK frequency = 0 CC Device deselected; all inputs < Max.; CLK cycle time > Description Test Conditions T = 25qC MHz 3.3V CC Description CY7C1340A Ambient [9] Temperature 0°C to +70°C 3.3V5%/+10% –40°C to +85°C Min. Max. 2.0 V CCQ 2.0 4.6 –0.3 0.8 –2 2 < ...

Page 7

... Description [23, 24] [23, 24] [25] [23, 24] [23, 24] [26] [26] is less than t and t is less than t KQHZ KQLZ OEHZ CY7C1340A TQFP Typ 200us 90% Vddtyp 10% Vddm in d 1.5 ns (c) (d) ALL INPUT PULSES 2.5V 90 100 MHz 66 MHz Min ...

Page 8

... OELZ KQLZ xxxxx xxxxxx xxxxxx xxxxx xxxxxx xxxxxx xxxxx Q(A1) xxxxxx Q(A2) xxxxxx xxxxx xxxxxx xxxxxx xxxxx xxxxxx xxxxxx SINGLE READ CY7C1340A xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxxx xxxxxxxxx ...

Page 9

... OEHZ xxxxxxxxxxxxxxx xxxxxxxxxxxxxxx xxxxxxxxxxxxxxx D(A1) D(A2) D(A2+1) D(A2+1) xxxxxxxxxxxxxxx xxxxxxxxxxxxxxx SINGLE WRITE BURST WRITE CY7C1340A xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx ...

Page 10

... ADV# xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx OE# DQ Ordering Information Speed (MHz) Ordering Code 100 CY7C1340A-100AC 66 CY7C1340A-66AI Document #: 38-05153 Rev. *C xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx t H xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ...

Page 11

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1340A 51-85050-*A ...

Page 12

... Document History Page Document Title: CY7C1340A 128K × 32 Synchronous-Pipelined RAM Document Number: 38-05153 REV. ECN NO. Issue Date ** 109897 09/22/01 *A 111530 02/06/02 *B 123139 01/19/03 *C 212291 See ECN Document #: 38-05153 Rev. *C Orig. of Change SZV Changed from Spec number: 38-01003 to 38-05153 GLC Added industrial temp to data sheet RBI Added power up requirements to operating conditions information ...

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