DSP56301 Freescale Semiconductor, Inc, DSP56301 Datasheet

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... DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The DSP56301 offers 80/100 MIPS using an internal 80/100 MHz clock at 3.0–3.6 volts. The DSP56300 core family offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power, enabling wireless, telecommunications, and multimedia products. © ...

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... Logic State Signal State True Asserted False Deasserted True Asserted False Deasserted are defined by individual product specifications DSP56301 Technical Data, Rev. 10 pin is active when RESET Voltage Freescale Semiconductor ...

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... X Data RAM Size Y Data RAM Size Size 2048 × 24 bits 0 1024 × 24-bit 2048 × 24 bits 3072 × 24 bits 0 1024 × 24-bit 3072 × 24 bits DSP56301 Technical Data, Rev. 10 Instruction Switch Cache Mode 2048 × 24 bits disabled disabled 2048 × 24 bits enabled disabled 3072 × ...

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... Fully static design specified to operate down (dc) • Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent) Packaging The DSP56301 is available in a 208-pin thin quad flat pack (TQFP 252-pin molded array process-ball grid array (MAP-BGA) package. Both packages are available in lead-bearing and lead-free versions. Target Applications Examples of target applications include: • ...

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... Signals/Connections The DSP56301 input and output signals are organized into functional groups, as shown in Table 1-1 and illustrated in Figure 1-1. The DSP56301 operates from supply; however, some of the inputs can tolerate special notice for this feature is added to the signal descriptions of those inputs. ...

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... Serial Communications 3 Interface (SCI) Port TIO0 4 Timers TIO1 TIO2 JTAG/OnC E Port pins that connect to an internal power plane. The MAP- CC Signals Identified by Functional Group DSP56301 Technical Data, Rev. 10 MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD RESET Universal Port B Bus GPIO PCI Bus Port C GPIO SC[00-02] PC[0-2] ...

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... HAD28 HD20 HAD29 HD21 HAD30 HD22 HAD31 HD23 HRST HRST HINTA HINTA PVCL Leave unconnected Host Interface/Port B Detail Signal Diagram DSP56301 Technical Data, Rev. 10 Host Port (HP) Port B GPIO Reference PB0 HP0 PB1 HP1 PB2 HP2 PB3 HP3 PB4 HP4 PB5 HP5 ...

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... The user must provide adequate external decoupling capacitors. 1-4 Table 1-2. Power Inputs Description power rail. CC inputs except V CC are labeled V . CCP CC Table 1-3. Grounds Description by a 0.47 μF capacitor located as close as possible to the chip package. P DSP56301 Technical Data, Rev each other internally. On CCP Freescale Semiconductor ...

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... If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL. PLL Capacitor Connects an off-chip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal the PLL is not used, PCAP can be tied to V DSP56301 Technical Data, Rev. 10 and GND to each other P P1 are labeled GND ...

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... Input Input 1.5 External Memory Expansion Port (Port A) Note: When the DSP56301 enters a low-power stand-by mode (Stop or Wait), it releases bus mastership and tri- states the relevant Port A signals hardware refresh of external DRAM is enabled, Port A exits the Wait mode to allow the refresh to BCLK occur and then returns to the Wait mode ...

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... Otherwise tri-stated. Transfer Acknowledge If the DSP56301 is the bus master and there is no external bus activity, or the DSP56301 is not the bus master, the TA input is ignored. The TA input is a Data Transfer Acknowledge (DTACK) function that can extend an external bus cycle indefinitely ...

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... When BCLK is active and synchronized to CLKOUT by the internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle. Bus Clock Not When the DSP is the bus master, BCLK is the inverse of the BCLK signal. Otherwise, the signal is tri-stated. DSP56301 Technical Data, Rev. 10 Signal Description Freescale Semiconductor ...

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... CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQC to exit the Wait state. If the processor is in the Stop stand-by state and IRQC is asserted, the processor exits the Stop state. These inputs are 5 V tolerant. DSP56301 Technical Data, Rev. 10 Interrupt and Mode Control Signal Description 1-9 ...

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... When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted after power-up. This input tolerant. Host Port Usage Considerations Description DSP56301 Technical Data, Rev. 10 Signal Description Freescale Semiconductor ...

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... The fourth signal in this set should connect to a pull-up resistor or directly to V when a non-PCI bus is used. CC Port B 16–19 When the HI32 is configured as GPIO through the DCTR, these signals are individually programmed through the HI32 DIRH. These inputs are 5 V tolerant. DSP56301 Technical Data, Rev. 10 Host Interface (HI32) Signal Description 1-11 ...

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... When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Bus Strobe Schmitt-trigger signal. Port B 23 When the HI32 is configured as GPIO through the DCTR, this signal is individually programmed through the HI32 DIRH. This input tolerant. DSP56301 Technical Data, Rev. 10 Signal Description Freescale Semiconductor ...

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... HI function is selected, this is the Host Data Bus Enable signal. HTA can be programmed as active high or active low. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input tolerant. DSP56301 Technical Data, Rev. 10 Host Interface (HI32) Signal Description 1-13 ...

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... When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this signal must be connected to a pull-up resistor or directly Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input tolerant. DSP56301 Technical Data, Rev. 10 Signal Description Freescale Semiconductor ...

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... PCI bus uses signal environment, connect this pin enable the high voltage clamping required by the PCI CC specifications. In all other cases, including PCI signal environment, leave the input unconnected. DSP56301 Technical Data, Rev. 10 Host Interface (HI32) Signal Description 1-15 ...

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... Port C 2 The default configuration following reset is GPIO. For PC2, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SC02 through PCR0. This input tolerant. DSP56301 Technical Data, Rev. 10 Signal Description Freescale Semiconductor ...

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... Transmits data from the serial transmit shift register. STD0 is an output when data is being transmitted. Port C 5 The default configuration following reset is GPIO. For PC5, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal STD0 through PCR0. This input tolerant. DSP56301 Technical Data, Rev. 10 Signal Description 1-17 ...

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... The ESSI needs at least three DSP phases inside each half of the serial clock. Port D 3 The default configuration following reset is GPIO. For PD3, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SCK1 through PCR1. This input tolerant. DSP56301 Technical Data, Rev. 10 Signal Description Freescale Semiconductor ...

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... The default configuration following reset is GPIO. When configured as PE1, signal direction is controlled through the SCI PRR. The signal can be configured as an SCI signal TXD through the SCI PCR. This input tolerant. DSP56301 Technical Data, Rev. 10 Serial Communication Interface (SCI) Signal Description Signal Description ...

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... SCLK Input/Output Input PE2 Input or Output 1.11 Timers The DSP56301 has three identical and independent timers. Each can use internal or external clocking, interrupt the after a specified number of events (clocks), or signal an external device after counting a specific number DSP56301 of internal events. Signal Name Type ...

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... OnCE module to initiate Debug mode directly or to provide a direct external indication that the chip has entered the Debug mode. All other interface with the OnCE module must occur through the JTAG port. This input tolerant. DSP56301 Technical Data, Rev. 10 JTAG/OnCE Interface Signal Description 1-21 ...

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... Signals/Connections 1-22 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

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... Specifications The DSP56301 is fabricated in high-density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs. 2.1 Maximum Ratings This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if ...

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... Table 2-2. Thermal Characteristics Symbol or θ R θ θ R θJC JC Ψ JT Table 2-3. DC Electrical Characteristics Symbol Min V 3.0 CC DSP56301 Technical Data, Rev Value –0.3 to +4.0 GND – 0 0.3 CC GND – –40 to +100 –55 to +150 3 4 TQFP PBGA PBGA Value Value Value 49 ...

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... the high V value may cause additional power consumption (DC current). To minimize IHX ILX should be no lower than IHX should be no higher than 0.1 × ILX CC DSP56301 Technical Data, Rev Electrical Characteristics 6 (Continued) Typ Max — — 5.25 — — ...

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... ET PDF × DF/ 0.49 × ET PDF × DF/MF 0.47 × ET PDF × DF/ — CYC = External clock cycle = 1/Ef Internal clock cycle C DSP56301 Technical Data, Rev. 10 maximum of 0 Expression Min Typ Max (Ef × MF)/ — — (PDF × DF) — Ef/2 — — ET — C × ...

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... External Clock Operation The DSP56301 system clock is derived from the on-chip oscillator externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; examples are shown in Figure 2-1. EXTAL XTAL R C XTAL1 C Fundamental Frequency Crystal Oscillator If an externally supplied square wave voltage source is used, disable the internal oscillator circuit during boot-up by setting XTLD (PCTL Register bit 16 = 1— ...

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... ET 3,5 I CYC Table 2-6. PLL Characteristics 80 MHz Min Max 30 160 ) ) (C PCAP (MF × 580) − (MF × 780) − 100 140 MF × 830 MF × 1470 DSP56301 Technical Data, Rev MHz 100 MHz Min Max Min 0 80.0 MHz 0 ∞ 5. 157.0 μs 5.31 ns 4.25 ns ∞ 5. 157.0 μ ...

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... MHz: 3.75 × × T – 10. MHz: 3.25 × × T – 12 100 MHz: 3.25 × × T – 10. DSP56301 Technical Data, Rev Electrical Characteristics 6 80 MHz 100 MHz Unit Min Max Min Max — 26.0 — 26.0 ns 625.0 — 500.0 — ...

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... C PLC/2) × PLC × ET × PDF + C (20.5 ± 0.5) × T 5.5 × × × × × DSP56301 Technical Data, Rev (Continued) 80 MHz 100 MHz Min Max Min Max — Note 8 — Note 8 — Note 8 — Note 8 — ...

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... MF) divided by the desired internal frequency (that is, for 66 MHz and T is not constant, and their width may vary, so timing may pF Reset Value Figure 2-3. Reset Timing DSP56301 Technical Data, Rev Electrical Characteristics 6 (Continued) 80 MHz 100 MHz Unit Min Max Min Max — 75.0 — 60.0 ns — ...

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... RD WR IRQA, IRQB, IRQC, IRQD, NMI General Purpose I/O IRQA, IRQB, IRQC, IRQD, NMI 2- Figure 2-4. Synchronous Reset Timing First Interrupt Instruction Execution/Fetch First Interrupt Instruction Execution 18 b) General-Purpose I/O Figure 2-5. External Fast Interrupt Timing DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

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... MODA, MODB, MODC, MODD, PINIT Freescale Semiconductor 15 16 External Interrupt Timing (Negative Edge-Triggered) 22 Synchronous Interrupt from Wait State Timing Figure 2-8. Operating Mode Select Timing DSP56301 Technical Data, Rev Electrical Characteristics IRQA, IRQB, IRQC, IRQD, NMI V IL 2-11 ...

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... Recovery from Stop State Using IRQA 26 25 Recovery from Stop State Using IRQA Interrupt Service DMA Source Address 29 First Interrupt Instruction Execution External Memory Access (DMA Source) Timing DSP56301 Technical Data, Rev. 10 First Instruction Fetch First IRQA Interrupt Instruction Fetch Freescale Semiconductor ...

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... WS ≤ 2.75 × T − 4.0 [WS ≥ 0.5 × T − 4.0 [ − 4.0 [2 ≤ WS ≤ 2.5 × T − 4.0 [4 ≤ WS ≤ 3.5 × T − 4.0 [WS ≥ DSP56301 Technical Data, Rev Electrical Characteristics 3,6 80 MHz 100 MHz Unit Min Max Min Max 21.0 — 16.0 — ns 71.0 — ...

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... WS ≤ 1.25 × T − 2.0 [4 ≤ WS ≤ 2.25 × T − 2.0 [WS ≥ 0.25 × 2 100 113 116 105 104 Figure 2-12. SRAM Read Access DSP56301 Technical Data, Rev. 10 (Continued) 80 MHz 100 MHz Unit Min Max Min Max 2.3 — 1.0 — ns 11.6 — 8.5 — ns 1.1 — ...

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... Note: Address lines A[0–23] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Freescale Semiconductor 100 107 101 102 114 108 Figure 2-13. SRAM Write Access DSP56301 Technical Data, Rev Electrical Characteristics 103 119 118 109 Data Out 2-15 ...

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... Figure 2-14. 2-16 Note: This figure should be used for primary selection. For exact and detailed timings see the following tables. 120 66 80 100 3 Wait states 4 Wait states DRAM Page Mode Wait States Selection Guide DSP56301 Technical Data, Rev. 10 Chip frequency (MHz) Freescale Semiconductor ...

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... The number of wait states for Page mode access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. The asynchronous delays specified in the expressions are valid for the DSP56301. 4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example for read-after-read or write-after-write sequences) ...

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... The number of wait states for Page mode access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. The asynchronous delays specified in the expressions are valid for DSP56301. 4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example for read-after-read or write-after-write sequences) ...

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... The number of wait states for Page mode access is specified in the DCR. 2. The refresh period is specified in the DCR. 3. The asynchronous delays specified in the expressions are valid for DSP56301. 4. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example × T for read-after-read or write-after-write sequences) ...

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... Column Column Address Address 143 132 133 153 154 Data In Data In DRAM Page Mode Read Accesses DSP56301 Technical Data, Rev. 10 136 135 138 142 Last Column Address 147 148 156 Data Out 136 135 138 142 Last Column ...

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... RAC t CAC OFF RAS t RSH t CSH t CAS t RCD t RAD t CRP ASR DSP56301 Technical Data, Rev Electrical Characteristics Chip Frequency (MHz MHz Expression Unit Min Max 9 × T 112.5 — 4.75 × T − 6.5 — 52 2.25 × T − 6.5 — 21 × ...

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... RRH t WCH t WCR RWL t CWL DHR t WCS t CSR t RPC t ROH DSP56301 Technical Data, Rev (Continued) 80 MHz Expression Unit Min Max 1.75 × T − 4.0 17.9 — 0.75 × T − 4.0 5.4 — 3.25 × T − 4.0 36.6 — 5.75 × T − 4.0 67.9 — ...

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... T t WCH 7.5 × WCR 11.5 × 11.75 × RWL 10.25 × CWL 5.75 × 5.25 × DSP56301 Technical Data, Rev Electrical Characteristics MHz 100 MHz Min Max Min Max 150.0 — 120.0 — C − 6.5 — 71.6 — — C − 7.0 — ...

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... T t RAS 6.25 × RSH 8.25 × CSH 4.75 × CAS 3.5 × RCD 2.75 × RAD 7.75 × CRP DSP56301 Technical Data, Rev (Continued) 80 MHz 100 MHz Min Max Min Max − 4.0 92.9 — 73.5 — C − 4.3 77.0 — 60.7 — C − 4.0 14.8 — ...

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... WCS 1.5 × CSR 4.75 × RPC 15.5 × ROH t 80 MHz × T 100 MHz: 14 × 0.75 × T 0.25 × T DSP56301 Technical Data, Rev Electrical Characteristics 1, 2 (Continued) 80 MHz 100 MHz Min Max Min Max – 6.0 74.1 — 56.5 — C − 4.0 74.1 — 58.5 — ...

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... Row Address Column Address 172 177 191 160 159 158 192 DRAM Out-of-Page Read Access DSP56301 Technical Data, Rev. 10 157 162 164 174 176 179 178 193 161 Data In Freescale Semiconductor ...

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... DRAM Out-of-Page Write Access 157 162 163 190 170 165 189 177 Figure 2-20. DRAM Refresh Access DSP56301 Technical Data, Rev Electrical Characteristics 157 162 164 166 174 176 Column Address 175 180 186 195 Data Out ...

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... T + 4.5 C 100 MHz: 0.25 × 4.0 C 0.25 × MHz: 0.25 × 0.5 C 100 MHz: 0.25 × maximum: 0.75 × 2.5 C 0.5 × 4 ≥ ≤ WS ≤ 3] DSP56301 Technical Data, Rev MHz 100 MHz Unit Min Max Min Max 2.6 8.3 2.0 7.7 ns 8.4 13.6 6.5 11.7 ns — 5.6 — 5.0 ns 2.4 — ...

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... Data Out 208 202 206 Synchronous Bus Timings 1 WS (BCR Controlled) 201 200 203 Data Out 202 206 Synchronous Bus Timings 2 WS (TA Controlled) DSP56301 Technical Data, Rev Electrical Characteristics 199 201 2 00 211 205 204 209 207 Data In 199 201 ...

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... T212 is valid for Address Trace mode when the ATE bit in the Operating Mode Register is set deasserted for internal accesses and asserted for external accesses. 2-30 Table 2-16. Arbitration Bus Timings 2 Expression 3 0.25 × 0.75 × 0.25 × maximum: 0.25 × 4.0 C 0.75 × DSP56301 Technical Data, Rev MHz 100 MHz Unit Min Max Min Max 1.0 4.5 0.0 4.0 ns 5.0 — 4.0 — ...

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... Figure 2-24. Bus Release Timings Case 1 (BRT Bit in Operating Mode Register Cleared) Freescale Semiconductor 212 213 215 Figure 2-23. Bus Acquisition Timings 213 212 218 223 DSP56301 Technical Data, Rev Electrical Characteristics 214 216 217 220 222 214 219 221 224 2-31 ...

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... In order to guarantee timings 250, and 251, BG inputs must be asserted to different DSP56300 devices on the same bus in the non-overlap manner shown in Figure 2-26. 2-32 214 213 221 223 Asynchronous Bus Arbitration Timing Expression 4 2.5 × × DSP56301 Technical Data, Rev. 10 219 218 224 1 MHz 100 MHz Unit Min Max Min Max — ...

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... MHz: 2.5 × T 100 MHz: 2.5 × MHz: 1.5 × T 100 MHz: 1.5 × MHz: 2 × 100 MHz: 2 × DSP56301 Technical Data, Rev Electrical Characteristics 251 . These BG is deasserted. Timing 250 BG input is asserted before that time, a input active is required MHz ...

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... T 1 2.5 × 1.5 × MHz: 2.5 × T 100 MHz: 2.5 × MHz: 2.5 × T 100 MHz: 2.5 × DSP56301 Technical Data, Rev MHz 100 MHz Min Max Min Max — 18.9 — 16.9 1.7 — 1.3 — — 12.0 — 9.6 8.3 — ...

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... MHz: 2.5 × MHz: 1.5 × T 100 MHz: 1.5 × 1,2 1,2 ( × 1.5 × MHz: 2.5 × T 100 MHz: 2.5 × T DSP56301 Technical Data, Rev Electrical Characteristics 80 MHz 100 MHz Min Max Min Max — 22.2 — 19.6 — 22.2 — 19.6 80 MHz ...

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... MHz: 2.5 × 2.5 × 2.5 × 301 305 307 308 310 309 329 328 330 Universal Bus Mode I/O Access Timing DSP56301 Technical Data, Rev MHz 100 MHz Unit Min Max Min Max + 24.7 — 55.9 + 21.5 — 46.5 31.3 — 25.0 — 31.3 — ...

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... HRST HI32 Outputs Freescale Semiconductor 336 305 334 333 Universal Bus Mode DMA Access Timing 303 Figure 2-29. HRW to HDS Timing 326 Figure 2-30. HIRQ Pulse Width (HIRH = 0) 346 Figure 2-31. HRST Timing DSP56301 Technical Data, Rev Electrical Characteristics 337 335 304 327 2-37 ...

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... HTA HD[23–0] HSAK 342 HDBDR HDBEN 338 2-38 306 309 307 310 322 321 323 311 Valid (Output) 312 313 318 343 339 Figure 2-32. Read Timing DSP56301 Technical Data, Rev. 10 324 325 315 314 319 345 344 341 340 Freescale Semiconductor ...

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... Figure 2-35. Freescale Semiconductor 306 309 307 310 322 321 323 324 Valid (Input) 318 316 339 Figure 2-33. Write Timing 347 Figure 2-34. HBS Synchronous Timing 348 Data Strobe Synchronous Timing DSP56301 Technical Data, Rev Electrical Characteristics 325 317 319 340 341 2-39 ...

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... SU t 10.0, 12.0 SU(ptp RST t 100.0 RST-CLK t RST-OFF t CYC t HIGH t LOW 359 361 360 349 350 351 352 353 354 Figure 2-36. PCI Timing DSP56301 Technical Data, Rev MHz 100 MHz Min Max Min Max 2.0 11.0 2.0 11.0 2.0 12.0 2.0 12.0 2.0 — 2.0 — — 28.0 — 28.0 7.0 — 7.0 — — 10.0, 12.0 — ...

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... T t SCC 8 × ACC C /2 − 10.0 t ACC /2 − 10.0 t ACC /2 − 30.0 t ACC /2 − 30.0 t ACC DSP56301 Technical Data, Rev Electrical Characteristics 358 80 MHz 100 MHz Min Max Min Max 100.0 — 80.0 — 40.0 — 30.0 — 40.0 — 30.0 — −17.0 14.3 — ...

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... Valid a) Internal Clock 400 402 401 407 408 Data Valid 409 410 Data Valid b) External Clock SCI Synchronous Mode Timing DSP56301 Technical Data, Rev MHz 100 MHz Unit Min Max Min Max ) C. is determined by the SCI clock ACC Freescale Semiconductor ...

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... Symbol Expression 3 × SSICC C 4 × × T − 10.0 C 1.5 × × T − 10.0 C 1.5 × DSP56301 Technical Data, Rev Electrical Characteristics 413 415 80 MHz 100 MHz Cond- ition Min Max Min Max 50.0 — 30.0 — 37.5 — 40.0 — 15.0 — ...

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... FST input (wl) setup time before TXC falling edge 461 FST input hold time after TXC falling edge 462 Flag output valid after TXC rising edge 2-44 Table 2-22. ESSI Timings (Continued) Symbol Expression DSP56301 Technical Data, Rev MHz 100 MHz Cond- 6 ition Min Max Min Max 6.0 — 6.0 — ...

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... If the DSP core writes to the transmit register during the last cycle before causing an underrun error, the delay (0.5 × Freescale Semiconductor Table 2-22. ESSI Timings (Continued) Symbol Expression = DSP56301 Technical Data, Rev Electrical Characteristics 80 MHz 100 MHz Cond- 6 ition Min Max Min Max Unit ...

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... Normal mode, the output flag state is asserted for the entire frame period. 2-46 430 432 446 447 450 454 454 452 First Bit 459 457 453 461 458 460 462 Figure 2-40. ESSI Transmitter Timing DSP56301 Technical Data, Rev. 10 451 455 Last Bit 456 461 See Note Freescale Semiconductor ...

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... Figure 2-41. ESSI Receiver Timing Table 2-23. Timer Timing Expression 2 × × 10.25 × T 0.5 × T 0.5 × DSP56301 Technical Data, Rev Electrical Characteristics 438 440 Last Bit 443 445 80 MHz 100 MHz Min Max Min Max + 2.0 27.0 — 22.0 — ...

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... TIO Timer Event Input Restrictions 482 First Interrupt Instruction Execution Figure 2-43. Timer Interrupt Generation 484 Figure 2-44. External Pulse Generation Table 2-24. GPIO Timing Expression 6.75 × DSP56301 Technical Data, Rev MHz 100 MHz Min Max Min Max + 0.5 9.8 — 5.5 — — 26.1 — ...

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... All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. Freescale Semiconductor 492 493 Valid 494 Figure 2-45. GPIO Timing Table 2-25. JTAG Timing 1,2 Characteristics × 3); maximum 22 MHz DSP56301 Technical Data, Rev Electrical Characteristics 490 491 All frequencies Unit Min Max 0.0 22.0 MHz 45.0 — ns 20.0 — ...

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... Output Data Valid Boundary Scan (JTAG) Timing Diagram 508 Input Data Valid 510 Output Data Valid 511 510 Output Data Valid Test Access Port Timing Diagram DSP56301 Technical Data, Rev. 10 502 V M 503 V IH 505 V IH 509 Freescale Semiconductor ...

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... TRST (Input) 2.5.12 OnCE Module TimIng No. Characteristics 500 TCK frequency of operation 514 DE assertion time in order to enter Debug mode 515 Response time when DSP56301 is executing NOP instructions from internal memory 516 Debug acknowledge assertion time = 3.3 V ± 0 −40°C to +100 °C, C Note ...

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... Specifications 2-52 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

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... Packaging This section provides information on the available packages for the DSP56301, including diagrams of the package pinouts and tables showing how the signals discussed in Section 1 are allocated for each package. The DSP56301 is available in two package types: • 208-pin Thin Quad Flat Pack (TQFP) • ...

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... STD0 SC00 SC01 SC02 DE TMS Orientation Mark TCK TDI TDO TRST Figure 3-1. 3-2 (Top View) DSP56301 Thin Quad Flat Pack (TQFP), Top View DSP56301 Technical Data, Rev MODB MODA D23 D22 D21 V CCD GND D D20 D19 D18 D17 D16 ...

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... A21 A20 A19 A18 V CCA GND A A17 A16 Figure 3-2. Freescale Semiconductor (Bottom View) DSP56301 Thin Quad Flat Pack (TQFP), Bottom View DSP56301 Technical Data, Rev. 10 TQFP Package Description 157 NC NC HAD11 HAD10 HAD9 HAD8 HC0 HAD7 HAD6 HAD5 HAD4 GND ...

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... GND P 14 GND CCN 19 GND N 20 AA2/RAS2 21 AA3/RAS3 XTAL 25 V CCQ 3-4 DSP56301 TQFP Signal Identification by Pin Number Pin Signal Name No. 26 EXTAL 27 GND Q 28 BCLK GND CCA GND ...

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... Table 3-1. DSP56301 TQFP Signal Identification by Pin Number (Continued) Pin Signal Name No GND CCQ 80 GND CCD D10 84 D11 85 D12 86 D13 87 D14 88 GND CCD 90 D15 91 D16 92 D17 93 D18 94 D19 95 D20 96 GND CCD 98 D21 99 D22 100 ...

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... Packaging Table 3-1. DSP56301 TQFP Signal Identification by Pin Number (Continued) Pin Signal Name No. 151 HAD15, HD7, or PB15 152 HAD14, HD6, or PB14 153 HAD13, HD5, or PB13 154 HAD12, HD4, or PB12 155 GND H 156 V CCH 157 NC 158 NC 159 HAD11, HD3, or PB11 160 HAD10, HD2, or PB10 ...

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... A21 62 A22 65 A23 AA0 AA1 AA2 20 Freescale Semiconductor DSP56301 TQFP Signal Identification by Name Signal Name AA3 BB BCLK BCLK CAS CLKOUT D0 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 ...

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... Packaging Table 3-2. DSP56301 TQFP Signal Identification by Name (Continued) Pin Signal Name No. GND 19 N GND 13 P GND 27 Q GND 78 Q GND 132 Q GND 183 Q GND 183 Q GND 180 S GND 194 S HA0 163 HA1 150 HA10 164 HA2 128 HA3 173 HA4 172 ...

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... Table 3-2. DSP56301 TQFP Signal Identification by Name (Continued) Pin Signal Name No. HD22 108 HD23 107 HD3 159 HD4 154 HD5 153 HD6 152 HD7 151 HD8 127 HD9 126 HDAK 145 HDBDR 133 HDBEN 134 HDEVSEL 138 HDRQ 141 HDS 129 HFRAME ...

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... Packaging Table 3-2. DSP56301 TQFP Signal Identification by Name (Continued) Pin Signal Name No. PC2 198 PC3 192 PC4 191 PC5 195 PCAP 12 PD0 187 PD1 186 PD2 185 PD3 189 PD4 190 PD5 188 177 PE0 PE1 184 PE2 178 PINIT 9 PVCL 137 ...

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... TQFP Package Mechanical Drawing 0 208 Pin 1 ident 0. View AA Figure 3-3. DSP56301 Mechanical Information, 208-pin TQFP Package Freescale Semiconductor 0 TIPS 157 156 M view 105 104 View AA Seating plane ( 0.08 ( 0.25 Gage ...

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... TDI NC BL CLK P TRST BS AA0 PINIT OUT AA1 CAS BCLK RESET PCAP Figure 3-4. DSP56301 Molded Array Process-Ball Grid Array (MAP-BGA), Top View 3-12 Top View HPERR HIRDY HAD16 HAD17 HAD20 HDEV HSERR HIDSEL HC2 HAD19 SEL H HC1 ...

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... V CC A18 NC A15 NC A12 NC NC A14 A11 A9 NC A13 A10 A7 Figure 3-5. DSP56301 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View Freescale Semiconductor Bottom View HAD20 HAD17 HAD16 HIRDY HPERR HPAR HIDSEL HDEV HSERR HRST HAD19 HC2 SEL H HC3 ...

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... B5 HRST/HRST B6 HSERR or HIRQ B7 HDEVSEL, HSAK, or PB22 B8 HIDSEL or HRD/HDS B9 HC2/HBE2, HA2, or PB18 B10 HAD19 or HD11 B11 HAD22 or HD14 3-14 DSP56301 MAP-BGA Signal Identification by Pin Number Pin Signal Name No. B12 HAD25 or HD17 B13 HAD29 or HD21 B14 HAD31 or HD23 B15 NC B16 NC C1 HAD8, HD0, or PB8 ...

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... Table 3-3. DSP56301 MAP-BGA Signal Identification by Pin Number (Continued) Pin Signal Name No. E14 MODA/IRQA E15 D22 E16 D21 F1 HAD1, HA4, or PB1 F2 HAD0, HA3, or PB0 F3 HAD3, HA6, or PB3 GND F7 GND F8 GND F9 GND F10 GND F11 GND F12 V CC F13 D18 ...

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... Packaging Table 3-3. DSP56301 MAP-BGA Signal Identification by Pin Number (Continued) Pin Signal Name No. K9 GND K10 GND K11 GND K12 V CC K13 V CC K14 D3 K15 D6 K16 D4 L1 SRD1 or PD4 L2 STD0 or PC5 L3 SC02 or PC2 L4 SC01 or PC1 GND L7 GND L8 GND L9 GND L10 ...

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... Table 3-3. DSP56301 MAP-BGA Signal Identification by Pin Number (Continued) Pin Signal Name No. R4 CAS R5 V CCP AA2/RAS2 R8 XTAL R9 BCLK R10 A3 R11 A6 R12 A9 Notes: 1. Signal names are based on configured functionality. Most connections supply a single signal. Some connections provide a signal with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is deasserted, but act as interrupt lines during operation. Some signals have configurable polarity ...

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... N15 A21 M14 A22 M15 A23 M16 A3 R10 A4 T11 A5 P10 A6 R11 A7 T12 A8 P11 A9 R12 AA0 AA1 3-18 DSP56301 MAP-BGA Signal Identification by Name Signal Name AA2 N9 AA3 BB BCLK BCLK CAS CLKOUT D0 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 ...

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... Table 3-4. DSP56301 MAP-BGA Signal Identification by Name (Continued) Pin Signal Name No. GND GND GND GND J10 GND J11 GND GND GND GND GND K10 GND K11 GND GND GND GND GND L10 GND L11 GND GND GND GND GND P1 GND P HA0 HA1 ...

Page 98

... Packaging Table 3-4. DSP56301 MAP-BGA Signal Identification by Name (Continued) Pin Signal Name No. HC3 C11 HCLK HD0 HD1 HD10 HD11 B10 HD12 A10 HD13 C10 HD14 B11 HD15 A11 HD16 A12 HD17 B12 HD18 C12 HD19 A13 HD2 HD20 D12 HD21 B13 HD22 ...

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... Table 3-4. DSP56301 MAP-BGA Signal Identification by Name (Continued) Pin Signal Name No. NC R15 NC R16 NC NC T15 NMI PB0 PB1 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 C11 PB2 PB20 PB21 PB22 PB23 PB3 PB4 PB5 Freescale Semiconductor Signal Name ...

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... Packaging Table 3-4. DSP56301 MAP-BGA Signal Identification by Name (Continued) Pin Signal Name No. TRST TXD V D10 CC V D11 E10 CC V E11 CC V E12 CC V E13 F12 Note: NC stands for Not Connected. The following pin groups are shorted to each other: — ...

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... MAP-BGA Package Mechanical Drawing Figure 3-6. DSP56301 Mechanical Information, 252-pin MAP-BGA Package Freescale Semiconductor Notes: 1. Dimensions are in millimeters. 2. Interpret dimensions and tolerances per ASME Y14.5M, 1994. 3. Dimension b is measured at the maximum solder ball diameter, parallel to datum plane Z. 4. Datum Z (seating plane) is defined by the spherical crowns of the solder balls ...

Page 102

... Packaging 3-24 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

Page 103

... Freescale Semiconductor , in °C can be obtained from this equation × θ θ For example, the user can change the air flow around the device, add θCA do not satisfactorily answer whether the thermal θJA DSP56301 Technical Data, Rev 4-1 ...

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... GND and V CC and circuits. GND , , ). TMS GND CCP P and RESET DSP56301 Technical Data, Rev – T )/P . This value gives a better estimate pin on the DSP and from the V CC and GND , , IRQA IRQB IRQC , and pins ...

Page 105

... Freescale Semiconductor × Example 1. Current Consumption – × × × 3 5.48 mA max) value reflects the typical possible switching of the internal buses on best- DSP56301 Technical Data, Rev. 10 Power Consumption Considerations signal should be supplied before EXTAL never CC ) value CCItyp 4-3 ...

Page 106

... The phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed values. 4-4 ⁄ ⁄ MHz = I – – typF2 typF1 is 0.5 percent. If the rate of change of the frequency of EXTAL DSP56301 Technical Data, Rev slow EXTAL Freescale Semiconductor ...

Page 107

... Area w.s (SSRAM) ; Default: 1 w.s (SRAM) ; movep #$0d0000,x:M_PCTL; XTAL disable ; PLL enable ; CLKOUT disable ; ;Load the program ; move #INT_PROG,r0 move #PROG_START,r1 do #(PROG_END-PROG_START),PLOAD_LOOP move p:(r1)+,x0 move x0,p:(r0)+ nop PLOAD_LOOP ; ; Load the X-data ; move #INT_XDAT,r0 move #XDAT_START,r1 Freescale Semiconductor * * DSP56301 Technical Data, Rev A-1 ...

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... PROG_END nop nop XDAT_START ; org x:0 dc $262EB9 dc $86F2FE dc $E56A5F dc $616CAC dc $8FFD75 dc $9210A dc $A06D7B dc $CEA798 dc $8DFBF1 dc $A063D6 A-2 ; ebd y:(r4)+,y1 y:(r4)+,y0 y:(r4)+,y0 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

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... XDAT_END YDAT_START ; org y:0 dc $5B6DA dc $C3F70B Freescale Semiconductor DSP56301 Technical Data, Rev. 10 A-3 ...

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... A-4 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

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... YDAT_END ;************************************************************************** ; ; EQUATES for DSP56301 I/O registers and ports ; Reference: DSP56301 Specifications Revision 3. Last update: November 15 1993 ; Changes: GPIO for ports C,D and E, ; HI32 ; DMA status reg ; ; AAR ; SCI registers address ; SSI registers addr. + split TSR from SSISR ; December 19 1993 (cosmetic - page and opt directives) ...

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... Host PCI Address Register Bit Flags M_ARL EQU $00ffff; DSP PCI Transaction Address (Low) M_C EQU $0f0000; PCI Bus Command M_BE EQU $f00000; PCI Byte Enables ; DSP Status Register Bit Flags M_HCP EQU 0 ; Host Command pending A-6 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

Page 113

... M_WDS1 EQU 1 ; Word Select 1 M_WDS2 EQU 2 ; Word Select 2 M_SSFTD EQU 3 ; SCI Shift Direction M_SBK EQU 4 ; Send Break M_WAKE EQU 5 ; Wakeup Mode Select M_RWU EQU 6 ; Receiver Wakeup Enable M_WOMS EQU 7 ; Wired-OR Mode Select Freescale Semiconductor DSP56301 Technical Data, Rev. 10 A-7 ...

Page 114

... M_TSR1 EQU $FFFFA9; SSI1 Time Slot Register M_RX1 EQU $FFFFA8; SSI1 Receive Data Register M_SSISR1 EQU $FFFFA7; SSI1 Status Register M_CRB1 EQU $FFFFA6; SSI1 Control Register B M_CRA1 EQU $FFFFA5; SSI1 Control Register A M_TSMA1 EQU $FFFFA4; SSI1 Transmit Slot Mask Register A A-8 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

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... Transmitter Underrun Error FLag M_ROE EQU 5 ; Receiver Overrun Error Flag M_TDE EQU 6 ; Transmit Data Register Empty M_RDF EQU 7 ; Receive Data Register Full ; SSI Transmit Slot Mask Register A M_SSTSA EQU $FFFF ; SSI Transmit Slot Bits Mask A (TS0-TS15) Freescale Semiconductor DSP56301 Technical Data, Rev. 10 A-9 ...

Page 116

... M_D3L0 EQU 18 ; DMA3 Interrupt Priority Level (low) M_D3L1 EQU 19 ; DMA3 Interrupt Priority Level (high) M_D4L EQU $300000; DMA4 Interrupt priority Level Mask M_D4L0 EQU 20 ; DMA4 Interrupt Priority Level (low) M_D4L1 EQU 21 ; DMA4 Interrupt Priority Level (high) A-10 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

Page 117

... M_TPCR EQU $FFFF82 ; TIMER Prescalar Count Register ; Timer Control/Status Register Bit Flags M_TE EQU 0 ; Timer Enable M_TOIE EQU 1 ; Timer Overflow Interrupt Enable M_TCIE EQU 2 ; Timer Compare Interrupt Enable Freescale Semiconductor Interrupt Priority Level Mask Interrupt Priority Level (low) Interrupt Priority Level (high) DSP56301 Technical Data, Rev. 10 A-11 ...

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... M_DCR1 EQU $FFFFE8; DMA1 Control Register ; Register Addresses Of DMA2 M_DSR2 EQU $FFFFE7; DMA2 Source Address Register M_DDR2 EQU $FFFFE6; DMA2 Destination Address Register M_DCO2 EQU $FFFFE5; DMA2 Counter M_DCR2 EQU $FFFFE4; DMA2 Control Register ; Register Addresses Of DMA4 A-12 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

Page 119

... DMA Channel Transfer Done Status 3 M_DTD4 EQU 4 ; DMA Channel Transfer Done Status 4 M_DTD5 EQU 5 ; DMA Channel Transfer Done Status 5 M_DACT EQU 8 ; DMA Active State M_DCH EQU $E00 ; DMA Active Channel Mask (DCH0-DCH2) M_DCH0 EQU 9 ; DMA Active Channel 0 Freescale Semiconductor DSP56301 Technical Data, Rev. 10 A-13 ...

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... DRAM Control Register M_BCW EQU $ Page Wait States Bits Mask (BCW0-BCW1) M_BRW EQU $C ; Out Of Page Wait States Bits Mask (BRW0-BRW1) M_BPS EQU $300 ; DRAM Page Size Bits Mask (BPS0-BPS1) M_BPLE EQU 11 ; Page Logic Enable A-14 DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

Page 121

... M_BEN EQU 10 ; Burst Enable M_TAS EQU Synchronize Select M_BRT EQU 12 ; Bus Release Timing M_XYS EQU 16 ; Stack Extension space select bit in OMR. M_EUN EQU 17 ; Extensed stack UNderflow flag in OMR. M_EOV EQU 18 ; Extended stack OVerflow flag in OMR. Freescale Semiconductor DSP56301 Technical Data, Rev. 10 A-15 ...

Page 122

... I_TIM0OF EQU I_VEC+$26 A-16 ; Hardware RESET ; Stack Error ; Illegal Instruction ; Debug Request ; Trap ; Non Maskable Interrupt ; IRQA ; IRQB ; IRQC ; IRQD ; DMA Channel 0 ; DMA Channel 1 ; DMA Channel 2 ; DMA Channel 3 ; DMA Channel 4 ; DMA Channel 5 ; TIMER 0 compare ; TIMER 0 overflow DSP56301 Technical Data, Rev. 10 Freescale Semiconductor ...

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... Host PCI Transaction Abort ; Host PCI Parity Error ; Host PCI Transfer Complete ; Host PCI Master Receive ; Host Slave Receive ; Host PCI Master Transmit ; Host Slave Transmit ; Host PCI Master Address ; Host Command/Host NMI (Default) ; last address of interrupt vector space DSP56301 Technical Data, Rev. 10 A-17 ...

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... Tai Po, N.T. Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Document Order No.: DSP56301 Rev. 10 7/2006 Pin Package Type Frequency Count (MHz) 208 252 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products ...