FS6131-01 AMI Semiconductor, FS6131-01 Datasheet

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... External feedback loop capability allows genlocking • Tunable VCXO loop for jitter attenuation 2.0 Description The FS6131- monolithic CMOS clock generator/regenerator IC designed to minimize cost and component count in a variety of 2 electronic systems. Via the I C-bus interface, the FS6131-01 can be adapted to many clock generation requirements. ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC XTUNE (optional) XCT[3:0], XLVTEN XIN VCXO XOUT (optional) REFDIV[11:0] REF 0 Reference (f ) REF Divider REFDSRC FBK ADDR SCL Registers Interface SDA Table 1: Pin Descriptions Key Analog Input Analog Output Digital Input; DI DIO = Digital Input/Output; DI-3 = Three-Level Digital Input Digital Output Power/Ground Active Low pin ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC 4.0 Functional Block Description 4.1 Main Loop PLL The main loop phase locked loop (ML-PLL standard phase- and frequency- locked loop architecture. As shown in Figure 2, the ML-PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled oscillator (VCO), a feedback divider, and a post divider ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC To understand the operation, refer to Figure 3. The M-counter (with a modulus cascaded with the dual-modulus pre-scaler. If the prescaler modulus were fixed at N, the overall modulus of the feedback divider chain would be MXN. However, the A-counter causes the pre-scaler modulus to be altered to N+1 for the first A outputs of the pre-scaler ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC The post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to the variety of output clock speeds that the device is required to generate. Second, it changes the basic PLL equation to The extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies must be achieved exactly ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC 4.2.2 Phase Alignment To maintain a fixed phase relation between input and output clocks, the post divider must be placed inside the feedback loop. The source for the feedback divider is obtained from the output of the post divider via the FBKDSRC switch. In addition, the feedback divider must be dividing at a multiple of the post divider ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC 4.3 Loop Gain Analysis For applications where an external loop filter is required, the following analysis example can be used to determine loop gain and stability. The loop gain of a PLL is the product of all of the gains within the loop. ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC The loop phase angle is: AMI Semiconductor – Rev. 3.0, Jan. 08 www.amis.com Specifications subject to change without notice 100 10 1 0.1 0.01 0.1kHz 1kHz 10kHz Frequency ( Figure 8: Loop Gain vs. Frequency [ π Θ = arg LOOP -100° ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC A Nyquist plot of gain vs. amplitude is shown below. 4.4 Voltage-Controlled Crystal Oscillator The VCXO provides a tunable, low-jitter frequency reference for the rest of the FS6131 system components. Loading capacitance for the crystal is internal to the device. No external components (other than the resonator itself) are required for operation of the VCXO. ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC 4.4.1 VCXO Tuning The VCXO may be coarse tuned by a programmable adjustment of the crystal load capacitance via the XCT[3:0] control bits. See Table 11 for the control code and the associated loading capacitance. The actual amount of frequency warping caused by the tuning capacitance will depend on the crystal used. The VCXO tuning capacitance includes an external 6pF load capacitance (12pF from the XIN pin to ground and 12pF from the XOUT pin to ground) ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC 4.5.1.1 Crystal Loop Lock Status Flag To enable this mode, clear the STAT[1] and STAT[0] bits to zero. If the CMOS bit is set to one, the LOCK/IPRG pin will be low if the crystal loop becomes unlocked. The flag is always available under software control by reading back the STAT[1] bit, which is overwritten with the status flag (low = unlocked) in this mode (see Table 6) ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC 2 5.0 I C-bus Control Interface This device is a read/write slave device meeting all Philips I controlled by a master device that generates the serial clock SCL, controls bus access and generates the START and STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC 2 5.2 I C-bus Operation All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital interface. The crystal oscillator does not have to run for communication to occur. The device accepts the following I C-bus commands. ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC 5.2.5 Sequential Register Read Procedure Sequential read operations allow the master to read from each register in order. The register pointer is automatically incremented by one after each read. This procedure is more efficient than the random register read if several registers must be read. ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC S DEVICE ADDRESS 7-bit Receive Device Address START Command S DEVICE ADDRESS W 7-bit Receive Device Address START Command From bus host to device S DEVICE ADDRESS W A REGISTER ADDRESS 7-bit Receive Register Address Device Address Acknowledge START ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC 6.0 Programming Information All register bits are cleared to zero on power-up. All register bits may be read back as written except STAT[1] (Bit 63). Table 3: Register Map Address Bit 7 Bit 6 STAT[1] STAT[0] (Bit 63) (Bit 62 Crystal Loop – Lock Status Byte Crystal Loop – ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Table 4: Device Configuration Bits Name Description REFerence Divider SouRCe REFDSRC Bit = 0 (Bit 12) Bit = 1 main loop SHUT down select SHUT Bit = 0 (Bit 13) Bit = 1 Phase Detector REFerence source PDREF Bit = 0 (Bit 14) Bit = 1 Phase Detector FeedBacK source ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Table 5: LOCK/IPRG Pin Configuration Bits Name Description Crystal Loop Lock STATus Mode / Main Loop Phase Align STATus mode (see also Table 6) Bit Bit STAT[1:0] Bit (Bits 63-62) Bit Bit Bit ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Table 8: Divider Control Bits Name Description REFDIV[11:0] REFerence DIVider (N (Bits 11-0) FeedBacK DIVider (N FBKDIV[13:0] FBKDIV[2:0] (Bits 37-24) FBKDIV[13:3] POST Divider #1 (N Bit Bit Bit POST1[1:0] Bit (Bits 17-16) Bit Bit Bit ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Table 9: Crystal Loop Tuning Bits Name Description Crystal Loop Charge Pump current Bit Bit Bit XLCP[1:0] Bit (Bits 53-52) Bit Bit Bit Bit XLROM[2:0] Crystal Loop Divider ROM select and Crystal Oscillator Power-Down (Bits 51-49) (see Error! Reference source not found ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Table 11: VCXO Coarse Running Capacitance XCT[3] XCT[2] XCT[ 7.0 Electrical Specifications Table 12: Absolute Maximum Ratings Parameter Supply Voltage ground) ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Table 13: Operating Conditions Parameter Supply Voltage Ambient Operating Temperature Range Crystal Resonator Frequency Crystal Resonator Load Capacitance Crystal Resonator Motional Capacitance Serial Data Transfer Rate PECL Mode Programming Current (LOCK/IPRG Pin High-Level Input Current) ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Table 14: DC Electrical Specifications (Continued) Parameter Loop Filter Input (EXTLF) Input Leakage Current High-Level Output Source Current Low-Level Output Sink Current Crystal Oscillator Input (XIN) Threshold Bias Voltage High-Level Input Current Low-Level Input Current ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Table 14: DC Electrical Specifications (Continued) Parameter Clock Outputs, CMOS Mode (CLKN, CLKP) High-Level Output Source Current Low-Level Output Sink Current Output Impedance * Short Circuit Source Current * Short Circuit Sink Current * Clock Outputs, PECL Mode (CLKN, CLKP) ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Table 15: AC Specifications (Continued) Parameter Symbol Divider Modulus Feedback Divider N F Reference Divider Post Divider Clock Output (CLKP, CLKN) Duty Cycle * t Jitter, Long Term (σ (τ)) * j(LT) y Jitter, Period (peak-peak) t j(∆P) ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC SCL t su:STA SDA START t F SCL t su:STA t hd:STA SDA IN SDA OUT AMI Semiconductor – Rev. 3.0, Jan. 08 www.amis.com Specifications subject to change without notice t hd:STA ADDRESS OR DATA CAN DATA VALID CHANGE Figure 17: Bus Timing Data t HI ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Table 17: CLKP, CLKN Clock Outputs (CMOS Mode) Low Drive Current (mA) Voltage (V) Min. Typ. Max 103 115 2 122 2 130 2 ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC 8.0 Package Information for Both ‘Green’/’ROHS’ and ‘Non-Green’ Table 19: 16-pin SOIC (0.150") Package Dimensions Dimension Inches Millimeters Min. Max. Min. A 0.061 0.068 1.55 A1 0.004 0.0098 0.102 A2 0.055 0.061 1.40 B 0.013 0.019 0.33 0.007 C 0.0098 ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC 10.0 Demonstration Software MS Windows® based software is available from AMIS that illustrates the capabilities of the FS6131. 10.1 Software Requirements • PC running MS Windows 95, 98, 98SE, ME, NT4, 2000, XP Home or Professional Editions. • 2.0MB available space on hard drive C: 10.2 Demo Program Operation Run the fs6131.exe program. A warning message will appear stating that the hardware is not connected. Click “ ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC 10.2.1 Device Mode The device mode block presets the demo program to program the FS6131 either as a frequency synthesizer (a stand alone clock generator line-locked or genlock clock generator. Frequency Synthesis: For use as a stand alone clock generator. Note that the reference source is the on-chip crystal oscillator, the expected crystal frequency is 27MHz, and the voltage tune in the crystal oscillator (i ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC 10.2.3 Example: Line-Locked Mode Selecting the line-locked/genlock option in the Device Mode block changes the program default settings. The Reference Source changes to the REF pin input, and a block appears to permit entry of the REF input frequency in MHz. A Desired Multiple block allows entry of the reference frequency multiplying factor used to generate the output frequency ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Table 21: Sample Text Output AMIS - FS6131 Solution Text File Created: Today’s Date, Today’s Time Line-Locked / Genlock Mode Desired Multiple = 800 Source = 0.0315MHz Reference Pin External Loop Filter C1 = 4700pF R = 47kOhms Crystal Oscillator Voltage Tune Disabled ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC 11.1.1 Example Calculation In PECL mode, the output driver does not source current, so the V the equation where R is the pull-up resistor the pull-down resistor and The resistor ratio must also match the line impedance via the equation where z is the line impedance ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC However, the full signal amplitude may take up to twice as long as the propagation delay of the line to develop, reducing noise immunity during the half-amplitude period. Note that the voltage at the receive end must add signal amplitude that meets the receiver switching thresholds ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC 12.0 Device Application: Stand-Alone Clock Generation The length of the reference and feedback dividers, their granularity and the flexibility of the post divider make the FS6131 the most flexible monolithic stand-alone PLL clock generation device available. The effective block diagram of the FS6131 when programmed for stand-alone mode is shown in Figure 25 ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Next, express the output and input frequencies as a ratio of f Simplifying the above equation yields Deciding how to apportion the denominator integers between the reference divider and the post divider is an iterative process. To obtain the best performance, the VCO should be operated at the highest frequency possible without exceeding its upper limit of 230MHz ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC 13.0 Device Application: Line-Locked Clock Generation Line-locked clock generation, as used here, refers to the process of synthesizing a clock frequency that is some integer multiple of the horizontal line frequency in a graphics system. The FS6131 is easily configured to perform that function, as shown in Figure 26. ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC However, the 31.5kHz line reference signal is too low in frequency for the internal loop filter to be used. A series combination of a 0.015mF capacitor and a 15kW resistor from power (V in parallel with the combination may improve the filter performance. ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC 14.0 Device Application: Genlocking Genlocking refers to the process of synchronizing the horizontal sync pulses (HSYNC target graphics system to the HSYNC of a source graphics system genlocked mode, the FS6131 increases (or decreases) the frequency of the VCO until the FBK input is frequency matched and phase-aligned to the frequency applied to the REF input ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC The output clock frequency is calculated as For best performance, program the post divider (N 70MHz but less than 230MHz. The VCO frequency (f Selecting the post divider modulus avoid divider values from becoming too large. The settings place the VCO frequency at about 72MHz. ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC 15.0 Device Application: Telecom Clock Regenerator The FS6131 can be used as a clock regenerator as shown in Figure 28. This mode uses the VCXO in its own phase-locked loop, referred to as the crystal loop. The VCXO provides a "de-jittered" multiple of the reference frequency at the REF pin (usually 8kHz in telecom applications) for use by the main loop. In essence, the crystal loop " ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC The goal is to choose the highest crystal frequency from Table 10 that generates the smallest value of N The equation establishing the output frequency (f where N is the feedback divider modulus. F Choose a few different crystal frequencies from Table 10 and factor both the input VCXO and output clock frequencies into prime numbers ...

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... FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC 16.0 Company or Product Inquiries For more information about AMI Semiconductor, our technology and our product, visit our Web site at: . North America Tel: +1.208.233.4690 Fax: +1.208.234.6795 Europe Tel: +32 (0) 55.33.22.11 Fax: +32 (0) 55.31.81.12 Devices sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement ...